1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/memory/stm32-sdram.h>
8/{
9	clocks {
10		u-boot,dm-pre-reloc;
11	};
12
13	aliases {
14		/* Aliases for gpios so as to use sequence */
15		gpio0 = &gpioa;
16		gpio1 = &gpiob;
17		gpio2 = &gpioc;
18		gpio3 = &gpiod;
19		gpio4 = &gpioe;
20		gpio5 = &gpiof;
21		gpio6 = &gpiog;
22		gpio7 = &gpioh;
23		gpio8 = &gpioi;
24		gpio9 = &gpioj;
25		gpio10 = &gpiok;
26	};
27
28	soc {
29		u-boot,dm-pre-reloc;
30		pin-controller {
31			u-boot,dm-pre-reloc;
32		};
33
34		fmc: fmc@A0000000 {
35			compatible = "st,stm32-fmc";
36			reg = <0xA0000000 0x1000>;
37			clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
38			pinctrl-0 = <&fmc_pins>;
39			pinctrl-names = "default";
40			st,syscfg = <&syscfg>;
41			st,swp_fmc = <1>;
42			u-boot,dm-pre-reloc;
43
44			/*
45			 * Memory configuration from sdram datasheet
46			 * IS42S16400J
47			 */
48			bank1: bank@1 {
49			       st,sdram-control = /bits/ 8 <NO_COL_8
50							    NO_ROW_12
51							    MWIDTH_16
52							    BANKS_4
53							    CAS_3
54							    SDCLK_2
55							    RD_BURST_EN
56							    RD_PIPE_DL_0>;
57			       st,sdram-timing = /bits/ 8 <TMRD_3
58							   TXSR_7
59							   TRAS_4
60							   TRC_6
61							   TWR_2
62							   TRP_2 TRCD_2>;
63			       st,sdram-refcount = < 1386 >;
64		       };
65		};
66	};
67};
68
69&clk_hse {
70	u-boot,dm-pre-reloc;
71};
72
73&clk_lse {
74	u-boot,dm-pre-reloc;
75};
76
77&clk_i2s_ckin {
78	u-boot,dm-pre-reloc;
79};
80
81&pwrcfg {
82	u-boot,dm-pre-reloc;
83};
84
85&rcc {
86	u-boot,dm-pre-reloc;
87};
88
89&gpioa {
90	compatible = "st,stm32-gpio";
91	u-boot,dm-pre-reloc;
92};
93
94&gpiob {
95	compatible = "st,stm32-gpio";
96	u-boot,dm-pre-reloc;
97};
98
99&gpioc {
100	compatible = "st,stm32-gpio";
101	u-boot,dm-pre-reloc;
102};
103
104&gpiod {
105	compatible = "st,stm32-gpio";
106	u-boot,dm-pre-reloc;
107};
108
109&gpioe {
110	compatible = "st,stm32-gpio";
111	u-boot,dm-pre-reloc;
112};
113
114&gpiof {
115	compatible = "st,stm32-gpio";
116	u-boot,dm-pre-reloc;
117};
118
119&gpiog {
120	compatible = "st,stm32-gpio";
121	u-boot,dm-pre-reloc;
122};
123
124&gpioh {
125	compatible = "st,stm32-gpio";
126	u-boot,dm-pre-reloc;
127};
128
129&gpioi {
130	compatible = "st,stm32-gpio";
131	u-boot,dm-pre-reloc;
132};
133
134&gpioj {
135	compatible = "st,stm32-gpio";
136	u-boot,dm-pre-reloc;
137};
138
139&gpiok {
140	compatible = "st,stm32-gpio";
141	u-boot,dm-pre-reloc;
142};
143
144&pinctrl {
145	usart1_pins_a: usart1@0	{
146		u-boot,dm-pre-reloc;
147		pins1 {
148			u-boot,dm-pre-reloc;
149		};
150		pins2 {
151			u-boot,dm-pre-reloc;
152		};
153	};
154
155	fmc_pins: fmc@0 {
156		u-boot,dm-pre-reloc;
157		pins
158		{
159			pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
160				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
161				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
162				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
163				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
164				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
165				 <STM32_PINMUX('E',12, AF12)>, /* D09 */
166				 <STM32_PINMUX('E',11, AF12)>, /* D08 */
167				 <STM32_PINMUX('E',10, AF12)>, /* D07 */
168				 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
169				 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
170				 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
171				 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
172				 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
173				 <STM32_PINMUX('D',15, AF12)>, /* D01 */
174				 <STM32_PINMUX('D',14, AF12)>, /* D00 */
175
176				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
177				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
178
179				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
180				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
181
182				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
183				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
184				 <STM32_PINMUX('F',15, AF12)>, /* A09 */
185				 <STM32_PINMUX('F',14, AF12)>, /* A08 */
186				 <STM32_PINMUX('F',13, AF12)>, /* A07 */
187				 <STM32_PINMUX('F',12, AF12)>, /* A06 */
188				 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
189				 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
190				 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
191				 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
192				 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
193				 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
194
195				 <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
196				 <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
197				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
198				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
199				 <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
200				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
201			slew-rate = <2>;
202			u-boot,dm-pre-reloc;
203		};
204	};
205};
206