xref: /openbmc/u-boot/arch/arm/dts/stih410.dtsi (revision eb5ba3ae)
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih410-clock.dtsi"
10#include "stih407-family.dtsi"
11#include "stih410-pinctrl.dtsi"
12/ {
13	aliases {
14		bdisp0 = &bdisp0;
15	};
16
17	cpus {
18		cpu@0 {
19			st,syscfg = <&syscfg_core 0x8e0>;
20			st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
21			clocks = <&clk_m_a9>;
22			operating-points-v2 = <&cpu0_opp_table>;
23		};
24		cpu@1 {
25			clocks = <&clk_m_a9>;
26			operating-points-v2 = <&cpu0_opp_table>;
27		};
28	};
29
30	cpu0_opp_table: opp_table0 {
31		compatible = "operating-points-v2";
32		opp-shared;
33
34		opp@1500000000 {
35			opp-supported-hw = <0xffffffff  0xffffffff  0xffffffff>;
36			opp-hz = /bits/ 64 <1500000000>;
37			clock-latency-ns = <10000000>;
38			opp-suspend;
39		};
40		opp@1200000000 {
41			opp-supported-hw = <0xffffffff  0xffffffff  0xffffffff>;
42			opp-hz = /bits/ 64 <1200000000>;
43			clock-latency-ns = <10000000>;
44		};
45		opp@800000000 {
46			opp-supported-hw = <0xffffffff  0xffffffff  0xffffffff>;
47			opp-hz = /bits/ 64 <800000000>;
48			clock-latency-ns = <10000000>;
49		};
50		opp@400000000 {
51			opp-supported-hw = <0xffffffff  0xffffffff  0xffffffff>;
52			opp-hz = /bits/ 64 <400000000>;
53			clock-latency-ns = <10000000>;
54		};
55	};
56
57	soc {
58		syscfg_opp: @08a6583c {
59			compatible = "syscon";
60			reg = <0x08a6583c 0x8>;
61		};
62
63		usb2_picophy1: phy2 {
64			compatible = "st,stih407-usb2-phy";
65			#phy-cells = <0>;
66			st,syscfg = <&syscfg_core 0xf8 0xf4>;
67			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
68				 <&picophyreset STIH407_PICOPHY0_RESET>;
69			reset-names = "global", "port";
70
71			status = "disabled";
72		};
73
74		usb2_picophy2: phy3 {
75			compatible = "st,stih407-usb2-phy";
76			#phy-cells = <0>;
77			st,syscfg = <&syscfg_core 0xfc 0xf4>;
78			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
79				 <&picophyreset STIH407_PICOPHY1_RESET>;
80			reset-names = "global", "port";
81
82			status = "disabled";
83		};
84
85		ohci0: usb@9a03c00 {
86			compatible = "st,st-ohci-300x";
87			reg = <0x9a03c00 0x100>;
88			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
89			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
90				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
91			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
92				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
93			reset-names = "power", "softreset";
94			phys = <&usb2_picophy1>;
95			phy-names = "usb";
96
97			status = "disabled";
98		};
99
100		ehci0: usb@9a03e00 {
101			compatible = "st,st-ehci-300x";
102			reg = <0x9a03e00 0x100>;
103			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
104			pinctrl-names = "default";
105			pinctrl-0 = <&pinctrl_usb0>;
106			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
107				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
108			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
109				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
110			reset-names = "power", "softreset";
111			phys = <&usb2_picophy1>;
112			phy-names = "usb";
113
114			status = "disabled";
115		};
116
117		ohci1: usb@9a83c00 {
118			compatible = "st,st-ohci-300x";
119			reg = <0x9a83c00 0x100>;
120			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
121			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
122				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
123			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
124				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
125			reset-names = "power", "softreset";
126			phys = <&usb2_picophy2>;
127			phy-names = "usb";
128
129			status = "disabled";
130		};
131
132		ehci1: usb@9a83e00 {
133			compatible = "st,st-ehci-300x";
134			reg = <0x9a83e00 0x100>;
135			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
136			pinctrl-names = "default";
137			pinctrl-0 = <&pinctrl_usb1>;
138			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
139				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
140			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
141				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
142			reset-names = "power", "softreset";
143			phys = <&usb2_picophy2>;
144			phy-names = "usb";
145
146			status = "disabled";
147		};
148
149		sti-display-subsystem {
150			compatible = "st,sti-display-subsystem";
151			#address-cells = <1>;
152			#size-cells = <1>;
153
154			assigned-clocks	= <&clk_s_d2_quadfs 0>,
155					  <&clk_s_d2_quadfs 1>,
156					  <&clk_s_c0_pll1 0>,
157					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
158					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
159					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
160					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
161					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
162					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
163					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
164					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;
165
166			assigned-clock-parents = <0>,
167						 <0>,
168						 <0>,
169						 <&clk_s_c0_pll1 0>,
170						 <&clk_s_c0_pll1 0>,
171						 <&clk_s_d2_quadfs 0>,
172						 <&clk_s_d2_quadfs 1>,
173						 <&clk_s_d2_quadfs 0>,
174						 <&clk_s_d2_quadfs 0>,
175						 <&clk_s_d2_quadfs 0>,
176						 <&clk_s_d2_quadfs 0>;
177
178			assigned-clock-rates = <297000000>,
179					       <297000000>,
180					       <0>,
181					       <400000000>,
182					       <400000000>;
183
184			ranges;
185
186			sti-compositor@9d11000 {
187				compatible = "st,stih407-compositor";
188				reg = <0x9d11000 0x1000>;
189
190				clock-names = "compo_main",
191					      "compo_aux",
192					      "pix_main",
193					      "pix_aux",
194					      "pix_gdp1",
195					      "pix_gdp2",
196					      "pix_gdp3",
197					      "pix_gdp4",
198					      "main_parent",
199					      "aux_parent";
200
201				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
202					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
203					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
204					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
205					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
206					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
207					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
208					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
209					 <&clk_s_d2_quadfs 0>,
210					 <&clk_s_d2_quadfs 1>;
211
212				reset-names = "compo-main", "compo-aux";
213				resets = <&softreset STIH407_COMPO_SOFTRESET>,
214					 <&softreset STIH407_COMPO_SOFTRESET>;
215				st,vtg = <&vtg_main>, <&vtg_aux>;
216			};
217
218			sti-tvout@8d08000 {
219				compatible = "st,stih407-tvout";
220				reg = <0x8d08000 0x1000>;
221				reg-names = "tvout-reg";
222				reset-names = "tvout";
223				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
224				#address-cells = <1>;
225				#size-cells = <1>;
226				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
227						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
228						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
229						  <&clk_s_d0_flexgen CLK_PCM_0>,
230						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
231						  <&clk_s_d2_flexgen CLK_HDDAC>;
232
233				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
234							 <&clk_tmdsout_hdmi>,
235							 <&clk_s_d2_quadfs 0>,
236							 <&clk_s_d0_quadfs 0>,
237							 <&clk_s_d2_quadfs 0>,
238							 <&clk_s_d2_quadfs 0>;
239			};
240
241			sti_hdmi: sti-hdmi@8d04000 {
242				compatible = "st,stih407-hdmi";
243				#sound-dai-cells = <0>;
244				reg = <0x8d04000 0x1000>;
245				reg-names = "hdmi-reg";
246				interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
247				interrupt-names	= "irq";
248				clock-names = "pix",
249					      "tmds",
250					      "phy",
251					      "audio",
252					      "main_parent",
253					      "aux_parent";
254
255				clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
256					 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
257					 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
258					 <&clk_s_d0_flexgen CLK_PCM_0>,
259					 <&clk_s_d2_quadfs 0>,
260					 <&clk_s_d2_quadfs 1>;
261
262				hdmi,hpd-gpio = <&pio5 3>;
263				reset-names = "hdmi";
264				resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
265				ddc = <&hdmiddc>;
266			};
267
268			sti-hda@8d02000 {
269				compatible = "st,stih407-hda";
270				status = "disabled";
271				reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
272				reg-names = "hda-reg", "video-dacs-ctrl";
273				clock-names = "pix",
274					      "hddac",
275					      "main_parent",
276					      "aux_parent";
277				clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
278					 <&clk_s_d2_flexgen CLK_HDDAC>,
279					 <&clk_s_d2_quadfs 0>,
280					 <&clk_s_d2_quadfs 1>;
281			};
282
283			sti-dvo@8d00400 {
284				compatible = "st,stih407-dvo";
285				status = "disabled";
286				reg = <0x8d00400 0x200>;
287				reg-names = "dvo-reg";
288				clock-names = "dvo_pix",
289					      "dvo",
290					      "main_parent",
291					      "aux_parent";
292				clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>,
293					 <&clk_s_d2_flexgen CLK_DVO>,
294					 <&clk_s_d2_quadfs 0>,
295					 <&clk_s_d2_quadfs 1>;
296				pinctrl-names = "default";
297				pinctrl-0 = <&pinctrl_dvo>;
298			};
299
300			sti-hqvdp@9c000000 {
301				compatible = "st,stih407-hqvdp";
302				reg = <0x9C00000 0x100000>;
303				clock-names = "hqvdp", "pix_main";
304				clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
305					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
306				reset-names = "hqvdp";
307				resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
308				st,vtg = <&vtg_main>;
309			};
310		};
311
312		bdisp0:bdisp@9f10000 {
313			compatible = "st,stih407-bdisp";
314			reg = <0x9f10000 0x1000>;
315			interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
316			clock-names = "bdisp";
317			clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
318		};
319
320		hva@8c85000 {
321			compatible = "st,st-hva";
322			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
323			reg-names = "hva_registers", "hva_esram";
324			interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
325				     <GIC_SPI 59 IRQ_TYPE_NONE>;
326			clock-names = "clk_hva";
327			clocks = <&clk_s_c0_flexgen CLK_HVA>;
328		};
329
330		thermal@91a0000 {
331			compatible = "st,stih407-thermal";
332			reg = <0x91a0000 0x28>;
333			clock-names = "thermal";
334			clocks = <&clk_sysin>;
335			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
336		};
337
338		g1@8c80000 {
339			compatible = "st,g1";
340			reg = <0x8c80000 0x194>;
341			interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
342		};
343
344		temp0{
345			compatible = "st,stih407-thermal";
346			reg = <0x91a0000 0x28>;
347			clock-names = "thermal";
348			clocks = <&clk_sysin>;
349			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
350		};
351
352		delta0 {
353			compatible = "st,delta";
354			clock-names = "delta", "delta-st231", "delta-flash-promip";
355			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
356			    <&clk_s_c0_flexgen CLK_ST231_DMU>,
357			    <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
358		};
359
360		h264pp0: h264pp@8c00000 {
361			compatible = "st,h264pp";
362			reg = <0x8c00000 0x20000>;
363			interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
364			clock-names = "clk_h264pp_0";
365			clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
366		};
367
368		mali: mali@09f00000 {
369			compatible	= "arm,mali-400";
370			reg		= <0x09f00000 0x10000>;
371			interrupts	= <GIC_SPI 49 IRQ_TYPE_NONE>,
372					  <GIC_SPI 50 IRQ_TYPE_NONE>,
373					  <GIC_SPI 41 IRQ_TYPE_NONE>,
374					  <GIC_SPI 45 IRQ_TYPE_NONE>,
375					  <GIC_SPI 42 IRQ_TYPE_NONE>,
376					  <GIC_SPI 46 IRQ_TYPE_NONE>,
377					  <GIC_SPI 43 IRQ_TYPE_NONE>,
378					  <GIC_SPI 47 IRQ_TYPE_NONE>,
379					  <GIC_SPI 44 IRQ_TYPE_NONE>,
380					  <GIC_SPI 48 IRQ_TYPE_NONE>;
381			interrupt-names = "IRQGP",
382					  "IRQGPMMU",
383					  "IRQPP0",
384					  "IRQPPMMU0",
385					  "IRQPP1",
386					  "IRQPPMMU1",
387					  "IRQPP2",
388					  "IRQPPMMU2",
389					  "IRQPP3",
390					  "IRQPPMMU3";
391			clock-names	= "gpu-clk";
392			clocks		= <&clk_s_c0_flexgen CLK_ICN_GPU>;
393			reset-names	= "gpu";
394			resets		= <&softreset STIH407_GPU_SOFTRESET>;
395		};
396
397		delta0 {
398			compatible = "st,st-delta";
399			clock-names = "delta",
400				      "delta-st231",
401				      "delta-flash-promip";
402			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
403				 <&clk_s_c0_flexgen CLK_ST231_DMU>,
404				 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
405		};
406
407		h264pp0: h264pp@8c00000 {
408			compatible = "st,h264pp";
409			reg = <0x8c00000 0x20000>;
410			interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
411			clock-names = "clk_h264pp_0";
412			clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
413		};
414
415		mali: mali@09f00000 {
416			compatible	= "arm,mali-400";
417			reg		= <0x09f00000 0x10000>;
418			interrupts	= <GIC_SPI 49 IRQ_TYPE_NONE>,
419					  <GIC_SPI 50 IRQ_TYPE_NONE>,
420					  <GIC_SPI 41 IRQ_TYPE_NONE>,
421					  <GIC_SPI 45 IRQ_TYPE_NONE>,
422					  <GIC_SPI 42 IRQ_TYPE_NONE>,
423					  <GIC_SPI 46 IRQ_TYPE_NONE>,
424					  <GIC_SPI 43 IRQ_TYPE_NONE>,
425					  <GIC_SPI 47 IRQ_TYPE_NONE>,
426					  <GIC_SPI 44 IRQ_TYPE_NONE>,
427					  <GIC_SPI 48 IRQ_TYPE_NONE>;
428			interrupt-names = "IRQGP",
429					  "IRQGPMMU",
430					  "IRQPP0",
431					  "IRQPPMMU0",
432					  "IRQPP1",
433					  "IRQPPMMU1",
434					  "IRQPP2",
435					  "IRQPPMMU2",
436					  "IRQPP3",
437					  "IRQPPMMU3";
438			clock-names	= "gpu-clk";
439			clocks		= <&clk_s_c0_flexgen CLK_ICN_GPU>;
440			reset-names	= "gpu";
441			resets		= <&softreset STIH407_GPU_SOFTRESET>;
442		};
443
444		hva@8c85000{
445			compatible = "st,st-hva";
446			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
447			reg-names = "hva_registers", "hva_esram";
448			interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
449				     <GIC_SPI 59 IRQ_TYPE_NONE>;
450			clock-names = "clk_hva";
451			clocks = <&clk_s_c0_flexgen CLK_HVA>;
452		};
453	};
454};
455