1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2018 Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 compatible = "altr,socfpga-stratix10"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a53", "arm,armv8"; 21 device_type = "cpu"; 22 enable-method = "psci"; 23 reg = <0x0>; 24 }; 25 26 cpu1: cpu@1 { 27 compatible = "arm,cortex-a53", "arm,armv8"; 28 device_type = "cpu"; 29 enable-method = "psci"; 30 reg = <0x1>; 31 }; 32 33 cpu2: cpu@2 { 34 compatible = "arm,cortex-a53", "arm,armv8"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x2>; 38 }; 39 40 cpu3: cpu@3 { 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x3>; 45 }; 46 }; 47 48 pmu { 49 compatible = "arm,armv8-pmuv3"; 50 interrupts = <0 120 8>, 51 <0 121 8>, 52 <0 122 8>, 53 <0 123 8>; 54 interrupt-affinity = <&cpu0>, 55 <&cpu1>, 56 <&cpu2>, 57 <&cpu3>; 58 interrupt-parent = <&intc>; 59 }; 60 61 psci { 62 compatible = "arm,psci-0.2"; 63 method = "smc"; 64 }; 65 66 intc: intc@fffc1000 { 67 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 68 #interrupt-cells = <3>; 69 interrupt-controller; 70 reg = <0x0 0xfffc1000 0x0 0x1000>, 71 <0x0 0xfffc2000 0x0 0x2000>, 72 <0x0 0xfffc4000 0x0 0x2000>, 73 <0x0 0xfffc6000 0x0 0x2000>; 74 }; 75 76 soc { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 compatible = "simple-bus"; 80 device_type = "soc"; 81 interrupt-parent = <&intc>; 82 ranges = <0 0 0 0xffffffff>; 83 u-boot,dm-pre-reloc; 84 85 clkmgr@ffd1000 { 86 compatible = "altr,clk-mgr"; 87 reg = <0xffd10000 0x1000>; 88 }; 89 90 gmac0: ethernet@ff800000 { 91 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 92 reg = <0xff800000 0x2000>; 93 interrupts = <0 90 4>; 94 interrupt-names = "macirq"; 95 mac-address = [00 00 00 00 00 00]; 96 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 97 reset-names = "stmmaceth"; 98 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 99 status = "disabled"; 100 }; 101 102 gmac1: ethernet@ff802000 { 103 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 104 reg = <0xff802000 0x2000>; 105 interrupts = <0 91 4>; 106 interrupt-names = "macirq"; 107 mac-address = [00 00 00 00 00 00]; 108 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 109 reset-names = "stmmaceth"; 110 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 111 status = "disabled"; 112 }; 113 114 gmac2: ethernet@ff804000 { 115 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 116 reg = <0xff804000 0x2000>; 117 interrupts = <0 92 4>; 118 interrupt-names = "macirq"; 119 mac-address = [00 00 00 00 00 00]; 120 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 121 reset-names = "stmmaceth"; 122 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 123 status = "disabled"; 124 }; 125 126 gpio0: gpio@ffc03200 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 compatible = "snps,dw-apb-gpio"; 130 reg = <0xffc03200 0x100>; 131 resets = <&rst GPIO0_RESET>; 132 status = "disabled"; 133 134 porta: gpio-controller@0 { 135 compatible = "snps,dw-apb-gpio-port"; 136 gpio-controller; 137 #gpio-cells = <2>; 138 snps,nr-gpios = <24>; 139 reg = <0>; 140 interrupt-controller; 141 #interrupt-cells = <2>; 142 interrupts = <0 110 4>; 143 bank-name = "porta"; 144 }; 145 }; 146 147 gpio1: gpio@ffc03300 { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "snps,dw-apb-gpio"; 151 reg = <0xffc03300 0x100>; 152 resets = <&rst GPIO1_RESET>; 153 status = "disabled"; 154 155 portb: gpio-controller@0 { 156 compatible = "snps,dw-apb-gpio-port"; 157 gpio-controller; 158 #gpio-cells = <2>; 159 snps,nr-gpios = <24>; 160 reg = <0>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 interrupts = <0 111 4>; 164 bank-name = "portb"; 165 }; 166 }; 167 168 i2c0: i2c@ffc02800 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "snps,designware-i2c"; 172 reg = <0xffc02800 0x100>; 173 interrupts = <0 103 4>; 174 resets = <&rst I2C0_RESET>; 175 reset-names = "i2c"; 176 status = "disabled"; 177 }; 178 179 i2c1: i2c@ffc02900 { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 compatible = "snps,designware-i2c"; 183 reg = <0xffc02900 0x100>; 184 interrupts = <0 104 4>; 185 resets = <&rst I2C1_RESET>; 186 reset-names = "i2c"; 187 status = "disabled"; 188 }; 189 190 i2c2: i2c@ffc02a00 { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 compatible = "snps,designware-i2c"; 194 reg = <0xffc02a00 0x100>; 195 interrupts = <0 105 4>; 196 resets = <&rst I2C2_RESET>; 197 reset-names = "i2c"; 198 status = "disabled"; 199 }; 200 201 i2c3: i2c@ffc02b00 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 compatible = "snps,designware-i2c"; 205 reg = <0xffc02b00 0x100>; 206 interrupts = <0 106 4>; 207 resets = <&rst I2C3_RESET>; 208 reset-names = "i2c"; 209 status = "disabled"; 210 }; 211 212 i2c4: i2c@ffc02c00 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 compatible = "snps,designware-i2c"; 216 reg = <0xffc02c00 0x100>; 217 interrupts = <0 107 4>; 218 resets = <&rst I2C4_RESET>; 219 reset-names = "i2c"; 220 status = "disabled"; 221 }; 222 223 mmc: dwmmc0@ff808000 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "altr,socfpga-dw-mshc"; 227 reg = <0xff808000 0x1000>; 228 interrupts = <0 96 4>; 229 fifo-depth = <0x400>; 230 resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; 231 u-boot,dm-pre-reloc; 232 status = "disabled"; 233 }; 234 235 ocram: sram@ffe00000 { 236 compatible = "mmio-sram"; 237 reg = <0xffe00000 0x100000>; 238 }; 239 240 rst: rstmgr@ffd11000 { 241 #reset-cells = <1>; 242 compatible = "altr,rst-mgr"; 243 reg = <0xffd11000 0x1000>; 244 altr,modrst-offset = <0x20>; 245 u-boot,dm-pre-reloc; 246 }; 247 248 spi0: spi@ffda4000 { 249 compatible = "snps,dw-apb-ssi"; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 reg = <0xffda4000 0x1000>; 253 interrupts = <0 99 4>; 254 resets = <&rst SPIM0_RESET>; 255 reg-io-width = <4>; 256 num-chipselect = <4>; 257 bus-num = <0>; 258 status = "disabled"; 259 }; 260 261 spi1: spi@ffda5000 { 262 compatible = "snps,dw-apb-ssi"; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 reg = <0xffda5000 0x1000>; 266 interrupts = <0 100 4>; 267 resets = <&rst SPIM1_RESET>; 268 reg-io-width = <4>; 269 num-chipselect = <4>; 270 bus-num = <0>; 271 status = "disabled"; 272 }; 273 274 sysmgr: sysmgr@ffd12000 { 275 compatible = "altr,sys-mgr", "syscon"; 276 reg = <0xffd12000 0x1000>; 277 }; 278 279 /* Local timer */ 280 timer { 281 compatible = "arm,armv8-timer"; 282 interrupts = <1 13 0xf08>, 283 <1 14 0xf08>, 284 <1 11 0xf08>, 285 <1 10 0xf08>; 286 }; 287 288 timer0: timer0@ffc03000 { 289 compatible = "snps,dw-apb-timer"; 290 interrupts = <0 113 4>; 291 reg = <0xffc03000 0x100>; 292 }; 293 294 timer1: timer1@ffc03100 { 295 compatible = "snps,dw-apb-timer"; 296 interrupts = <0 114 4>; 297 reg = <0xffc03100 0x100>; 298 }; 299 300 timer2: timer2@ffd00000 { 301 compatible = "snps,dw-apb-timer"; 302 interrupts = <0 115 4>; 303 reg = <0xffd00000 0x100>; 304 }; 305 306 timer3: timer3@ffd00100 { 307 compatible = "snps,dw-apb-timer"; 308 interrupts = <0 116 4>; 309 reg = <0xffd00100 0x100>; 310 }; 311 312 uart0: serial0@ffc02000 { 313 compatible = "snps,dw-apb-uart"; 314 reg = <0xffc02000 0x100>; 315 interrupts = <0 108 4>; 316 reg-shift = <2>; 317 reg-io-width = <4>; 318 resets = <&rst UART0_RESET>; 319 clock-frequency = <100000000>; 320 u-boot,dm-pre-reloc; 321 status = "disabled"; 322 }; 323 324 uart1: serial1@ffc02100 { 325 compatible = "snps,dw-apb-uart"; 326 reg = <0xffc02100 0x100>; 327 interrupts = <0 109 4>; 328 reg-shift = <2>; 329 reg-io-width = <4>; 330 resets = <&rst UART1_RESET>; 331 status = "disabled"; 332 }; 333 334 usbphy0: usbphy@0 { 335 #phy-cells = <0>; 336 compatible = "usb-nop-xceiv"; 337 status = "okay"; 338 }; 339 340 usb0: usb@ffb00000 { 341 compatible = "snps,dwc2"; 342 reg = <0xffb00000 0x40000>; 343 interrupts = <0 93 4>; 344 phys = <&usbphy0>; 345 phy-names = "usb2-phy"; 346 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 347 reset-names = "dwc2", "dwc2-ecc"; 348 status = "disabled"; 349 }; 350 351 usb1: usb@ffb40000 { 352 compatible = "snps,dwc2"; 353 reg = <0xffb40000 0x40000>; 354 interrupts = <0 94 4>; 355 phys = <&usbphy0>; 356 phy-names = "usb2-phy"; 357 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 358 reset-names = "dwc2", "dwc2-ecc"; 359 status = "disabled"; 360 }; 361 362 watchdog0: watchdog@ffd00200 { 363 compatible = "snps,dw-wdt"; 364 reg = <0xffd00200 0x100>; 365 interrupts = <0 117 4>; 366 resets = <&rst WATCHDOG0_RESET>; 367 u-boot,dm-pre-reloc; 368 status = "disabled"; 369 }; 370 371 watchdog1: watchdog@ffd00300 { 372 compatible = "snps,dw-wdt"; 373 reg = <0xffd00300 0x100>; 374 interrupts = <0 118 4>; 375 resets = <&rst WATCHDOG1_RESET>; 376 status = "disabled"; 377 }; 378 379 watchdog2: watchdog@ffd00400 { 380 compatible = "snps,dw-wdt"; 381 reg = <0xffd00400 0x100>; 382 interrupts = <0 125 4>; 383 resets = <&rst WATCHDOG2_RESET>; 384 status = "disabled"; 385 }; 386 387 watchdog3: watchdog@ffd00500 { 388 compatible = "snps,dw-wdt"; 389 reg = <0xffd00500 0x100>; 390 interrupts = <0 126 4>; 391 resets = <&rst WATCHDOG3_RESET>; 392 status = "disabled"; 393 }; 394 }; 395}; 396