1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
4 */
5
6#include "socfpga_cyclone5.dtsi"
7
8/ {
9	model = "samtec VIN|ING FPGA";
10	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
11
12	chosen {
13		bootargs = "console=ttyS0,115200";
14	};
15
16	aliases {
17		ethernet0 = &gmac1;
18		udc0 = &usb0;
19	};
20
21	memory {
22		name = "memory";
23		device_type = "memory";
24		reg = <0x0 0x40000000>; /* 1GB */
25	};
26
27	soc {
28		u-boot,dm-pre-reloc;
29	};
30};
31
32&gmac1 {
33	status = "okay";
34	phy-mode = "rgmii";
35
36	rxd0-skew-ps = <0>;
37	rxd1-skew-ps = <0>;
38	rxd2-skew-ps = <0>;
39	rxd3-skew-ps = <0>;
40	txen-skew-ps = <0>;
41	txc-skew-ps = <2600>;
42	rxdv-skew-ps = <0>;
43	rxc-skew-ps = <2000>;
44};
45
46&gpio0 {
47	status = "okay";
48};
49
50&gpio1 {
51	status = "okay";
52};
53
54&gpio2 {
55	status = "okay";
56};
57
58&i2c0 {
59	status = "okay";
60
61	rtc: rtc@68 {
62		compatible = "stm,m41t82";
63		reg = <0x68>;
64	};
65};
66
67&qspi {
68	status = "okay";
69	u-boot,dm-pre-reloc;
70
71	flash0: n25q128@0 {
72		u-boot,dm-pre-reloc;
73		#address-cells = <1>;
74		#size-cells = <1>;
75		compatible = "n25q128", "spi-flash";
76		reg = <0>;      /* chip select */
77		spi-max-frequency = <50000000>;
78		m25p,fast-read;
79		page-size = <256>;
80		block-size = <16>; /* 2^16, 64KB */
81		cdns,tshsl-ns = <50>;
82		cdns,tsd2d-ns = <50>;
83		cdns,tchsh-ns = <4>;
84		cdns,tslch-ns = <4>;
85	};
86
87	flash1: n25q00@1 {
88		u-boot,dm-pre-reloc;
89		#address-cells = <1>;
90		#size-cells = <1>;
91		compatible = "n25q00", "spi-flash";
92		reg = <1>;      /* chip select */
93		spi-max-frequency = <50000000>;
94		m25p,fast-read;
95		page-size = <256>;
96		block-size = <16>; /* 2^16, 64KB */
97		cdns,tshsl-ns = <50>;
98		cdns,tsd2d-ns = <50>;
99		cdns,tchsh-ns = <4>;
100		cdns,tslch-ns = <4>;
101	};
102};
103
104&usb0 {
105	status = "okay";
106};
107
108&usb1 {
109	status = "okay";
110};
111