1/* 2 * Copyright (C) 2015 Marek Vasut <marex@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include "socfpga_cyclone5.dtsi" 8 9/ { 10 model = "samtec VIN|ING FPGA"; 11 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 12 13 chosen { 14 bootargs = "console=ttyS0,115200"; 15 }; 16 17 aliases { 18 ethernet0 = &gmac1; 19 udc0 = &usb0; 20 }; 21 22 memory { 23 name = "memory"; 24 device_type = "memory"; 25 reg = <0x0 0x40000000>; /* 1GB */ 26 }; 27 28 soc { 29 u-boot,dm-pre-reloc; 30 }; 31}; 32 33&gmac1 { 34 status = "okay"; 35 phy-mode = "rgmii"; 36 37 rxd0-skew-ps = <0>; 38 rxd1-skew-ps = <0>; 39 rxd2-skew-ps = <0>; 40 rxd3-skew-ps = <0>; 41 txen-skew-ps = <0>; 42 txc-skew-ps = <2600>; 43 rxdv-skew-ps = <0>; 44 rxc-skew-ps = <2000>; 45}; 46 47&gpio0 { 48 status = "okay"; 49}; 50 51&gpio1 { 52 status = "okay"; 53}; 54 55&gpio2 { 56 status = "okay"; 57}; 58 59&i2c0 { 60 status = "okay"; 61 62 rtc: rtc@68 { 63 compatible = "stm,m41t82"; 64 reg = <0x68>; 65 }; 66}; 67 68&qspi { 69 status = "okay"; 70 u-boot,dm-pre-reloc; 71 72 flash0: n25q128@0 { 73 u-boot,dm-pre-reloc; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 compatible = "n25q128", "spi-flash"; 77 reg = <0>; /* chip select */ 78 spi-max-frequency = <50000000>; 79 m25p,fast-read; 80 page-size = <256>; 81 block-size = <16>; /* 2^16, 64KB */ 82 read-delay = <4>; /* delay value in read data capture register */ 83 tshsl-ns = <50>; 84 tsd2d-ns = <50>; 85 tchsh-ns = <4>; 86 tslch-ns = <4>; 87 }; 88 89 flash1: n25q00@1 { 90 u-boot,dm-pre-reloc; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 compatible = "n25q00", "spi-flash"; 94 reg = <1>; /* chip select */ 95 spi-max-frequency = <50000000>; 96 m25p,fast-read; 97 page-size = <256>; 98 block-size = <16>; /* 2^16, 64KB */ 99 read-delay = <4>; /* delay value in read data capture register */ 100 tshsl-ns = <50>; 101 tsd2d-ns = <50>; 102 tchsh-ns = <4>; 103 tslch-ns = <4>; 104 }; 105}; 106 107&usb0 { 108 status = "okay"; 109}; 110 111&usb1 { 112 status = "okay"; 113}; 114