1/* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include "socfpga_cyclone5.dtsi" 8 9/ { 10 model = "Altera SOCFPGA Cyclone V SoC Development Kit"; 11 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 12 13 chosen { 14 bootargs = "console=ttyS0,115200"; 15 }; 16 17 memory { 18 name = "memory"; 19 device_type = "memory"; 20 reg = <0x0 0x40000000>; /* 1GB */ 21 }; 22 23 aliases { 24 /* this allow the ethaddr uboot environmnet variable contents 25 * to be added to the gmac1 device tree blob. 26 */ 27 ethernet0 = &gmac1; 28 udc0 = &usb1; 29 }; 30 31 regulator_3_3v: 3-3-v-regulator { 32 compatible = "regulator-fixed"; 33 regulator-name = "3.3V"; 34 regulator-min-microvolt = <3300000>; 35 regulator-max-microvolt = <3300000>; 36 }; 37 38 soc { 39 u-boot,dm-pre-reloc; 40 }; 41}; 42 43&gmac1 { 44 status = "okay"; 45 phy-mode = "rgmii"; 46 47 rxd0-skew-ps = <0>; 48 rxd1-skew-ps = <0>; 49 rxd2-skew-ps = <0>; 50 rxd3-skew-ps = <0>; 51 txen-skew-ps = <0>; 52 txc-skew-ps = <2600>; 53 rxdv-skew-ps = <0>; 54 rxc-skew-ps = <2000>; 55}; 56 57&gpio1 { 58 status = "okay"; 59}; 60 61&i2c0 { 62 status = "okay"; 63 64 eeprom@51 { 65 compatible = "atmel,24c32"; 66 reg = <0x51>; 67 pagesize = <32>; 68 }; 69 70 rtc@68 { 71 compatible = "dallas,ds1339"; 72 reg = <0x68>; 73 }; 74}; 75 76&mmc0 { 77 status = "okay"; 78 u-boot,dm-pre-reloc; 79 80 cd-gpios = <&portb 18 0>; 81 vmmc-supply = <®ulator_3_3v>; 82 vqmmc-supply = <®ulator_3_3v>; 83}; 84 85&qspi { 86 status = "okay"; 87 u-boot,dm-pre-reloc; 88 89 flash0: n25q00@0 { 90 u-boot,dm-pre-reloc; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 compatible = "n25q00"; 94 reg = <0>; /* chip select */ 95 spi-max-frequency = <100000000>; 96 m25p,fast-read; 97 page-size = <256>; 98 block-size = <16>; /* 2^16, 64KB */ 99 read-delay = <4>; /* delay value in read data capture register */ 100 tshsl-ns = <50>; 101 tsd2d-ns = <50>; 102 tchsh-ns = <4>; 103 tslch-ns = <4>; 104 }; 105}; 106 107&usb1 { 108 status = "okay"; 109}; 110