1/*
2 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include "socfpga_cyclone5.dtsi"
8
9/ {
10	model = "Altera SOCFPGA Cyclone V SoC Development Kit";
11	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
12
13	chosen {
14		bootargs = "console=ttyS0,115200";
15	};
16
17	memory {
18		name = "memory";
19		device_type = "memory";
20		reg = <0x0 0x40000000>; /* 1GB */
21	};
22
23	aliases {
24		/* this allow the ethaddr uboot environmnet variable contents
25		 * to be added to the gmac1 device tree blob.
26		 */
27		ethernet0 = &gmac1;
28	};
29
30	regulator_3_3v: 3-3-v-regulator {
31		compatible = "regulator-fixed";
32		regulator-name = "3.3V";
33		regulator-min-microvolt = <3300000>;
34		regulator-max-microvolt = <3300000>;
35	};
36};
37
38&gmac1 {
39	status = "okay";
40	phy-mode = "rgmii";
41
42	rxd0-skew-ps = <0>;
43	rxd1-skew-ps = <0>;
44	rxd2-skew-ps = <0>;
45	rxd3-skew-ps = <0>;
46	txen-skew-ps = <0>;
47	txc-skew-ps = <2600>;
48	rxdv-skew-ps = <0>;
49	rxc-skew-ps = <2000>;
50};
51
52&gpio1 {
53	status = "okay";
54};
55
56&i2c0 {
57	status = "okay";
58
59	eeprom@51 {
60		compatible = "atmel,24c32";
61		reg = <0x51>;
62		pagesize = <32>;
63	};
64
65	rtc@68 {
66		compatible = "dallas,ds1339";
67		reg = <0x68>;
68	};
69};
70
71&mmc0 {
72	status = "okay";
73	u-boot,dm-pre-reloc;
74
75	cd-gpios = <&portb 18 0>;
76	vmmc-supply = <&regulator_3_3v>;
77	vqmmc-supply = <&regulator_3_3v>;
78};
79
80&usb1 {
81	status = "okay";
82};
83
84&qspi {
85	status = "okay";
86
87	flash0: n25q00@0 {
88		#address-cells = <1>;
89		#size-cells = <1>;
90		compatible = "n25q00";
91		reg = <0>;      /* chip select */
92		spi-max-frequency = <50000000>;
93		m25p,fast-read;
94		page-size = <256>;
95		block-size = <16>; /* 2^16, 64KB */
96		read-delay = <4>;  /* delay value in read data capture register */
97		tshsl-ns = <50>;
98		tsd2d-ns = <50>;
99		tchsh-ns = <4>;
100		tslch-ns = <4>;
101	};
102};
103