xref: /openbmc/u-boot/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi (revision 6d4a3ff2649faa2cf2739e332557f256cc34831e)
1*c402e817SSimon Goldschmidt// SPDX-License-Identifier: GPL-2.0+
2*c402e817SSimon Goldschmidt/*
3*c402e817SSimon Goldschmidt * U-Boot additions
4*c402e817SSimon Goldschmidt *
5*c402e817SSimon Goldschmidt * Copyright Altera Corporation (C) 2015
6*c402e817SSimon Goldschmidt * Copyright (c) 2018 Simon Goldschmidt
7*c402e817SSimon Goldschmidt */
8*c402e817SSimon Goldschmidt
9*c402e817SSimon Goldschmidt/{
10*c402e817SSimon Goldschmidt	aliases {
11*c402e817SSimon Goldschmidt		udc0 = &usb1;
12*c402e817SSimon Goldschmidt	};
13*c402e817SSimon Goldschmidt
14*c402e817SSimon Goldschmidt	soc {
15*c402e817SSimon Goldschmidt		u-boot,dm-pre-reloc;
16*c402e817SSimon Goldschmidt	};
17*c402e817SSimon Goldschmidt};
18*c402e817SSimon Goldschmidt
19*c402e817SSimon Goldschmidt&watchdog0 {
20*c402e817SSimon Goldschmidt	status = "disabled";
21*c402e817SSimon Goldschmidt};
22*c402e817SSimon Goldschmidt
23*c402e817SSimon Goldschmidt&mmc {
24*c402e817SSimon Goldschmidt	u-boot,dm-pre-reloc;
25*c402e817SSimon Goldschmidt};
26*c402e817SSimon Goldschmidt
27*c402e817SSimon Goldschmidt&uart0 {
28*c402e817SSimon Goldschmidt	clock-frequency = <100000000>;
29*c402e817SSimon Goldschmidt	u-boot,dm-pre-reloc;
30*c402e817SSimon Goldschmidt};
31*c402e817SSimon Goldschmidt
32*c402e817SSimon Goldschmidt&uart1 {
33*c402e817SSimon Goldschmidt	clock-frequency = <100000000>;
34*c402e817SSimon Goldschmidt};
35*c402e817SSimon Goldschmidt
36*c402e817SSimon Goldschmidt&porta {
37*c402e817SSimon Goldschmidt	bank-name = "porta";
38*c402e817SSimon Goldschmidt};
39*c402e817SSimon Goldschmidt
40*c402e817SSimon Goldschmidt&portb {
41*c402e817SSimon Goldschmidt	bank-name = "portb";
42*c402e817SSimon Goldschmidt};
43*c402e817SSimon Goldschmidt
44*c402e817SSimon Goldschmidt&portc {
45*c402e817SSimon Goldschmidt	bank-name = "portc";
46*c402e817SSimon Goldschmidt};
47