1/*
2 *  Copyright (C) 2013 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include "socfpga_arria5.dtsi"
8
9/ {
10	model = "Altera SOCFPGA Arria V SoC Development Kit";
11	compatible = "altr,socfpga-arria5", "altr,socfpga";
12
13	chosen {
14		bootargs = "console=ttyS0,115200";
15	};
16
17	memory {
18		name = "memory";
19		device_type = "memory";
20		reg = <0x0 0x40000000>; /* 1GB */
21	};
22
23	aliases {
24		/* this allow the ethaddr uboot environmnet variable contents
25		 * to be added to the gmac1 device tree blob.
26		 */
27		ethernet0 = &gmac1;
28	};
29
30	regulator_3_3v: 3-3-v-regulator {
31		compatible = "regulator-fixed";
32		regulator-name = "3.3V";
33		regulator-min-microvolt = <3300000>;
34		regulator-max-microvolt = <3300000>;
35	};
36
37	soc {
38		u-boot,dm-pre-reloc;
39	};
40};
41
42&gmac1 {
43	status = "okay";
44	phy-mode = "rgmii";
45
46	rxd0-skew-ps = <0>;
47	rxd1-skew-ps = <0>;
48	rxd2-skew-ps = <0>;
49	rxd3-skew-ps = <0>;
50	txen-skew-ps = <0>;
51	txc-skew-ps = <2600>;
52	rxdv-skew-ps = <0>;
53	rxc-skew-ps = <2000>;
54};
55
56&i2c0 {
57	status = "okay";
58
59	eeprom@51 {
60		compatible = "atmel,24c32";
61		reg = <0x51>;
62		pagesize = <32>;
63	};
64
65	rtc@68 {
66		compatible = "dallas,ds1339";
67		reg = <0x68>;
68	};
69};
70
71&mmc0 {
72	vmmc-supply = <&regulator_3_3v>;
73	vqmmc-supply = <&regulator_3_3v>;
74	bus-width = <4>;
75	u-boot,dm-pre-reloc;
76};
77
78&usb1 {
79	status = "okay";
80};
81
82&qspi {
83	status = "okay";
84
85	flash0: n25q00@0 {
86		#address-cells = <1>;
87		#size-cells = <1>;
88		compatible = "n25q00";
89		reg = <0>;      /* chip select */
90		spi-max-frequency = <50000000>;
91		m25p,fast-read;
92		page-size = <256>;
93		block-size = <16>; /* 2^16, 64KB */
94		read-delay = <4>;  /* delay value in read data capture register */
95		tshsl-ns = <50>;
96		tsd2d-ns = <50>;
97		tchsh-ns = <4>;
98		tslch-ns = <4>;
99	};
100};
101