1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright (C) 2016-2017 Intel Corporation
4 *
5 *<auto-generated>
6 *	This code was generated by a tool based on
7 *	handoffs from both Qsys and Quartus.
8 *
9 *	Changes to this file may be lost if
10 *	the code is regenerated.
11 *</auto-generated>
12 */
13
14#include "socfpga_arria10.dtsi"
15
16/ {
17	model = "Altera SOCFPGA Arria 10";
18	compatible = "altr,socfpga-arria10", "altr,socfpga";
19
20	chosen {
21		/* Bootloader setting: uboot.rbf_filename */
22		cff-file = "ghrd_10as066n2.periph.rbf";
23		early-release-fpga-config;
24	};
25
26	soc {
27		u-boot,dm-pre-reloc;
28		clkmgr@ffd04000 {
29			u-boot,dm-pre-reloc;
30			clocks {
31				u-boot,dm-pre-reloc;
32				osc1 {
33					u-boot,dm-pre-reloc;
34					clock-frequency = <25000000>;
35					clock-output-names = "altera_arria10_hps_eosc1-clk";
36				};
37
38				cb_intosc_ls_clk {
39					u-boot,dm-pre-reloc;
40					clock-frequency = <60000000>;
41					clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
42				};
43
44				f2s_free_clk {
45					u-boot,dm-pre-reloc;
46					clock-frequency = <200000000>;
47					clock-output-names = "altera_arria10_hps_f2h_free-clk";
48				};
49
50				main_pll {
51					u-boot,dm-pre-reloc;
52				/*
53				 * Address Block: soc_clock_manager_OCP_SLV.
54				 * i_clk_mgr_mainpllgrp
55				 */
56					altr,of_reg_value = <
57						0	/* Field: vco0.psrc */
58						1	/* Field: vco1.denom */
59						191	/* Field: vco1.numer */
60						0	/* Field: mpuclk */
61						0	/* Field: mpuclk.cnt */
62						0	/* Field: mpuclk.src */
63						0	/* Field: nocclk */
64						0	/* Field: nocclk.cnt */
65						0	/* Field: nocclk.src */
66						900	/* Field: cntr2clk.cnt */
67						900	/* Field: cntr3clk.cnt */
68						900	/* Field: cntr4clk.cnt */
69						900	/* Field: cntr5clk.cnt */
70						900	/* Field: cntr6clk.cnt */
71						900	/* Field: cntr7clk.cnt */
72						0	/* Field: cntr7clk.src */
73						900	/* Field: cntr8clk.cnt */
74						900	/* Field: cntr9clk.cnt */
75						0	/* Field: cntr9clk.src */
76						900	/* Field: cntr15clk.cnt */
77						0	/* Field: nocdiv.l4mainclk */
78						0	/* Field: nocdiv.l4mpclk */
79						2	/* Field: nocdiv.l4spclk */
80						0	/* Field: nocdiv.csatclk */
81						1	/* Field: nocdiv.cstraceclk */
82						1	/* Field: nocdiv.cspdbgclk */
83					>;
84				};
85
86				periph_pll {
87					u-boot,dm-pre-reloc;
88				/*
89				 * Address Block: soc_clock_manager_OCP_SLV.
90				 * i_clk_mgr_perpllgrp
91				 */
92					altr,of_reg_value = <
93						0	/* Field: vco0.psrc */
94						1	/* Field: vco1.denom */
95						159	/* Field: vco1.numer */
96						7	/* Field: cntr2clk.cnt */
97						1	/* Field: cntr2clk.src */
98						900	/* Field: cntr3clk.cnt */
99						1	/* Field: cntr3clk.src */
100						19	/* Field: cntr4clk.cnt */
101						1	/* Field: cntr4clk.src */
102						499	/* Field: cntr5clk.cnt */
103						1	/* Field: cntr5clk.src */
104						9	/* Field: cntr6clk.cnt */
105						1	/* Field: cntr6clk.src */
106						900	/* Field: cntr7clk.cnt */
107						900	/* Field: cntr8clk.cnt */
108						0	/* Field: cntr8clk.src */
109						900	/* Field: cntr9clk.cnt */
110						0	/* Field: emacctl.emac0sel */
111						0	/* Field: emacctl.emac1sel */
112						0	/* Field: emacctl.emac2sel */
113						32000	/* Field: gpiodiv.gpiodbclk */
114					>;
115				};
116
117				altera {
118					u-boot,dm-pre-reloc;
119				/*
120				 * Address Block: soc_clock_manager_OCP_SLV.
121				 * i_clk_mgr_alteragrp
122				 */
123					altr,of_reg_value = <
124						0x0384000b	/* Register: nocclk */
125						0x03840001	/* Register: mpuclk */
126					>;
127				};
128			};
129		};
130
131		/*
132		 * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
133		 * Binding: pinmux
134		 */
135		i_io48_pin_mux: pinmux@0xffd07000 {
136			u-boot,dm-pre-reloc;
137			#address-cells = <1>;
138			#size-cells = <1>;
139			compatible = "pinctrl-single";
140			reg = <0xffd07000 0x00000800>;
141			reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
142
143			/*
144			 *	Address Block: soc_3v_io48_pin_mux_OCP_SLV.
145			 *					i_io48_pin_mux_shared_3v_io_grp
146			 */
147			shared {
148				u-boot,dm-pre-reloc;
149				reg = <0xffd07000 0x00000200>;
150				pinctrl-single,register-width = <32>;
151				pinctrl-single,function-mask = <0x0000000f>;
152				pinctrl-single,pins =
153					/* Reg: pinmux_shared_io_q1_1 */
154					<0x00000000 0x00000008>,
155					/* Reg: pinmux_shared_io_q1_2 */
156					<0x00000004 0x00000008>,
157					/* Reg: pinmux_shared_io_q1_3 */
158					<0x00000008 0x00000008>,
159					/* Reg: pinmux_shared_io_q1_4 */
160					<0x0000000c 0x00000008>,
161					/* Reg: pinmux_shared_io_q1_5 */
162					<0x00000010 0x00000008>,
163					/* Reg: pinmux_shared_io_q1_6 */
164					<0x00000014 0x00000008>,
165					/* Reg: pinmux_shared_io_q1_7 */
166					<0x00000018 0x00000008>,
167					/* Reg: pinmux_shared_io_q1_8 */
168					<0x0000001c 0x00000008>,
169					/* Reg: pinmux_shared_io_q1_9 */
170					<0x00000020 0x00000008>,
171					/* Reg: pinmux_shared_io_q1_10 */
172					<0x00000024 0x00000008>,
173					/* Reg: pinmux_shared_io_q1_11 */
174					<0x00000028 0x00000008>,
175					/* Reg: pinmux_shared_io_q1_12 */
176					<0x0000002c 0x00000008>,
177					/* Reg: pinmux_shared_io_q2_1 */
178					<0x00000030 0x00000004>,
179					/* Reg: pinmux_shared_io_q2_2 */
180					<0x00000034 0x00000004>,
181					/* Reg: pinmux_shared_io_q2_3 */
182					<0x00000038 0x00000004>,
183					/* Reg: pinmux_shared_io_q2_4 */
184					<0x0000003c 0x00000004>,
185					/* Reg: pinmux_shared_io_q2_5 */
186					<0x00000040 0x00000004>,
187					/* Reg: pinmux_shared_io_q2_6 */
188					<0x00000044 0x00000004>,
189					/* Reg: pinmux_shared_io_q2_7 */
190					<0x00000048 0x00000004>,
191					/* Reg: pinmux_shared_io_q2_8 */
192					<0x0000004c 0x00000004>,
193					/* Reg: pinmux_shared_io_q2_9 */
194					<0x00000050 0x00000004>,
195					/* Reg: pinmux_shared_io_q2_10 */
196					<0x00000054 0x00000004>,
197					/* Reg: pinmux_shared_io_q2_11 */
198					<0x00000058 0x00000004>,
199					/* Reg: pinmux_shared_io_q2_12 */
200					<0x0000005c 0x00000004>,
201					/* Reg: pinmux_shared_io_q3_1 */
202					<0x00000060 0x00000003>,
203					/* Reg: pinmux_shared_io_q3_2 */
204					<0x00000064 0x00000003>,
205					/* Reg: pinmux_shared_io_q3_3 */
206					<0x00000068 0x00000003>,
207					/* Reg: pinmux_shared_io_q3_4 */
208					<0x0000006c 0x00000003>,
209					/* Reg: pinmux_shared_io_q3_5 */
210					<0x00000070 0x00000003>,
211					/* Reg: pinmux_shared_io_q3_6 */
212					<0x00000074 0x0000000f>,
213					/* Reg: pinmux_shared_io_q3_7 */
214					<0x00000078 0x0000000a>,
215					/* Reg: pinmux_shared_io_q3_8 */
216					<0x0000007c 0x0000000a>,
217					/* Reg: pinmux_shared_io_q3_9 */
218					<0x00000080 0x0000000a>,
219					/* Reg: pinmux_shared_io_q3_10 */
220					<0x00000084 0x0000000a>,
221					/* Reg: pinmux_shared_io_q3_11 */
222					<0x00000088 0x00000001>,
223					/* Reg: pinmux_shared_io_q3_12 */
224					<0x0000008c 0x00000001>,
225					/* Reg: pinmux_shared_io_q4_1 */
226					<0x00000090 0x00000000>,
227					/* Reg: pinmux_shared_io_q4_2 */
228					<0x00000094 0x00000000>,
229					/* Reg: pinmux_shared_io_q4_3 */
230					<0x00000098 0x0000000f>,
231					/* Reg: pinmux_shared_io_q4_4 */
232					<0x0000009c 0x0000000c>,
233					/* Reg: pinmux_shared_io_q4_5 */
234					<0x000000a0 0x0000000f>,
235					/* Reg: pinmux_shared_io_q4_6 */
236					<0x000000a4 0x0000000f>,
237					/* Reg: pinmux_shared_io_q4_7 */
238					<0x000000a8 0x0000000a>,
239					/* Reg: pinmux_shared_io_q4_8 */
240					<0x000000ac 0x0000000a>,
241					/* Reg: pinmux_shared_io_q4_9 */
242					<0x000000b0 0x0000000c>,
243					/* Reg: pinmux_shared_io_q4_10 */
244					<0x000000b4 0x0000000c>,
245					/* Reg: pinmux_shared_io_q4_11 */
246					<0x000000b8 0x0000000c>,
247					/* Reg: pinmux_shared_io_q4_12 */
248					<0x000000bc 0x0000000c>;
249			};
250
251			/*
252			 *	Address Block: soc_3v_io48_pin_mux_OCP_SLV.
253			 *	i_io48_pin_mux_dedicated_io_grp
254			 */
255			dedicated {
256				u-boot,dm-pre-reloc;
257				reg = <0xffd07200 0x00000200>;
258				pinctrl-single,register-width = <32>;
259				pinctrl-single,function-mask = <0x0000000f>;
260				pinctrl-single,pins =
261					/* Reg: pinmux_dedicated_io_4 */
262					<0x0000000c 0x00000008>,
263					/* Reg: pinmux_dedicated_io_5 */
264					<0x00000010 0x00000008>,
265					/* Reg: pinmux_dedicated_io_6 */
266					<0x00000014 0x00000008>,
267					/* Regi: pinmux_dedicated_io_7 */
268					<0x00000018 0x00000008>,
269					/* Reg: pinmux_dedicated_io_8 */
270					<0x0000001c 0x00000008>,
271					/* Reg: pinmux_dedicated_io_9 */
272					<0x00000020 0x00000008>,
273					/* Reg: pinmux_dedicated_io_10 */
274					<0x00000024 0x0000000a>,
275					/* Reg: pinmux_dedicated_io_11 */
276					<0x00000028 0x0000000a>,
277					/* Reg: pinmux_dedicated_io_12 */
278					<0x0000002c 0x00000008>,
279					/* Reg: pinmux_dedicated_io_13 */
280					<0x00000030 0x00000008>,
281					/* Reg: pinmux_dedicated_io_14 */
282					<0x00000034 0x00000008>,
283					/* Reg: pinmux_dedicated_io_15 */
284					<0x00000038 0x00000008>,
285					/* Reg: pinmux_dedicated_io_16 */
286					<0x0000003c 0x0000000d>,
287					/* Reg: pinmux_dedicated_io_17 */
288					<0x00000040 0x0000000d>;
289			};
290
291			/*
292			 * Address Block: soc_3v_io48_pin_mux_OCP_SLV.
293			 * i_io48_pin_mux_dedicated_io_grp
294			 */
295			dedicated_cfg {
296				u-boot,dm-pre-reloc;
297				reg = <0xffd07200 0x00000200>;
298				pinctrl-single,register-width = <32>;
299				pinctrl-single,function-mask = <0x003f3f3f>;
300				pinctrl-single,pins =
301					/* Reg: cfg_dedicated_io_bank */
302					<0x00000100 0x00000101>,
303					/* Reg: cfg_dedicated_io_1 */
304					<0x00000104 0x000b080a>,
305					/* Reg: cfg_dedicated_io_2 */
306					<0x00000108 0x000b080a>,
307					/* Reg: cfg_dedicated_io_3 */
308					<0x0000010c 0x000b080a>,
309					/* Reg: cfg_dedicated_io_4 */
310					<0x00000110 0x000a282a>,
311					/* Reg: cfg_dedicated_io_5 */
312					<0x00000114 0x000a282a>,
313					/* Reg: cfg_dedicated_io_6 */
314					<0x00000118 0x0008282a>,
315					/* Reg: cfg_dedicated_io_7 */
316					<0x0000011c 0x000a282a>,
317					/* Reg: cfg_dedicated_io_8 */
318					<0x00000120 0x000a282a>,
319					/* Reg: cfg_dedicated_io_9 */
320					<0x00000124 0x000a282a>,
321					/* Reg: cfg_dedicated_io_10 */
322					<0x00000128 0x00090000>,
323					/* Reg: cfg_dedicated_io_11 */
324					<0x0000012c 0x00090000>,
325					/* Reg: cfg_dedicated_io_12 */
326					<0x00000130 0x000b282a>,
327					/* Reg: cfg_dedicated_io_13 */
328					<0x00000134 0x000b282a>,
329					/* Reg: cfg_dedicated_io_14 */
330					<0x00000138 0x000b282a>,
331					/* Reg: cfg_dedicated_io_15 */
332					<0x0000013c 0x000b282a>,
333					/* Reg: cfg_dedicated_io_16 */
334					<0x00000140 0x0008282a>,
335					/* Reg: cfg_dedicated_io_17 */
336					<0x00000144 0x000a282a>;
337			};
338
339			/*
340			 *	Address Block: soc_3v_io48_pin_mux_OCP_SLV.
341			 *	i_io48_pin_mux_fpga_interface_grp
342			 */
343			fpga {
344				u-boot,dm-pre-reloc;
345				reg = <0xffd07400 0x00000100>;
346				pinctrl-single,register-width = <32>;
347				pinctrl-single,function-mask = <0x00000001>;
348				pinctrl-single,pins =
349					/* Reg: pinmux_emac0_usefpga */
350					<0x00000000 0x00000000>,
351					/* Reg: pinmux_emac1_usefpga */
352					<0x00000004 0x00000000>,
353					/* Reg: pinmux_emac2_usefpga */
354					<0x00000008 0x00000000>,
355					/* Reg: pinmux_i2c0_usefpga */
356					<0x0000000c 0x00000000>,
357					/* Reg: pinmux_i2c1_usefpga */
358					<0x00000010 0x00000000>,
359					/* Reg: pinmux_i2c_emac0_usefpga */
360					<0x00000014 0x00000000>,
361					/* Reg: pinmux_i2c_emac1_usefpga */
362					<0x00000018 0x00000000>,
363					/* Reg: pinmux_i2c_emac2_usefpga */
364					<0x0000001c 0x00000000>,
365					/* Reg: pinmux_nand_usefpga */
366					<0x00000020 0x00000000>,
367					/* Reg: pinmux_qspi_usefpga */
368					<0x00000024 0x00000000>,
369					/* Reg: pinmux_sdmmc_usefpga */
370					<0x00000028 0x00000000>,
371					/* Reg: pinmux_spim0_usefpga */
372					<0x0000002c 0x00000000>,
373					/* Reg: pinmux_spim1_usefpga */
374					<0x00000030 0x00000000>,
375					/* Reg: pinmux_spis0_usefpga */
376					<0x00000034 0x00000000>,
377					/* Reg: pinmux_spis1_usefpga */
378					<0x00000038 0x00000000>,
379					/* Reg: pinmux_uart0_usefpga */
380					<0x0000003c 0x00000000>,
381					/* Reg: pinmux_uart1_usefpga */
382					<0x00000040 0x00000000>;
383			};
384		};
385
386		i_noc: noc@0xffd10000 {
387			u-boot,dm-pre-reloc;
388			compatible = "altr,socfpga-a10-noc";
389			reg = <0xffd10000 0x00008000>;
390			reg-names = "mpu_m0";
391
392			firewall {
393				u-boot,dm-pre-reloc;
394				/*
395				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
396				 *					I_NOC.mpu_m0.
397				 *					noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
398				 *					mpuregion0addr.base
399				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
400				 *					I_NOC.mpu_m0.
401				 *					noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
402				 *					mpuregion0addr.limit
403				 */
404				altr,mpu0 = <0x00000000 0x0000ffff>;
405				/*
406				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
407				 *					I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
408				 *					hpsregion0addr.base
409				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
410				 *					I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
411				 *					hpsregion0addr.limit
412				 */
413				altr,l3-0 = <0x00000000 0x0000ffff>;
414				/*
415				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
416				 * 					I_NOC.mpu_m0.
417				 *					noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
418				 *					fpga2sdram0region0addr.base
419				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
420				 *					I_NOC.mpu_m0.
421				 *					noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
422				 *					fpga2sdram0region0addr.limit
423				 */
424				altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>;
425				/*
426				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
427				 *					I_NOC.mpu_m0.
428				 *					noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
429				 *					fpga2sdram1region0addr.base
430				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
431				 *					I_NOC.mpu_m0.
432				 *					noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
433				 *					fpga2sdram1region0addr.limit
434				 */
435				altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>;
436				/*
437				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
438				 *					I_NOC.mpu_m0.
439				 *					noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
440				 *					fpga2sdram2region0addr.base
441				 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
442				 *					I_NOC.mpu_m0.
443				 *					noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
444				 *					fpga2sdram2region0addr.limit
445				 */
446				altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>;
447			};
448		};
449
450		hps_fpgabridge0: fpgabridge@0 {
451			compatible = "altr,socfpga-hps2fpga-bridge";
452			altr,init-val = <1>;
453		};
454
455		hps_fpgabridge1: fpgabridge@1 {
456			compatible = "altr,socfpga-lwhps2fpga-bridge";
457			altr,init-val = <1>;
458		};
459
460		hps_fpgabridge2: fpgabridge@2 {
461			compatible = "altr,socfpga-fpga2hps-bridge";
462			altr,init-val = <1>;
463		};
464
465		hps_fpgabridge3: fpgabridge@3 {
466			compatible = "altr,socfpga-fpga2sdram0-bridge";
467			altr,init-val = <1>;
468		};
469
470		hps_fpgabridge4: fpgabridge@4 {
471			compatible = "altr,socfpga-fpga2sdram1-bridge";
472			altr,init-val = <0>;
473		};
474
475		hps_fpgabridge5: fpgabridge@5 {
476			compatible = "altr,socfpga-fpga2sdram2-bridge";
477			altr,init-val = <1>;
478		};
479	};
480};
481