1/*
2 * Copyright (C) 2015 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 */
17#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
18
19/ {
20	model = "Altera SOCFPGA Arria 10";
21	compatible = "altr,socfpga-arria10", "altr,socfpga";
22
23	aliases {
24		ethernet0 = &gmac0;
25		serial0 = &uart1;
26		i2c0 = &i2c1;
27	};
28
29	chosen {
30		bootargs = "earlyprintk";
31		stdout-path = "serial0:115200n8";
32	};
33
34	memory@0 {
35		name = "memory";
36		device_type = "memory";
37		reg = <0x0 0x40000000>; /* 1GB */
38		u-boot,dm-pre-reloc;
39	};
40
41	a10leds {
42		compatible = "gpio-leds";
43
44		a10sr_led0 {
45			label = "a10sr-led0";
46			gpios = <&a10sr_gpio 0 1>;
47		};
48
49		a10sr_led1 {
50			label = "a10sr-led1";
51			gpios = <&a10sr_gpio 1 1>;
52		};
53
54		a10sr_led2 {
55			label = "a10sr-led2";
56			gpios = <&a10sr_gpio 2 1>;
57		};
58
59		a10sr_led3 {
60			label = "a10sr-led3";
61			gpios = <&a10sr_gpio 3 1>;
62		};
63	};
64
65	soc {
66		u-boot,dm-pre-reloc;
67	};
68};
69
70&gmac0 {
71	phy-mode = "rgmii";
72	phy-addr = <0xffffffff>; /* probe for phy addr */
73
74	/*
75	 * These skews assume the user's FPGA design is adding 600ps of delay
76	 * for TX_CLK on Arria 10.
77	 *
78	 * All skews are offset since hardware skew values for the ksz9031
79	 * range from a negative skew to a positive skew.
80	 * See the micrel-ksz90x1.txt Documentation file for details.
81	 */
82	txd0-skew-ps = <0>; /* -420ps */
83	txd1-skew-ps = <0>; /* -420ps */
84	txd2-skew-ps = <0>; /* -420ps */
85	txd3-skew-ps = <0>; /* -420ps */
86	rxd0-skew-ps = <420>; /* 0ps */
87	rxd1-skew-ps = <420>; /* 0ps */
88	rxd2-skew-ps = <420>; /* 0ps */
89	rxd3-skew-ps = <420>; /* 0ps */
90	txen-skew-ps = <0>; /* -420ps */
91	txc-skew-ps = <1860>; /* 960ps */
92	rxdv-skew-ps = <420>; /* 0ps */
93	rxc-skew-ps = <1680>; /* 780ps */
94	max-frame-size = <3800>;
95	status = "okay";
96};
97
98&gpio1 {
99	status = "okay";
100};
101
102&spi1 {
103	status = "okay";
104
105	resource-manager@0 {
106		compatible = "altr,a10sr";
107		reg = <0>;
108		spi-max-frequency = <100000>;
109		/* low-level active IRQ at GPIO1_5 */
110		interrupt-parent = <&portb>;
111		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
112		interrupt-controller;
113		#interrupt-cells = <2>;
114
115		a10sr_gpio: gpio-controller {
116			compatible = "altr,a10sr-gpio";
117			gpio-controller;
118			#gpio-cells = <2>;
119		};
120
121		a10sr_rst: reset-controller {
122			compatible = "altr,a10sr-reset";
123			#reset-cells = <1>;
124		};
125	};
126};
127
128&i2c1 {
129	status = "okay";
130
131	/*
132	 * adjust the falling times to decrease the i2c frequency to 50Khz
133	 * because the LCD module does not work at the standard 100Khz
134	 */
135	clock-frequency = <100000>;
136	i2c-sda-falling-time-ns = <6000>;
137	i2c-scl-falling-time-ns = <6000>;
138
139	eeprom@51 {
140		compatible = "atmel,24c32";
141		reg = <0x51>;
142		pagesize = <32>;
143	};
144
145	rtc@68 {
146		compatible = "dallas,ds1339";
147		reg = <0x68>;
148	};
149
150	ltc@5c {
151		compatible = "ltc2977";
152		reg = <0x5c>;
153	};
154};
155
156&uart1 {
157	clock-frequency = <50000000>;
158	u-boot,dm-pre-reloc;
159	status = "okay";
160};
161
162&usb0 {
163	status = "okay";
164	disable-over-current;
165};
166
167&watchdog1 {
168	status = "okay";
169};
170
171/* Clock available early */
172&main_noc_base_clk {
173	u-boot,dm-pre-reloc;
174};
175
176&main_periph_ref_clk {
177	u-boot,dm-pre-reloc;
178};
179
180&peri_noc_base_clk {
181	u-boot,dm-pre-reloc;
182};
183
184&noc_free_clk {
185	u-boot,dm-pre-reloc;
186};
187
188&l4_mp_clk {
189	u-boot,dm-pre-reloc;
190};
191
192&l4_sp_clk {
193	u-boot,dm-pre-reloc;
194};
195