1/* 2 * Copyright Altera Corporation (C) 2014. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/reset/altr,rst-mgr-a10.h> 19 20/ { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 enable-method = "altr,socfpga-a10-smp"; 28 29 cpu@0 { 30 compatible = "arm,cortex-a9"; 31 device_type = "cpu"; 32 reg = <0>; 33 next-level-cache = <&L2>; 34 }; 35 cpu@1 { 36 compatible = "arm,cortex-a9"; 37 device_type = "cpu"; 38 reg = <1>; 39 next-level-cache = <&L2>; 40 }; 41 }; 42 43 intc: intc@ffffd000 { 44 compatible = "arm,cortex-a9-gic"; 45 #interrupt-cells = <3>; 46 interrupt-controller; 47 reg = <0xffffd000 0x1000>, 48 <0xffffc100 0x100>; 49 }; 50 51 soc { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 compatible = "simple-bus"; 55 device_type = "soc"; 56 interrupt-parent = <&intc>; 57 ranges; 58 u-boot,dm-pre-reloc; 59 60 amba { 61 compatible = "simple-bus"; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges; 65 66 pdma: pdma@ffda1000 { 67 compatible = "arm,pl330", "arm,primecell"; 68 reg = <0xffda1000 0x1000>; 69 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, 70 <0 84 IRQ_TYPE_LEVEL_HIGH>, 71 <0 85 IRQ_TYPE_LEVEL_HIGH>, 72 <0 86 IRQ_TYPE_LEVEL_HIGH>, 73 <0 87 IRQ_TYPE_LEVEL_HIGH>, 74 <0 88 IRQ_TYPE_LEVEL_HIGH>, 75 <0 89 IRQ_TYPE_LEVEL_HIGH>, 76 <0 90 IRQ_TYPE_LEVEL_HIGH>, 77 <0 91 IRQ_TYPE_LEVEL_HIGH>; 78 #dma-cells = <1>; 79 #dma-channels = <8>; 80 #dma-requests = <32>; 81 clocks = <&l4_main_clk>; 82 clock-names = "apb_pclk"; 83 }; 84 }; 85 86 base_fpga_region { 87 #address-cells = <0x1>; 88 #size-cells = <0x1>; 89 90 compatible = "fpga-region"; 91 fpga-mgr = <&fpga_mgr>; 92 }; 93 94 clkmgr@ffd04000 { 95 compatible = "altr,clk-mgr"; 96 reg = <0xffd04000 0x1000>; 97 98 clocks { 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { 103 #clock-cells = <0>; 104 compatible = "fixed-clock"; 105 }; 106 107 cb_intosc_ls_clk: cb_intosc_ls_clk { 108 #clock-cells = <0>; 109 compatible = "fixed-clock"; 110 }; 111 112 f2s_free_clk: f2s_free_clk { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 }; 116 117 osc1: osc1 { 118 #clock-cells = <0>; 119 compatible = "fixed-clock"; 120 }; 121 122 main_pll: main_pll@40 { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 #clock-cells = <0>; 126 compatible = "altr,socfpga-a10-pll-clock"; 127 clocks = <&osc1>, <&cb_intosc_ls_clk>, 128 <&f2s_free_clk>; 129 reg = <0x40>; 130 131 main_mpu_base_clk: main_mpu_base_clk { 132 #clock-cells = <0>; 133 compatible = "altr,socfpga-a10-perip-clk"; 134 clocks = <&main_pll>; 135 div-reg = <0x140 0 11>; 136 }; 137 138 main_noc_base_clk: main_noc_base_clk { 139 #clock-cells = <0>; 140 compatible = "altr,socfpga-a10-perip-clk"; 141 clocks = <&main_pll>; 142 div-reg = <0x144 0 11>; 143 }; 144 145 main_emaca_clk: main_emaca_clk@68 { 146 #clock-cells = <0>; 147 compatible = "altr,socfpga-a10-perip-clk"; 148 clocks = <&main_pll>; 149 reg = <0x68>; 150 }; 151 152 main_emacb_clk: main_emacb_clk@6c { 153 #clock-cells = <0>; 154 compatible = "altr,socfpga-a10-perip-clk"; 155 clocks = <&main_pll>; 156 reg = <0x6C>; 157 }; 158 159 main_emac_ptp_clk: main_emac_ptp_clk@70 { 160 #clock-cells = <0>; 161 compatible = "altr,socfpga-a10-perip-clk"; 162 clocks = <&main_pll>; 163 reg = <0x70>; 164 }; 165 166 main_gpio_db_clk: main_gpio_db_clk@74 { 167 #clock-cells = <0>; 168 compatible = "altr,socfpga-a10-perip-clk"; 169 clocks = <&main_pll>; 170 reg = <0x74>; 171 }; 172 173 main_sdmmc_clk: main_sdmmc_clk@78 { 174 #clock-cells = <0>; 175 compatible = "altr,socfpga-a10-perip-clk" 176; 177 clocks = <&main_pll>; 178 reg = <0x78>; 179 }; 180 181 main_s2f_usr0_clk: main_s2f_usr0_clk@7c { 182 #clock-cells = <0>; 183 compatible = "altr,socfpga-a10-perip-clk"; 184 clocks = <&main_pll>; 185 reg = <0x7C>; 186 }; 187 188 main_s2f_usr1_clk: main_s2f_usr1_clk@80 { 189 #clock-cells = <0>; 190 compatible = "altr,socfpga-a10-perip-clk"; 191 clocks = <&main_pll>; 192 reg = <0x80>; 193 }; 194 195 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { 196 #clock-cells = <0>; 197 compatible = "altr,socfpga-a10-perip-clk"; 198 clocks = <&main_pll>; 199 reg = <0x84>; 200 }; 201 202 main_periph_ref_clk: main_periph_ref_clk@9c { 203 #clock-cells = <0>; 204 compatible = "altr,socfpga-a10-perip-clk"; 205 clocks = <&main_pll>; 206 reg = <0x9C>; 207 }; 208 }; 209 210 periph_pll: periph_pll@c0 { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 #clock-cells = <0>; 214 compatible = "altr,socfpga-a10-pll-clock"; 215 clocks = <&osc1>, <&cb_intosc_ls_clk>, 216 <&f2s_free_clk>, <&main_periph_ref_clk>; 217 reg = <0xC0>; 218 219 peri_mpu_base_clk: peri_mpu_base_clk { 220 #clock-cells = <0>; 221 compatible = "altr,socfpga-a10-perip-clk"; 222 clocks = <&periph_pll>; 223 div-reg = <0x140 16 11>; 224 }; 225 226 peri_noc_base_clk: peri_noc_base_clk { 227 #clock-cells = <0>; 228 compatible = "altr,socfpga-a10-perip-clk"; 229 clocks = <&periph_pll>; 230 div-reg = <0x144 16 11>; 231 }; 232 233 peri_emaca_clk: peri_emaca_clk@e8 { 234 #clock-cells = <0>; 235 compatible = "altr,socfpga-a10-perip-clk"; 236 clocks = <&periph_pll>; 237 reg = <0xE8>; 238 }; 239 240 peri_emacb_clk: peri_emacb_clk@ec { 241 #clock-cells = <0>; 242 compatible = "altr,socfpga-a10-perip-clk"; 243 clocks = <&periph_pll>; 244 reg = <0xEC>; 245 }; 246 247 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { 248 #clock-cells = <0>; 249 compatible = "altr,socfpga-a10-perip-clk"; 250 clocks = <&periph_pll>; 251 reg = <0xF0>; 252 }; 253 254 peri_gpio_db_clk: peri_gpio_db_clk@f4 { 255 #clock-cells = <0>; 256 compatible = "altr,socfpga-a10-perip-clk"; 257 clocks = <&periph_pll>; 258 reg = <0xF4>; 259 }; 260 261 peri_sdmmc_clk: peri_sdmmc_clk@f8 { 262 #clock-cells = <0>; 263 compatible = "altr,socfpga-a10-perip-clk"; 264 clocks = <&periph_pll>; 265 reg = <0xF8>; 266 }; 267 268 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { 269 #clock-cells = <0>; 270 compatible = "altr,socfpga-a10-perip-clk"; 271 clocks = <&periph_pll>; 272 reg = <0xFC>; 273 }; 274 275 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { 276 #clock-cells = <0>; 277 compatible = "altr,socfpga-a10-perip-clk"; 278 clocks = <&periph_pll>; 279 reg = <0x100>; 280 }; 281 282 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { 283 #clock-cells = <0>; 284 compatible = "altr,socfpga-a10-perip-clk"; 285 clocks = <&periph_pll>; 286 reg = <0x104>; 287 }; 288 }; 289 290 mpu_free_clk: mpu_free_clk@60 { 291 #clock-cells = <0>; 292 compatible = "altr,socfpga-a10-perip-clk"; 293 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, 294 <&osc1>, <&cb_intosc_hs_div2_clk>, 295 <&f2s_free_clk>; 296 reg = <0x60>; 297 }; 298 299 noc_free_clk: noc_free_clk@64 { 300 #clock-cells = <0>; 301 compatible = "altr,socfpga-a10-perip-clk"; 302 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, 303 <&osc1>, <&cb_intosc_hs_div2_clk>, 304 <&f2s_free_clk>; 305 reg = <0x64>; 306 }; 307 308 s2f_user1_free_clk: s2f_user1_free_clk@104 { 309 #clock-cells = <0>; 310 compatible = "altr,socfpga-a10-perip-clk"; 311 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, 312 <&osc1>, <&cb_intosc_hs_div2_clk>, 313 <&f2s_free_clk>; 314 reg = <0x104>; 315 }; 316 317 sdmmc_free_clk: sdmmc_free_clk@f8 { 318 #clock-cells = <0>; 319 compatible = "altr,socfpga-a10-perip-clk"; 320 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, 321 <&osc1>, <&cb_intosc_hs_div2_clk>, 322 <&f2s_free_clk>; 323 fixed-divider = <4>; 324 reg = <0xF8>; 325 }; 326 327 l4_sys_free_clk: l4_sys_free_clk { 328 #clock-cells = <0>; 329 compatible = "altr,socfpga-a10-perip-clk"; 330 clocks = <&noc_free_clk>; 331 fixed-divider = <4>; 332 }; 333 334 l4_main_clk: l4_main_clk { 335 #clock-cells = <0>; 336 compatible = "altr,socfpga-a10-gate-clk"; 337 clocks = <&noc_free_clk>; 338 div-reg = <0xA8 0 2>; 339 clk-gate = <0x48 1>; 340 }; 341 342 l4_mp_clk: l4_mp_clk { 343 #clock-cells = <0>; 344 compatible = "altr,socfpga-a10-gate-clk"; 345 clocks = <&noc_free_clk>; 346 div-reg = <0xA8 8 2>; 347 clk-gate = <0x48 2>; 348 }; 349 350 l4_sp_clk: l4_sp_clk { 351 #clock-cells = <0>; 352 compatible = "altr,socfpga-a10-gate-clk"; 353 clocks = <&noc_free_clk>; 354 div-reg = <0xA8 16 2>; 355 clk-gate = <0x48 3>; 356 }; 357 358 mpu_periph_clk: mpu_periph_clk { 359 #clock-cells = <0>; 360 compatible = "altr,socfpga-a10-gate-clk"; 361 clocks = <&mpu_free_clk>; 362 fixed-divider = <4>; 363 clk-gate = <0x48 0>; 364 }; 365 366 sdmmc_clk: sdmmc_clk { 367 #clock-cells = <0>; 368 compatible = "altr,socfpga-a10-gate-clk"; 369 clocks = <&sdmmc_free_clk>; 370 clk-gate = <0xC8 5>; 371 clk-phase = <0 135>; 372 }; 373 374 qspi_clk: qspi_clk { 375 #clock-cells = <0>; 376 compatible = "altr,socfpga-a10-gate-clk"; 377 clocks = <&l4_main_clk>; 378 clk-gate = <0xC8 11>; 379 }; 380 381 nand_clk: nand_clk { 382 #clock-cells = <0>; 383 compatible = "altr,socfpga-a10-gate-clk"; 384 clocks = <&l4_mp_clk>; 385 clk-gate = <0xC8 10>; 386 }; 387 388 spi_m_clk: spi_m_clk { 389 #clock-cells = <0>; 390 compatible = "altr,socfpga-a10-gate-clk"; 391 clocks = <&l4_main_clk>; 392 clk-gate = <0xC8 9>; 393 }; 394 395 usb_clk: usb_clk { 396 #clock-cells = <0>; 397 compatible = "altr,socfpga-a10-gate-clk"; 398 clocks = <&l4_mp_clk>; 399 clk-gate = <0xC8 8>; 400 }; 401 402 s2f_usr1_clk: s2f_usr1_clk { 403 #clock-cells = <0>; 404 compatible = "altr,socfpga-a10-gate-clk"; 405 clocks = <&peri_s2f_usr1_clk>; 406 clk-gate = <0xC8 6>; 407 }; 408 }; 409 }; 410 411 socfpga_axi_setup: stmmac-axi-config { 412 snps,wr_osr_lmt = <0xf>; 413 snps,rd_osr_lmt = <0xf>; 414 snps,blen = <0 0 0 0 16 0 0>; 415 }; 416 417 gmac0: ethernet@ff800000 { 418 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 419 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 420 reg = <0xff800000 0x2000>; 421 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 422 interrupt-names = "macirq"; 423 /* Filled in by bootloader */ 424 mac-address = [00 00 00 00 00 00]; 425 snps,multicast-filter-bins = <256>; 426 snps,perfect-filter-entries = <128>; 427 tx-fifo-depth = <4096>; 428 rx-fifo-depth = <16384>; 429 clocks = <&l4_mp_clk>; 430 clock-names = "stmmaceth"; 431 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 432 reset-names = "stmmaceth", "stmmaceth-ocp"; 433 snps,axi-config = <&socfpga_axi_setup>; 434 status = "disabled"; 435 }; 436 437 gmac1: ethernet@ff802000 { 438 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 439 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 440 reg = <0xff802000 0x2000>; 441 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 442 interrupt-names = "macirq"; 443 /* Filled in by bootloader */ 444 mac-address = [00 00 00 00 00 00]; 445 snps,multicast-filter-bins = <256>; 446 snps,perfect-filter-entries = <128>; 447 tx-fifo-depth = <4096>; 448 rx-fifo-depth = <16384>; 449 clocks = <&l4_mp_clk>; 450 clock-names = "stmmaceth"; 451 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 452 reset-names = "stmmaceth", "stmmaceth-ocp"; 453 snps,axi-config = <&socfpga_axi_setup>; 454 status = "disabled"; 455 }; 456 457 gmac2: ethernet@ff804000 { 458 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 459 altr,sysmgr-syscon = <&sysmgr 0x4C 0>; 460 reg = <0xff804000 0x2000>; 461 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "macirq"; 463 /* Filled in by bootloader */ 464 mac-address = [00 00 00 00 00 00]; 465 snps,multicast-filter-bins = <256>; 466 snps,perfect-filter-entries = <128>; 467 tx-fifo-depth = <4096>; 468 rx-fifo-depth = <16384>; 469 clocks = <&l4_mp_clk>; 470 clock-names = "stmmaceth"; 471 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 472 reset-names = "stmmaceth", "stmmaceth-ocp"; 473 snps,axi-config = <&socfpga_axi_setup>; 474 status = "disabled"; 475 }; 476 477 gpio0: gpio@ffc02900 { 478 #address-cells = <1>; 479 #size-cells = <0>; 480 compatible = "snps,dw-apb-gpio"; 481 reg = <0xffc02900 0x100>; 482 status = "disabled"; 483 484 porta: gpio-controller@0 { 485 compatible = "snps,dw-apb-gpio-port"; 486 bank-name = "porta"; 487 gpio-controller; 488 #gpio-cells = <2>; 489 snps,nr-gpios = <29>; 490 reg = <0>; 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; 494 }; 495 }; 496 497 gpio1: gpio@ffc02a00 { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 compatible = "snps,dw-apb-gpio"; 501 reg = <0xffc02a00 0x100>; 502 status = "disabled"; 503 504 portb: gpio-controller@0 { 505 compatible = "snps,dw-apb-gpio-port"; 506 bank-name = "portb"; 507 gpio-controller; 508 #gpio-cells = <2>; 509 snps,nr-gpios = <29>; 510 reg = <0>; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; 514 }; 515 }; 516 517 gpio2: gpio@ffc02b00 { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 compatible = "snps,dw-apb-gpio"; 521 reg = <0xffc02b00 0x100>; 522 status = "disabled"; 523 524 portc: gpio-controller@0 { 525 compatible = "snps,dw-apb-gpio-port"; 526 bank-name = "portc"; 527 gpio-controller; 528 #gpio-cells = <2>; 529 snps,nr-gpios = <27>; 530 reg = <0>; 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; 534 }; 535 }; 536 537 fpga_mgr: fpga-mgr@ffd03000 { 538 compatible = "altr,socfpga-a10-fpga-mgr"; 539 reg = <0xffd03000 0x100 540 0xffcfe400 0x20>; 541 clocks = <&l4_mp_clk>; 542 resets = <&rst FPGAMGR_RESET>; 543 reset-names = "fpgamgr"; 544 }; 545 546 i2c0: i2c@ffc02200 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 compatible = "snps,designware-i2c"; 550 reg = <0xffc02200 0x100>; 551 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&l4_sp_clk>; 553 resets = <&rst I2C0_RESET>; 554 reset-names = "i2c"; 555 status = "disabled"; 556 }; 557 558 i2c1: i2c@ffc02300 { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 compatible = "snps,designware-i2c"; 562 reg = <0xffc02300 0x100>; 563 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&l4_sp_clk>; 565 resets = <&rst I2C1_RESET>; 566 reset-names = "i2c"; 567 status = "disabled"; 568 }; 569 570 i2c2: i2c@ffc02400 { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 compatible = "snps,designware-i2c"; 574 reg = <0xffc02400 0x100>; 575 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&l4_sp_clk>; 577 resets = <&rst I2C2_RESET>; 578 reset-names = "i2c"; 579 status = "disabled"; 580 }; 581 582 i2c3: i2c@ffc02500 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 compatible = "snps,designware-i2c"; 586 reg = <0xffc02500 0x100>; 587 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&l4_sp_clk>; 589 resets = <&rst I2C3_RESET>; 590 reset-names = "i2c"; 591 status = "disabled"; 592 }; 593 594 i2c4: i2c@ffc02600 { 595 #address-cells = <1>; 596 #size-cells = <0>; 597 compatible = "snps,designware-i2c"; 598 reg = <0xffc02600 0x100>; 599 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&l4_sp_clk>; 601 resets = <&rst I2C4_RESET>; 602 reset-names = "i2c"; 603 status = "disabled"; 604 }; 605 606 spi1: spi@ffda5000 { 607 compatible = "snps,dw-apb-ssi"; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 reg = <0xffda5000 0x100>; 611 interrupts = <0 102 4>; 612 num-chipselect = <4>; 613 bus-num = <0>; 614 /*32bit_access;*/ 615 tx-dma-channel = <&pdma 16>; 616 rx-dma-channel = <&pdma 17>; 617 clocks = <&spi_m_clk>; 618 status = "disabled"; 619 }; 620 621 sdr: sdr@ffc25000 { 622 compatible = "altr,sdr-ctl", "syscon"; 623 reg = <0xffcfb100 0x80>; 624 }; 625 626 L2: l2-cache@fffff000 { 627 compatible = "arm,pl310-cache"; 628 reg = <0xfffff000 0x1000>; 629 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 630 cache-unified; 631 cache-level = <2>; 632 prefetch-data = <1>; 633 prefetch-instr = <1>; 634 arm,shared-override; 635 }; 636 637 mmc: dwmmc0@ff808000 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 compatible = "altr,socfpga-dw-mshc"; 641 reg = <0xff808000 0x1000>; 642 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 643 fifo-depth = <0x400>; 644 clocks = <&l4_mp_clk>, <&sdmmc_clk>; 645 clock-names = "biu", "ciu"; 646 status = "disabled"; 647 }; 648 649 nand: nand@ffb90000 { 650 #address-cells = <1>; 651 #size-cells = <1>; 652 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand"; 653 reg = <0xffb90000 0x20>, 654 <0xffb80000 0x1000>; 655 reg-names = "nand_data", "denali_reg"; 656 interrupts = <0 99 4>; 657 dma-mask = <0xffffffff>; 658 clocks = <&nand_clk>; 659 status = "disabled"; 660 }; 661 662 ocram: sram@ffe00000 { 663 compatible = "mmio-sram"; 664 reg = <0xffe00000 0x40000>; 665 }; 666 667 eccmgr: eccmgr { 668 compatible = "altr,socfpga-a10-ecc-manager"; 669 altr,sysmgr-syscon = <&sysmgr>; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, 673 <0 0 IRQ_TYPE_LEVEL_HIGH>; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 ranges; 677 678 sdramedac { 679 compatible = "altr,sdram-edac-a10"; 680 altr,sdr-syscon = <&sdr>; 681 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, 682 <49 IRQ_TYPE_LEVEL_HIGH>; 683 }; 684 685 l2-ecc@ffd06010 { 686 compatible = "altr,socfpga-a10-l2-ecc"; 687 reg = <0xffd06010 0x4>; 688 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, 689 <32 IRQ_TYPE_LEVEL_HIGH>; 690 }; 691 692 ocram-ecc@ff8c3000 { 693 compatible = "altr,socfpga-a10-ocram-ecc"; 694 reg = <0xff8c3000 0x400>; 695 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, 696 <33 IRQ_TYPE_LEVEL_HIGH>; 697 }; 698 699 emac0-rx-ecc@ff8c0800 { 700 compatible = "altr,socfpga-eth-mac-ecc"; 701 reg = <0xff8c0800 0x400>; 702 altr,ecc-parent = <&gmac0>; 703 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, 704 <36 IRQ_TYPE_LEVEL_HIGH>; 705 }; 706 707 emac0-tx-ecc@ff8c0c00 { 708 compatible = "altr,socfpga-eth-mac-ecc"; 709 reg = <0xff8c0c00 0x400>; 710 altr,ecc-parent = <&gmac0>; 711 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, 712 <37 IRQ_TYPE_LEVEL_HIGH>; 713 }; 714 715 dma-ecc@ff8c8000 { 716 compatible = "altr,socfpga-dma-ecc"; 717 reg = <0xff8c8000 0x400>; 718 altr,ecc-parent = <&pdma>; 719 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, 720 <42 IRQ_TYPE_LEVEL_HIGH>; 721 }; 722 723 usb0-ecc@ff8c8800 { 724 compatible = "altr,socfpga-usb-ecc"; 725 reg = <0xff8c8800 0x400>; 726 altr,ecc-parent = <&usb0>; 727 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, 728 <34 IRQ_TYPE_LEVEL_HIGH>; 729 }; 730 }; 731 732 qspi: spi@ff809000 { 733 compatible = "cdns,qspi-nor", "cadence,qspi"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 reg = <0xff809000 0x100>, 737 <0xffa00000 0x100000>; 738 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 739 cdns,fifo-depth = <128>; 740 cdns,fifo-width = <4>; 741 cdns,trigger-address = <0x00000000>; 742 clocks = <&qspi_clk>; 743 status = "disabled"; 744 }; 745 746 rst: rstmgr@ffd05000 { 747 #reset-cells = <1>; 748 compatible = "altr,rst-mgr"; 749 reg = <0xffd05000 0x100>; 750 altr,modrst-offset = <0x20>; 751 u-boot,dm-pre-reloc; 752 }; 753 754 scu: snoop-control-unit@ffffc000 { 755 compatible = "arm,cortex-a9-scu"; 756 reg = <0xffffc000 0x100>; 757 }; 758 759 sysmgr: sysmgr@ffd06000 { 760 compatible = "altr,sys-mgr", "syscon"; 761 reg = <0xffd06000 0x300>; 762 cpu1-start-addr = <0xffd06230>; 763 }; 764 765 /* Local timer */ 766 timer@ffffc600 { 767 compatible = "arm,cortex-a9-twd-timer"; 768 reg = <0xffffc600 0x100>; 769 interrupts = <1 13 0xf04>; 770 clocks = <&mpu_periph_clk>; 771 }; 772 773 timer0: timer0@ffc02700 { 774 compatible = "snps,dw-apb-timer"; 775 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; 776 reg = <0xffc02700 0x100>; 777 clocks = <&l4_sp_clk>; 778 clock-names = "timer"; 779 }; 780 781 timer1: timer1@ffc02800 { 782 compatible = "snps,dw-apb-timer"; 783 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; 784 reg = <0xffc02800 0x100>; 785 clocks = <&l4_sp_clk>; 786 clock-names = "timer"; 787 }; 788 789 timer2: timer2@ffd00000 { 790 compatible = "snps,dw-apb-timer"; 791 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; 792 reg = <0xffd00000 0x100>; 793 clocks = <&l4_sys_free_clk>; 794 clock-names = "timer"; 795 }; 796 797 timer3: timer3@ffd00100 { 798 compatible = "snps,dw-apb-timer"; 799 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; 800 reg = <0xffd01000 0x100>; 801 clocks = <&l4_sys_free_clk>; 802 clock-names = "timer"; 803 }; 804 805 uart0: serial0@ffc02000 { 806 compatible = "snps,dw-apb-uart"; 807 reg = <0xffc02000 0x100>; 808 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 809 reg-shift = <2>; 810 reg-io-width = <4>; 811 clocks = <&l4_sp_clk>; 812 resets = <&rst UART0_RESET>; 813 status = "disabled"; 814 }; 815 816 uart1: serial1@ffc02100 { 817 compatible = "snps,dw-apb-uart"; 818 reg = <0xffc02100 0x100>; 819 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 820 reg-shift = <2>; 821 reg-io-width = <4>; 822 clocks = <&l4_sp_clk>; 823 resets = <&rst UART1_RESET>; 824 status = "disabled"; 825 }; 826 827 usbphy0: usbphy { 828 #phy-cells = <0>; 829 compatible = "usb-nop-xceiv"; 830 status = "okay"; 831 }; 832 833 usb0: usb@ffb00000 { 834 compatible = "snps,dwc2"; 835 reg = <0xffb00000 0xffff>; 836 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&usb_clk>; 838 clock-names = "otg"; 839 resets = <&rst USB0_RESET>; 840 reset-names = "dwc2"; 841 phys = <&usbphy0>; 842 phy-names = "usb2-phy"; 843 status = "disabled"; 844 }; 845 846 usb1: usb@ffb40000 { 847 compatible = "snps,dwc2"; 848 reg = <0xffb40000 0xffff>; 849 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&usb_clk>; 851 clock-names = "otg"; 852 resets = <&rst USB1_RESET>; 853 reset-names = "dwc2"; 854 phys = <&usbphy0>; 855 phy-names = "usb2-phy"; 856 status = "disabled"; 857 }; 858 859 watchdog0: watchdog@ffd00200 { 860 compatible = "snps,dw-wdt"; 861 reg = <0xffd00200 0x100>; 862 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&l4_sys_free_clk>; 864 status = "disabled"; 865 }; 866 867 watchdog1: watchdog@ffd00300 { 868 compatible = "snps,dw-wdt"; 869 reg = <0xffd00300 0x100>; 870 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&l4_sys_free_clk>; 872 status = "disabled"; 873 }; 874 }; 875}; 876