1/* 2 * Copyright Altera Corporation (C) 2014. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/reset/altr,rst-mgr-a10.h> 19 20/ { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 enable-method = "altr,socfpga-a10-smp"; 28 29 cpu@0 { 30 compatible = "arm,cortex-a9"; 31 device_type = "cpu"; 32 reg = <0>; 33 next-level-cache = <&L2>; 34 }; 35 cpu@1 { 36 compatible = "arm,cortex-a9"; 37 device_type = "cpu"; 38 reg = <1>; 39 next-level-cache = <&L2>; 40 }; 41 }; 42 43 intc: intc@ffffd000 { 44 compatible = "arm,cortex-a9-gic"; 45 #interrupt-cells = <3>; 46 interrupt-controller; 47 reg = <0xffffd000 0x1000>, 48 <0xffffc100 0x100>; 49 }; 50 51 soc { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 compatible = "simple-bus"; 55 device_type = "soc"; 56 interrupt-parent = <&intc>; 57 ranges; 58 u-boot,dm-pre-reloc; 59 60 amba { 61 compatible = "simple-bus"; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges; 65 66 pdma: pdma@ffda1000 { 67 compatible = "arm,pl330", "arm,primecell"; 68 reg = <0xffda1000 0x1000>; 69 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, 70 <0 84 IRQ_TYPE_LEVEL_HIGH>, 71 <0 85 IRQ_TYPE_LEVEL_HIGH>, 72 <0 86 IRQ_TYPE_LEVEL_HIGH>, 73 <0 87 IRQ_TYPE_LEVEL_HIGH>, 74 <0 88 IRQ_TYPE_LEVEL_HIGH>, 75 <0 89 IRQ_TYPE_LEVEL_HIGH>, 76 <0 90 IRQ_TYPE_LEVEL_HIGH>, 77 <0 91 IRQ_TYPE_LEVEL_HIGH>; 78 #dma-cells = <1>; 79 #dma-channels = <8>; 80 #dma-requests = <32>; 81 clocks = <&l4_main_clk>; 82 clock-names = "apb_pclk"; 83 }; 84 }; 85 86 base_fpga_region { 87 #address-cells = <0x1>; 88 #size-cells = <0x1>; 89 90 compatible = "fpga-region"; 91 fpga-mgr = <&fpga_mgr>; 92 }; 93 94 clkmgr@ffd04000 { 95 compatible = "altr,clk-mgr"; 96 reg = <0xffd04000 0x1000>; 97 u-boot,dm-pre-reloc; 98 99 clocks { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 u-boot,dm-pre-reloc; 103 104 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { 105 #clock-cells = <0>; 106 compatible = "fixed-clock"; 107 u-boot,dm-pre-reloc; 108 }; 109 110 cb_intosc_ls_clk: cb_intosc_ls_clk { 111 #clock-cells = <0>; 112 compatible = "fixed-clock"; 113 u-boot,dm-pre-reloc; 114 }; 115 116 f2s_free_clk: f2s_free_clk { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 u-boot,dm-pre-reloc; 120 }; 121 122 osc1: osc1 { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 u-boot,dm-pre-reloc; 126 }; 127 128 main_pll: main_pll@40 { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 #clock-cells = <0>; 132 compatible = "altr,socfpga-a10-pll-clock"; 133 clocks = <&osc1>, <&cb_intosc_ls_clk>, 134 <&f2s_free_clk>; 135 reg = <0x40>; 136 u-boot,dm-pre-reloc; 137 138 main_mpu_base_clk: main_mpu_base_clk { 139 #clock-cells = <0>; 140 compatible = "altr,socfpga-a10-perip-clk"; 141 clocks = <&main_pll>; 142 div-reg = <0x140 0 11>; 143 }; 144 145 main_noc_base_clk: main_noc_base_clk { 146 #clock-cells = <0>; 147 compatible = "altr,socfpga-a10-perip-clk"; 148 clocks = <&main_pll>; 149 div-reg = <0x144 0 11>; 150 }; 151 152 main_emaca_clk: main_emaca_clk@68 { 153 #clock-cells = <0>; 154 compatible = "altr,socfpga-a10-perip-clk"; 155 clocks = <&main_pll>; 156 reg = <0x68>; 157 }; 158 159 main_emacb_clk: main_emacb_clk@6c { 160 #clock-cells = <0>; 161 compatible = "altr,socfpga-a10-perip-clk"; 162 clocks = <&main_pll>; 163 reg = <0x6C>; 164 }; 165 166 main_emac_ptp_clk: main_emac_ptp_clk@70 { 167 #clock-cells = <0>; 168 compatible = "altr,socfpga-a10-perip-clk"; 169 clocks = <&main_pll>; 170 reg = <0x70>; 171 }; 172 173 main_gpio_db_clk: main_gpio_db_clk@74 { 174 #clock-cells = <0>; 175 compatible = "altr,socfpga-a10-perip-clk"; 176 clocks = <&main_pll>; 177 reg = <0x74>; 178 }; 179 180 main_sdmmc_clk: main_sdmmc_clk@78 { 181 #clock-cells = <0>; 182 compatible = "altr,socfpga-a10-perip-clk" 183; 184 clocks = <&main_pll>; 185 reg = <0x78>; 186 }; 187 188 main_s2f_usr0_clk: main_s2f_usr0_clk@7c { 189 #clock-cells = <0>; 190 compatible = "altr,socfpga-a10-perip-clk"; 191 clocks = <&main_pll>; 192 reg = <0x7C>; 193 }; 194 195 main_s2f_usr1_clk: main_s2f_usr1_clk@80 { 196 #clock-cells = <0>; 197 compatible = "altr,socfpga-a10-perip-clk"; 198 clocks = <&main_pll>; 199 reg = <0x80>; 200 }; 201 202 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { 203 #clock-cells = <0>; 204 compatible = "altr,socfpga-a10-perip-clk"; 205 clocks = <&main_pll>; 206 reg = <0x84>; 207 }; 208 209 main_periph_ref_clk: main_periph_ref_clk@9c { 210 #clock-cells = <0>; 211 compatible = "altr,socfpga-a10-perip-clk"; 212 clocks = <&main_pll>; 213 reg = <0x9C>; 214 }; 215 }; 216 217 periph_pll: periph_pll@c0 { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 #clock-cells = <0>; 221 compatible = "altr,socfpga-a10-pll-clock"; 222 clocks = <&osc1>, <&cb_intosc_ls_clk>, 223 <&f2s_free_clk>, <&main_periph_ref_clk>; 224 reg = <0xC0>; 225 u-boot,dm-pre-reloc; 226 227 peri_mpu_base_clk: peri_mpu_base_clk { 228 #clock-cells = <0>; 229 compatible = "altr,socfpga-a10-perip-clk"; 230 clocks = <&periph_pll>; 231 div-reg = <0x140 16 11>; 232 }; 233 234 peri_noc_base_clk: peri_noc_base_clk { 235 #clock-cells = <0>; 236 compatible = "altr,socfpga-a10-perip-clk"; 237 clocks = <&periph_pll>; 238 div-reg = <0x144 16 11>; 239 }; 240 241 peri_emaca_clk: peri_emaca_clk@e8 { 242 #clock-cells = <0>; 243 compatible = "altr,socfpga-a10-perip-clk"; 244 clocks = <&periph_pll>; 245 reg = <0xE8>; 246 }; 247 248 peri_emacb_clk: peri_emacb_clk@ec { 249 #clock-cells = <0>; 250 compatible = "altr,socfpga-a10-perip-clk"; 251 clocks = <&periph_pll>; 252 reg = <0xEC>; 253 }; 254 255 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { 256 #clock-cells = <0>; 257 compatible = "altr,socfpga-a10-perip-clk"; 258 clocks = <&periph_pll>; 259 reg = <0xF0>; 260 }; 261 262 peri_gpio_db_clk: peri_gpio_db_clk@f4 { 263 #clock-cells = <0>; 264 compatible = "altr,socfpga-a10-perip-clk"; 265 clocks = <&periph_pll>; 266 reg = <0xF4>; 267 }; 268 269 peri_sdmmc_clk: peri_sdmmc_clk@f8 { 270 #clock-cells = <0>; 271 compatible = "altr,socfpga-a10-perip-clk"; 272 clocks = <&periph_pll>; 273 reg = <0xF8>; 274 }; 275 276 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { 277 #clock-cells = <0>; 278 compatible = "altr,socfpga-a10-perip-clk"; 279 clocks = <&periph_pll>; 280 reg = <0xFC>; 281 }; 282 283 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { 284 #clock-cells = <0>; 285 compatible = "altr,socfpga-a10-perip-clk"; 286 clocks = <&periph_pll>; 287 reg = <0x100>; 288 }; 289 290 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { 291 #clock-cells = <0>; 292 compatible = "altr,socfpga-a10-perip-clk"; 293 clocks = <&periph_pll>; 294 reg = <0x104>; 295 }; 296 }; 297 298 mpu_free_clk: mpu_free_clk@60 { 299 #clock-cells = <0>; 300 compatible = "altr,socfpga-a10-perip-clk"; 301 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, 302 <&osc1>, <&cb_intosc_hs_div2_clk>, 303 <&f2s_free_clk>; 304 reg = <0x60>; 305 }; 306 307 noc_free_clk: noc_free_clk@64 { 308 #clock-cells = <0>; 309 compatible = "altr,socfpga-a10-perip-clk"; 310 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, 311 <&osc1>, <&cb_intosc_hs_div2_clk>, 312 <&f2s_free_clk>; 313 reg = <0x64>; 314 }; 315 316 s2f_user1_free_clk: s2f_user1_free_clk@104 { 317 #clock-cells = <0>; 318 compatible = "altr,socfpga-a10-perip-clk"; 319 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, 320 <&osc1>, <&cb_intosc_hs_div2_clk>, 321 <&f2s_free_clk>; 322 reg = <0x104>; 323 }; 324 325 sdmmc_free_clk: sdmmc_free_clk@f8 { 326 #clock-cells = <0>; 327 compatible = "altr,socfpga-a10-perip-clk"; 328 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, 329 <&osc1>, <&cb_intosc_hs_div2_clk>, 330 <&f2s_free_clk>; 331 fixed-divider = <4>; 332 reg = <0xF8>; 333 }; 334 335 l4_sys_free_clk: l4_sys_free_clk { 336 #clock-cells = <0>; 337 compatible = "altr,socfpga-a10-perip-clk"; 338 clocks = <&noc_free_clk>; 339 fixed-divider = <4>; 340 }; 341 342 l4_main_clk: l4_main_clk { 343 #clock-cells = <0>; 344 compatible = "altr,socfpga-a10-gate-clk"; 345 clocks = <&noc_free_clk>; 346 div-reg = <0xA8 0 2>; 347 clk-gate = <0x48 1>; 348 }; 349 350 l4_mp_clk: l4_mp_clk { 351 #clock-cells = <0>; 352 compatible = "altr,socfpga-a10-gate-clk"; 353 clocks = <&noc_free_clk>; 354 div-reg = <0xA8 8 2>; 355 clk-gate = <0x48 2>; 356 }; 357 358 l4_sp_clk: l4_sp_clk { 359 #clock-cells = <0>; 360 compatible = "altr,socfpga-a10-gate-clk"; 361 clocks = <&noc_free_clk>; 362 div-reg = <0xA8 16 2>; 363 clk-gate = <0x48 3>; 364 }; 365 366 mpu_periph_clk: mpu_periph_clk { 367 #clock-cells = <0>; 368 compatible = "altr,socfpga-a10-gate-clk"; 369 clocks = <&mpu_free_clk>; 370 fixed-divider = <4>; 371 clk-gate = <0x48 0>; 372 }; 373 374 sdmmc_clk: sdmmc_clk { 375 #clock-cells = <0>; 376 compatible = "altr,socfpga-a10-gate-clk"; 377 clocks = <&sdmmc_free_clk>; 378 clk-gate = <0xC8 5>; 379 clk-phase = <0 135>; 380 }; 381 382 qspi_clk: qspi_clk { 383 #clock-cells = <0>; 384 compatible = "altr,socfpga-a10-gate-clk"; 385 clocks = <&l4_main_clk>; 386 clk-gate = <0xC8 11>; 387 }; 388 389 nand_clk: nand_clk { 390 #clock-cells = <0>; 391 compatible = "altr,socfpga-a10-gate-clk"; 392 clocks = <&l4_mp_clk>; 393 clk-gate = <0xC8 10>; 394 }; 395 396 spi_m_clk: spi_m_clk { 397 #clock-cells = <0>; 398 compatible = "altr,socfpga-a10-gate-clk"; 399 clocks = <&l4_main_clk>; 400 clk-gate = <0xC8 9>; 401 }; 402 403 usb_clk: usb_clk { 404 #clock-cells = <0>; 405 compatible = "altr,socfpga-a10-gate-clk"; 406 clocks = <&l4_mp_clk>; 407 clk-gate = <0xC8 8>; 408 }; 409 410 s2f_usr1_clk: s2f_usr1_clk { 411 #clock-cells = <0>; 412 compatible = "altr,socfpga-a10-gate-clk"; 413 clocks = <&peri_s2f_usr1_clk>; 414 clk-gate = <0xC8 6>; 415 }; 416 }; 417 }; 418 419 socfpga_axi_setup: stmmac-axi-config { 420 snps,wr_osr_lmt = <0xf>; 421 snps,rd_osr_lmt = <0xf>; 422 snps,blen = <0 0 0 0 16 0 0>; 423 }; 424 425 gmac0: ethernet@ff800000 { 426 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 427 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 428 reg = <0xff800000 0x2000>; 429 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 430 interrupt-names = "macirq"; 431 /* Filled in by bootloader */ 432 mac-address = [00 00 00 00 00 00]; 433 snps,multicast-filter-bins = <256>; 434 snps,perfect-filter-entries = <128>; 435 tx-fifo-depth = <4096>; 436 rx-fifo-depth = <16384>; 437 clocks = <&l4_mp_clk>; 438 clock-names = "stmmaceth"; 439 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 440 reset-names = "stmmaceth", "stmmaceth-ocp"; 441 snps,axi-config = <&socfpga_axi_setup>; 442 status = "disabled"; 443 }; 444 445 gmac1: ethernet@ff802000 { 446 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 447 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 448 reg = <0xff802000 0x2000>; 449 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 450 interrupt-names = "macirq"; 451 /* Filled in by bootloader */ 452 mac-address = [00 00 00 00 00 00]; 453 snps,multicast-filter-bins = <256>; 454 snps,perfect-filter-entries = <128>; 455 tx-fifo-depth = <4096>; 456 rx-fifo-depth = <16384>; 457 clocks = <&l4_mp_clk>; 458 clock-names = "stmmaceth"; 459 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 460 reset-names = "stmmaceth", "stmmaceth-ocp"; 461 snps,axi-config = <&socfpga_axi_setup>; 462 status = "disabled"; 463 }; 464 465 gmac2: ethernet@ff804000 { 466 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; 467 altr,sysmgr-syscon = <&sysmgr 0x4C 0>; 468 reg = <0xff804000 0x2000>; 469 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "macirq"; 471 /* Filled in by bootloader */ 472 mac-address = [00 00 00 00 00 00]; 473 snps,multicast-filter-bins = <256>; 474 snps,perfect-filter-entries = <128>; 475 tx-fifo-depth = <4096>; 476 rx-fifo-depth = <16384>; 477 clocks = <&l4_mp_clk>; 478 clock-names = "stmmaceth"; 479 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 480 reset-names = "stmmaceth", "stmmaceth-ocp"; 481 snps,axi-config = <&socfpga_axi_setup>; 482 status = "disabled"; 483 }; 484 485 gpio0: gpio@ffc02900 { 486 #address-cells = <1>; 487 #size-cells = <0>; 488 compatible = "snps,dw-apb-gpio"; 489 reg = <0xffc02900 0x100>; 490 status = "disabled"; 491 492 porta: gpio-controller@0 { 493 compatible = "snps,dw-apb-gpio-port"; 494 bank-name = "porta"; 495 gpio-controller; 496 #gpio-cells = <2>; 497 snps,nr-gpios = <29>; 498 reg = <0>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; 502 }; 503 }; 504 505 gpio1: gpio@ffc02a00 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 compatible = "snps,dw-apb-gpio"; 509 reg = <0xffc02a00 0x100>; 510 status = "disabled"; 511 512 portb: gpio-controller@0 { 513 compatible = "snps,dw-apb-gpio-port"; 514 bank-name = "portb"; 515 gpio-controller; 516 #gpio-cells = <2>; 517 snps,nr-gpios = <29>; 518 reg = <0>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; 522 }; 523 }; 524 525 gpio2: gpio@ffc02b00 { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 compatible = "snps,dw-apb-gpio"; 529 reg = <0xffc02b00 0x100>; 530 status = "disabled"; 531 532 portc: gpio-controller@0 { 533 compatible = "snps,dw-apb-gpio-port"; 534 bank-name = "portc"; 535 gpio-controller; 536 #gpio-cells = <2>; 537 snps,nr-gpios = <27>; 538 reg = <0>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; 542 }; 543 }; 544 545 fpga_mgr: fpga-mgr@ffd03000 { 546 compatible = "altr,socfpga-a10-fpga-mgr"; 547 reg = <0xffd03000 0x100 548 0xffcfe400 0x20>; 549 clocks = <&l4_mp_clk>; 550 resets = <&rst FPGAMGR_RESET>; 551 reset-names = "fpgamgr"; 552 }; 553 554 i2c0: i2c@ffc02200 { 555 #address-cells = <1>; 556 #size-cells = <0>; 557 compatible = "snps,designware-i2c"; 558 reg = <0xffc02200 0x100>; 559 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&l4_sp_clk>; 561 resets = <&rst I2C0_RESET>; 562 reset-names = "i2c"; 563 status = "disabled"; 564 }; 565 566 i2c1: i2c@ffc02300 { 567 #address-cells = <1>; 568 #size-cells = <0>; 569 compatible = "snps,designware-i2c"; 570 reg = <0xffc02300 0x100>; 571 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&l4_sp_clk>; 573 resets = <&rst I2C1_RESET>; 574 reset-names = "i2c"; 575 status = "disabled"; 576 }; 577 578 i2c2: i2c@ffc02400 { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 compatible = "snps,designware-i2c"; 582 reg = <0xffc02400 0x100>; 583 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&l4_sp_clk>; 585 resets = <&rst I2C2_RESET>; 586 reset-names = "i2c"; 587 status = "disabled"; 588 }; 589 590 i2c3: i2c@ffc02500 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 compatible = "snps,designware-i2c"; 594 reg = <0xffc02500 0x100>; 595 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&l4_sp_clk>; 597 resets = <&rst I2C3_RESET>; 598 reset-names = "i2c"; 599 status = "disabled"; 600 }; 601 602 i2c4: i2c@ffc02600 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 compatible = "snps,designware-i2c"; 606 reg = <0xffc02600 0x100>; 607 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&l4_sp_clk>; 609 resets = <&rst I2C4_RESET>; 610 reset-names = "i2c"; 611 status = "disabled"; 612 }; 613 614 spi1: spi@ffda5000 { 615 compatible = "snps,dw-apb-ssi"; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 reg = <0xffda5000 0x100>; 619 interrupts = <0 102 4>; 620 num-chipselect = <4>; 621 bus-num = <0>; 622 /*32bit_access;*/ 623 tx-dma-channel = <&pdma 16>; 624 rx-dma-channel = <&pdma 17>; 625 clocks = <&spi_m_clk>; 626 status = "disabled"; 627 }; 628 629 sdr: sdr@ffc25000 { 630 compatible = "altr,sdr-ctl", "syscon"; 631 reg = <0xffcfb100 0x80>; 632 }; 633 634 L2: l2-cache@fffff000 { 635 compatible = "arm,pl310-cache"; 636 reg = <0xfffff000 0x1000>; 637 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 638 cache-unified; 639 cache-level = <2>; 640 prefetch-data = <1>; 641 prefetch-instr = <1>; 642 arm,shared-override; 643 }; 644 645 mmc: dwmmc0@ff808000 { 646 #address-cells = <1>; 647 #size-cells = <0>; 648 compatible = "altr,socfpga-dw-mshc"; 649 reg = <0xff808000 0x1000>; 650 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 651 fifo-depth = <0x400>; 652 clocks = <&l4_mp_clk>, <&sdmmc_clk>; 653 clock-names = "biu", "ciu"; 654 status = "disabled"; 655 }; 656 657 nand: nand@ffb90000 { 658 #address-cells = <1>; 659 #size-cells = <1>; 660 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand"; 661 reg = <0xffb90000 0x20>, 662 <0xffb80000 0x1000>; 663 reg-names = "nand_data", "denali_reg"; 664 interrupts = <0 99 4>; 665 dma-mask = <0xffffffff>; 666 clocks = <&nand_clk>; 667 status = "disabled"; 668 }; 669 670 ocram: sram@ffe00000 { 671 compatible = "mmio-sram"; 672 reg = <0xffe00000 0x40000>; 673 }; 674 675 eccmgr: eccmgr { 676 compatible = "altr,socfpga-a10-ecc-manager"; 677 altr,sysmgr-syscon = <&sysmgr>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, 681 <0 0 IRQ_TYPE_LEVEL_HIGH>; 682 interrupt-controller; 683 #interrupt-cells = <2>; 684 ranges; 685 686 sdramedac { 687 compatible = "altr,sdram-edac-a10"; 688 altr,sdr-syscon = <&sdr>; 689 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, 690 <49 IRQ_TYPE_LEVEL_HIGH>; 691 }; 692 693 l2-ecc@ffd06010 { 694 compatible = "altr,socfpga-a10-l2-ecc"; 695 reg = <0xffd06010 0x4>; 696 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, 697 <32 IRQ_TYPE_LEVEL_HIGH>; 698 }; 699 700 ocram-ecc@ff8c3000 { 701 compatible = "altr,socfpga-a10-ocram-ecc"; 702 reg = <0xff8c3000 0x400>; 703 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, 704 <33 IRQ_TYPE_LEVEL_HIGH>; 705 }; 706 707 emac0-rx-ecc@ff8c0800 { 708 compatible = "altr,socfpga-eth-mac-ecc"; 709 reg = <0xff8c0800 0x400>; 710 altr,ecc-parent = <&gmac0>; 711 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, 712 <36 IRQ_TYPE_LEVEL_HIGH>; 713 }; 714 715 emac0-tx-ecc@ff8c0c00 { 716 compatible = "altr,socfpga-eth-mac-ecc"; 717 reg = <0xff8c0c00 0x400>; 718 altr,ecc-parent = <&gmac0>; 719 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, 720 <37 IRQ_TYPE_LEVEL_HIGH>; 721 }; 722 723 dma-ecc@ff8c8000 { 724 compatible = "altr,socfpga-dma-ecc"; 725 reg = <0xff8c8000 0x400>; 726 altr,ecc-parent = <&pdma>; 727 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, 728 <42 IRQ_TYPE_LEVEL_HIGH>; 729 }; 730 731 usb0-ecc@ff8c8800 { 732 compatible = "altr,socfpga-usb-ecc"; 733 reg = <0xff8c8800 0x400>; 734 altr,ecc-parent = <&usb0>; 735 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, 736 <34 IRQ_TYPE_LEVEL_HIGH>; 737 }; 738 }; 739 740 qspi: spi@ff809000 { 741 compatible = "cdns,qspi-nor", "cadence,qspi"; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 reg = <0xff809000 0x100>, 745 <0xffa00000 0x100000>; 746 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 747 cdns,fifo-depth = <128>; 748 cdns,fifo-width = <4>; 749 cdns,trigger-address = <0x00000000>; 750 clocks = <&qspi_clk>; 751 status = "disabled"; 752 }; 753 754 rst: rstmgr@ffd05000 { 755 #reset-cells = <1>; 756 compatible = "altr,rst-mgr"; 757 reg = <0xffd05000 0x100>; 758 altr,modrst-offset = <0x20>; 759 u-boot,dm-pre-reloc; 760 }; 761 762 scu: snoop-control-unit@ffffc000 { 763 compatible = "arm,cortex-a9-scu"; 764 reg = <0xffffc000 0x100>; 765 }; 766 767 sysmgr: sysmgr@ffd06000 { 768 compatible = "altr,sys-mgr", "syscon"; 769 reg = <0xffd06000 0x300>; 770 cpu1-start-addr = <0xffd06230>; 771 }; 772 773 /* Local timer */ 774 timer@ffffc600 { 775 compatible = "arm,cortex-a9-twd-timer"; 776 reg = <0xffffc600 0x100>; 777 interrupts = <1 13 0xf04>; 778 clocks = <&mpu_periph_clk>; 779 }; 780 781 timer0: timer0@ffc02700 { 782 compatible = "snps,dw-apb-timer"; 783 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; 784 reg = <0xffc02700 0x100>; 785 clocks = <&l4_sp_clk>; 786 clock-names = "timer"; 787 }; 788 789 timer1: timer1@ffc02800 { 790 compatible = "snps,dw-apb-timer"; 791 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; 792 reg = <0xffc02800 0x100>; 793 clocks = <&l4_sp_clk>; 794 clock-names = "timer"; 795 }; 796 797 timer2: timer2@ffd00000 { 798 compatible = "snps,dw-apb-timer"; 799 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; 800 reg = <0xffd00000 0x100>; 801 clocks = <&l4_sys_free_clk>; 802 clock-names = "timer"; 803 }; 804 805 timer3: timer3@ffd00100 { 806 compatible = "snps,dw-apb-timer"; 807 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; 808 reg = <0xffd01000 0x100>; 809 clocks = <&l4_sys_free_clk>; 810 clock-names = "timer"; 811 }; 812 813 uart0: serial0@ffc02000 { 814 compatible = "snps,dw-apb-uart"; 815 reg = <0xffc02000 0x100>; 816 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 817 reg-shift = <2>; 818 reg-io-width = <4>; 819 clocks = <&l4_sp_clk>; 820 resets = <&rst UART0_RESET>; 821 status = "disabled"; 822 }; 823 824 uart1: serial1@ffc02100 { 825 compatible = "snps,dw-apb-uart"; 826 reg = <0xffc02100 0x100>; 827 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 828 reg-shift = <2>; 829 reg-io-width = <4>; 830 clocks = <&l4_sp_clk>; 831 resets = <&rst UART1_RESET>; 832 status = "disabled"; 833 }; 834 835 usbphy0: usbphy { 836 #phy-cells = <0>; 837 compatible = "usb-nop-xceiv"; 838 status = "okay"; 839 }; 840 841 usb0: usb@ffb00000 { 842 compatible = "snps,dwc2"; 843 reg = <0xffb00000 0xffff>; 844 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&usb_clk>; 846 clock-names = "otg"; 847 resets = <&rst USB0_RESET>; 848 reset-names = "dwc2"; 849 phys = <&usbphy0>; 850 phy-names = "usb2-phy"; 851 status = "disabled"; 852 }; 853 854 usb1: usb@ffb40000 { 855 compatible = "snps,dwc2"; 856 reg = <0xffb40000 0xffff>; 857 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&usb_clk>; 859 clock-names = "otg"; 860 resets = <&rst USB1_RESET>; 861 reset-names = "dwc2"; 862 phys = <&usbphy0>; 863 phy-names = "usb2-phy"; 864 status = "disabled"; 865 }; 866 867 watchdog0: watchdog@ffd00200 { 868 compatible = "snps,dw-wdt"; 869 reg = <0xffd00200 0x100>; 870 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&l4_sys_free_clk>; 872 status = "disabled"; 873 }; 874 875 watchdog1: watchdog@ffd00300 { 876 compatible = "snps,dw-wdt"; 877 reg = <0xffd00300 0x100>; 878 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&l4_sys_free_clk>; 880 status = "disabled"; 881 }; 882 }; 883}; 884