xref: /openbmc/u-boot/arch/arm/dts/socfpga.dtsi (revision acc2372d)
1/*
2 *  Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 */
6
7#include "skeleton.dtsi"
8#include <dt-bindings/reset/altr,rst-mgr.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	aliases {
15		ethernet0 = &gmac0;
16		ethernet1 = &gmac1;
17		serial0 = &uart0;
18		serial1 = &uart1;
19		timer0 = &timer0;
20		timer1 = &timer1;
21		timer2 = &timer2;
22		timer3 = &timer3;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu@0 {
30			compatible = "arm,cortex-a9";
31			device_type = "cpu";
32			reg = <0>;
33			next-level-cache = <&L2>;
34		};
35		cpu@1 {
36			compatible = "arm,cortex-a9";
37			device_type = "cpu";
38			reg = <1>;
39			next-level-cache = <&L2>;
40		};
41	};
42
43	intc: intc@fffed000 {
44		compatible = "arm,cortex-a9-gic";
45		#interrupt-cells = <3>;
46		interrupt-controller;
47		reg = <0xfffed000 0x1000>,
48		      <0xfffec100 0x100>;
49	};
50
51	soc {
52		#address-cells = <1>;
53		#size-cells = <1>;
54		compatible = "simple-bus";
55		device_type = "soc";
56		interrupt-parent = <&intc>;
57		ranges;
58
59		amba {
60			compatible = "arm,amba-bus";
61			#address-cells = <1>;
62			#size-cells = <1>;
63			ranges;
64
65			pdma: pdma@ffe01000 {
66				compatible = "arm,pl330", "arm,primecell";
67				reg = <0xffe01000 0x1000>;
68				interrupts = <0 104 4>,
69					     <0 105 4>,
70					     <0 106 4>,
71					     <0 107 4>,
72					     <0 108 4>,
73					     <0 109 4>,
74					     <0 110 4>,
75					     <0 111 4>;
76				#dma-cells = <1>;
77				#dma-channels = <8>;
78				#dma-requests = <32>;
79				clocks = <&l4_main_clk>;
80				clock-names = "apb_pclk";
81			};
82		};
83
84		can0: can@ffc00000 {
85			compatible = "bosch,d_can";
86			reg = <0xffc00000 0x1000>;
87			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
88			clocks = <&can0_clk>;
89			status = "disabled";
90		};
91
92		can1: can@ffc01000 {
93			compatible = "bosch,d_can";
94			reg = <0xffc01000 0x1000>;
95			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
96			clocks = <&can1_clk>;
97			status = "disabled";
98		};
99
100		clkmgr@ffd04000 {
101				compatible = "altr,clk-mgr";
102				reg = <0xffd04000 0x1000>;
103
104				clocks {
105					#address-cells = <1>;
106					#size-cells = <0>;
107
108					osc1: osc1 {
109						#clock-cells = <0>;
110						compatible = "fixed-clock";
111					};
112
113					osc2: osc2 {
114						#clock-cells = <0>;
115						compatible = "fixed-clock";
116					};
117
118					f2s_periph_ref_clk: f2s_periph_ref_clk {
119						#clock-cells = <0>;
120						compatible = "fixed-clock";
121					};
122
123					f2s_sdram_ref_clk: f2s_sdram_ref_clk {
124						#clock-cells = <0>;
125						compatible = "fixed-clock";
126					};
127
128					main_pll: main_pll {
129						#address-cells = <1>;
130						#size-cells = <0>;
131						#clock-cells = <0>;
132						compatible = "altr,socfpga-pll-clock";
133						clocks = <&osc1>;
134						reg = <0x40>;
135
136						mpuclk: mpuclk {
137							#clock-cells = <0>;
138							compatible = "altr,socfpga-perip-clk";
139							clocks = <&main_pll>;
140							div-reg = <0xe0 0 9>;
141							reg = <0x48>;
142						};
143
144						mainclk: mainclk {
145							#clock-cells = <0>;
146							compatible = "altr,socfpga-perip-clk";
147							clocks = <&main_pll>;
148							div-reg = <0xe4 0 9>;
149							reg = <0x4C>;
150						};
151
152						dbg_base_clk: dbg_base_clk {
153							#clock-cells = <0>;
154							compatible = "altr,socfpga-perip-clk";
155							clocks = <&main_pll>;
156							div-reg = <0xe8 0 9>;
157							reg = <0x50>;
158						};
159
160						main_qspi_clk: main_qspi_clk {
161							#clock-cells = <0>;
162							compatible = "altr,socfpga-perip-clk";
163							clocks = <&main_pll>;
164							reg = <0x54>;
165						};
166
167						main_nand_sdmmc_clk: main_nand_sdmmc_clk {
168							#clock-cells = <0>;
169							compatible = "altr,socfpga-perip-clk";
170							clocks = <&main_pll>;
171							reg = <0x58>;
172						};
173
174						cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
175							#clock-cells = <0>;
176							compatible = "altr,socfpga-perip-clk";
177							clocks = <&main_pll>;
178							reg = <0x5C>;
179						};
180					};
181
182					periph_pll: periph_pll {
183						#address-cells = <1>;
184						#size-cells = <0>;
185						#clock-cells = <0>;
186						compatible = "altr,socfpga-pll-clock";
187						clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
188						reg = <0x80>;
189
190						emac0_clk: emac0_clk {
191							#clock-cells = <0>;
192							compatible = "altr,socfpga-perip-clk";
193							clocks = <&periph_pll>;
194							reg = <0x88>;
195						};
196
197						emac1_clk: emac1_clk {
198							#clock-cells = <0>;
199							compatible = "altr,socfpga-perip-clk";
200							clocks = <&periph_pll>;
201							reg = <0x8C>;
202						};
203
204						per_qspi_clk: per_qsi_clk {
205							#clock-cells = <0>;
206							compatible = "altr,socfpga-perip-clk";
207							clocks = <&periph_pll>;
208							reg = <0x90>;
209						};
210
211						per_nand_mmc_clk: per_nand_mmc_clk {
212							#clock-cells = <0>;
213							compatible = "altr,socfpga-perip-clk";
214							clocks = <&periph_pll>;
215							reg = <0x94>;
216						};
217
218						per_base_clk: per_base_clk {
219							#clock-cells = <0>;
220							compatible = "altr,socfpga-perip-clk";
221							clocks = <&periph_pll>;
222							reg = <0x98>;
223						};
224
225						h2f_usr1_clk: h2f_usr1_clk {
226							#clock-cells = <0>;
227							compatible = "altr,socfpga-perip-clk";
228							clocks = <&periph_pll>;
229							reg = <0x9C>;
230						};
231					};
232
233					sdram_pll: sdram_pll {
234						#address-cells = <1>;
235						#size-cells = <0>;
236						#clock-cells = <0>;
237						compatible = "altr,socfpga-pll-clock";
238						clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
239						reg = <0xC0>;
240
241						ddr_dqs_clk: ddr_dqs_clk {
242							#clock-cells = <0>;
243							compatible = "altr,socfpga-perip-clk";
244							clocks = <&sdram_pll>;
245							reg = <0xC8>;
246						};
247
248						ddr_2x_dqs_clk: ddr_2x_dqs_clk {
249							#clock-cells = <0>;
250							compatible = "altr,socfpga-perip-clk";
251							clocks = <&sdram_pll>;
252							reg = <0xCC>;
253						};
254
255						ddr_dq_clk: ddr_dq_clk {
256							#clock-cells = <0>;
257							compatible = "altr,socfpga-perip-clk";
258							clocks = <&sdram_pll>;
259							reg = <0xD0>;
260						};
261
262						h2f_usr2_clk: h2f_usr2_clk {
263							#clock-cells = <0>;
264							compatible = "altr,socfpga-perip-clk";
265							clocks = <&sdram_pll>;
266							reg = <0xD4>;
267						};
268					};
269
270					mpu_periph_clk: mpu_periph_clk {
271						#clock-cells = <0>;
272						compatible = "altr,socfpga-perip-clk";
273						clocks = <&mpuclk>;
274						fixed-divider = <4>;
275					};
276
277					mpu_l2_ram_clk: mpu_l2_ram_clk {
278						#clock-cells = <0>;
279						compatible = "altr,socfpga-perip-clk";
280						clocks = <&mpuclk>;
281						fixed-divider = <2>;
282					};
283
284					l4_main_clk: l4_main_clk {
285						#clock-cells = <0>;
286						compatible = "altr,socfpga-gate-clk";
287						clocks = <&mainclk>;
288						clk-gate = <0x60 0>;
289					};
290
291					l3_main_clk: l3_main_clk {
292						#clock-cells = <0>;
293						compatible = "altr,socfpga-perip-clk";
294						clocks = <&mainclk>;
295						fixed-divider = <1>;
296					};
297
298					l3_mp_clk: l3_mp_clk {
299						#clock-cells = <0>;
300						compatible = "altr,socfpga-gate-clk";
301						clocks = <&mainclk>;
302						div-reg = <0x64 0 2>;
303						clk-gate = <0x60 1>;
304					};
305
306					l3_sp_clk: l3_sp_clk {
307						#clock-cells = <0>;
308						compatible = "altr,socfpga-gate-clk";
309						clocks = <&mainclk>;
310						div-reg = <0x64 2 2>;
311					};
312
313					l4_mp_clk: l4_mp_clk {
314						#clock-cells = <0>;
315						compatible = "altr,socfpga-gate-clk";
316						clocks = <&mainclk>, <&per_base_clk>;
317						div-reg = <0x64 4 3>;
318						clk-gate = <0x60 2>;
319					};
320
321					l4_sp_clk: l4_sp_clk {
322						#clock-cells = <0>;
323						compatible = "altr,socfpga-gate-clk";
324						clocks = <&mainclk>, <&per_base_clk>;
325						div-reg = <0x64 7 3>;
326						clk-gate = <0x60 3>;
327					};
328
329					dbg_at_clk: dbg_at_clk {
330						#clock-cells = <0>;
331						compatible = "altr,socfpga-gate-clk";
332						clocks = <&dbg_base_clk>;
333						div-reg = <0x68 0 2>;
334						clk-gate = <0x60 4>;
335					};
336
337					dbg_clk: dbg_clk {
338						#clock-cells = <0>;
339						compatible = "altr,socfpga-gate-clk";
340						clocks = <&dbg_base_clk>;
341						div-reg = <0x68 2 2>;
342						clk-gate = <0x60 5>;
343					};
344
345					dbg_trace_clk: dbg_trace_clk {
346						#clock-cells = <0>;
347						compatible = "altr,socfpga-gate-clk";
348						clocks = <&dbg_base_clk>;
349						div-reg = <0x6C 0 3>;
350						clk-gate = <0x60 6>;
351					};
352
353					dbg_timer_clk: dbg_timer_clk {
354						#clock-cells = <0>;
355						compatible = "altr,socfpga-gate-clk";
356						clocks = <&dbg_base_clk>;
357						clk-gate = <0x60 7>;
358					};
359
360					cfg_clk: cfg_clk {
361						#clock-cells = <0>;
362						compatible = "altr,socfpga-gate-clk";
363						clocks = <&cfg_h2f_usr0_clk>;
364						clk-gate = <0x60 8>;
365					};
366
367					h2f_user0_clk: h2f_user0_clk {
368						#clock-cells = <0>;
369						compatible = "altr,socfpga-gate-clk";
370						clocks = <&cfg_h2f_usr0_clk>;
371						clk-gate = <0x60 9>;
372					};
373
374					emac_0_clk: emac_0_clk {
375						#clock-cells = <0>;
376						compatible = "altr,socfpga-gate-clk";
377						clocks = <&emac0_clk>;
378						clk-gate = <0xa0 0>;
379					};
380
381					emac_1_clk: emac_1_clk {
382						#clock-cells = <0>;
383						compatible = "altr,socfpga-gate-clk";
384						clocks = <&emac1_clk>;
385						clk-gate = <0xa0 1>;
386					};
387
388					usb_mp_clk: usb_mp_clk {
389						#clock-cells = <0>;
390						compatible = "altr,socfpga-gate-clk";
391						clocks = <&per_base_clk>;
392						clk-gate = <0xa0 2>;
393						div-reg = <0xa4 0 3>;
394					};
395
396					spi_m_clk: spi_m_clk {
397						#clock-cells = <0>;
398						compatible = "altr,socfpga-gate-clk";
399						clocks = <&per_base_clk>;
400						clk-gate = <0xa0 3>;
401						div-reg = <0xa4 3 3>;
402					};
403
404					can0_clk: can0_clk {
405						#clock-cells = <0>;
406						compatible = "altr,socfpga-gate-clk";
407						clocks = <&per_base_clk>;
408						clk-gate = <0xa0 4>;
409						div-reg = <0xa4 6 3>;
410					};
411
412					can1_clk: can1_clk {
413						#clock-cells = <0>;
414						compatible = "altr,socfpga-gate-clk";
415						clocks = <&per_base_clk>;
416						clk-gate = <0xa0 5>;
417						div-reg = <0xa4 9 3>;
418					};
419
420					gpio_db_clk: gpio_db_clk {
421						#clock-cells = <0>;
422						compatible = "altr,socfpga-gate-clk";
423						clocks = <&per_base_clk>;
424						clk-gate = <0xa0 6>;
425						div-reg = <0xa8 0 24>;
426					};
427
428					h2f_user1_clk: h2f_user1_clk {
429						#clock-cells = <0>;
430						compatible = "altr,socfpga-gate-clk";
431						clocks = <&h2f_usr1_clk>;
432						clk-gate = <0xa0 7>;
433					};
434
435					sdmmc_clk: sdmmc_clk {
436						#clock-cells = <0>;
437						compatible = "altr,socfpga-gate-clk";
438						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
439						clk-gate = <0xa0 8>;
440						clk-phase = <0 135>;
441					};
442
443					nand_x_clk: nand_x_clk {
444						#clock-cells = <0>;
445						compatible = "altr,socfpga-gate-clk";
446						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
447						clk-gate = <0xa0 9>;
448					};
449
450					nand_clk: nand_clk {
451						#clock-cells = <0>;
452						compatible = "altr,socfpga-gate-clk";
453						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
454						clk-gate = <0xa0 10>;
455						fixed-divider = <4>;
456					};
457
458					qspi_clk: qspi_clk {
459						#clock-cells = <0>;
460						compatible = "altr,socfpga-gate-clk";
461						clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
462						clk-gate = <0xa0 11>;
463					};
464				};
465			};
466
467		gmac0: ethernet@ff700000 {
468			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
469			altr,sysmgr-syscon = <&sysmgr 0x60 0>;
470			reg = <0xff700000 0x2000>;
471			interrupts = <0 115 4>;
472			interrupt-names = "macirq";
473			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
474			clocks = <&emac0_clk>;
475			clock-names = "stmmaceth";
476			resets = <&rst EMAC0_RESET>;
477			reset-names = "stmmaceth";
478			snps,multicast-filter-bins = <256>;
479			snps,perfect-filter-entries = <128>;
480			status = "disabled";
481		};
482
483		gmac1: ethernet@ff702000 {
484			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
485			altr,sysmgr-syscon = <&sysmgr 0x60 2>;
486			reg = <0xff702000 0x2000>;
487			interrupts = <0 120 4>;
488			interrupt-names = "macirq";
489			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
490			clocks = <&emac1_clk>;
491			clock-names = "stmmaceth";
492			resets = <&rst EMAC1_RESET>;
493			reset-names = "stmmaceth";
494			snps,multicast-filter-bins = <256>;
495			snps,perfect-filter-entries = <128>;
496			status = "disabled";
497		};
498
499		i2c0: i2c@ffc04000 {
500			#address-cells = <1>;
501			#size-cells = <0>;
502			compatible = "snps,designware-i2c";
503			reg = <0xffc04000 0x1000>;
504			clocks = <&l4_sp_clk>;
505			interrupts = <0 158 0x4>;
506			status = "disabled";
507		};
508
509		i2c1: i2c@ffc05000 {
510			#address-cells = <1>;
511			#size-cells = <0>;
512			compatible = "snps,designware-i2c";
513			reg = <0xffc05000 0x1000>;
514			clocks = <&l4_sp_clk>;
515			interrupts = <0 159 0x4>;
516			status = "disabled";
517		};
518
519		i2c2: i2c@ffc06000 {
520			#address-cells = <1>;
521			#size-cells = <0>;
522			compatible = "snps,designware-i2c";
523			reg = <0xffc06000 0x1000>;
524			clocks = <&l4_sp_clk>;
525			interrupts = <0 160 0x4>;
526			status = "disabled";
527		};
528
529		i2c3: i2c@ffc07000 {
530			#address-cells = <1>;
531			#size-cells = <0>;
532			compatible = "snps,designware-i2c";
533			reg = <0xffc07000 0x1000>;
534			clocks = <&l4_sp_clk>;
535			interrupts = <0 161 0x4>;
536			status = "disabled";
537		};
538
539		gpio0: gpio@ff708000 {
540			#address-cells = <1>;
541			#size-cells = <0>;
542			compatible = "snps,dw-apb-gpio";
543			reg = <0xff708000 0x1000>;
544			clocks = <&per_base_clk>;
545			status = "disabled";
546
547			porta: gpio-controller@0 {
548				compatible = "snps,dw-apb-gpio-port";
549				gpio-controller;
550				#gpio-cells = <2>;
551				snps,nr-gpios = <29>;
552				reg = <0>;
553				interrupt-controller;
554				#interrupt-cells = <2>;
555				interrupts = <0 164 4>;
556			};
557		};
558
559		gpio1: gpio@ff709000 {
560			#address-cells = <1>;
561			#size-cells = <0>;
562			compatible = "snps,dw-apb-gpio";
563			reg = <0xff709000 0x1000>;
564			clocks = <&per_base_clk>;
565			status = "disabled";
566
567			portb: gpio-controller@0 {
568				compatible = "snps,dw-apb-gpio-port";
569				gpio-controller;
570				#gpio-cells = <2>;
571				snps,nr-gpios = <29>;
572				reg = <0>;
573				interrupt-controller;
574				#interrupt-cells = <2>;
575				interrupts = <0 165 4>;
576			};
577		};
578
579		gpio2: gpio@ff70a000 {
580			#address-cells = <1>;
581			#size-cells = <0>;
582			compatible = "snps,dw-apb-gpio";
583			reg = <0xff70a000 0x1000>;
584			clocks = <&per_base_clk>;
585			status = "disabled";
586
587			portc: gpio-controller@0 {
588				compatible = "snps,dw-apb-gpio-port";
589				gpio-controller;
590				#gpio-cells = <2>;
591				snps,nr-gpios = <27>;
592				reg = <0>;
593				interrupt-controller;
594				#interrupt-cells = <2>;
595				interrupts = <0 166 4>;
596			};
597		};
598
599		sdr: sdr@ffc25000 {
600			compatible = "syscon";
601			reg = <0xffc25000 0x1000>;
602		};
603
604		sdramedac {
605			compatible = "altr,sdram-edac";
606			altr,sdr-syscon = <&sdr>;
607			interrupts = <0 39 4>;
608		};
609
610		L2: l2-cache@fffef000 {
611			compatible = "arm,pl310-cache";
612			reg = <0xfffef000 0x1000>;
613			interrupts = <0 38 0x04>;
614			cache-unified;
615			cache-level = <2>;
616			arm,tag-latency = <1 1 1>;
617			arm,data-latency = <2 1 1>;
618		};
619
620		mmc: dwmmc0@ff704000 {
621			compatible = "altr,socfpga-dw-mshc";
622			reg = <0xff704000 0x1000>;
623			interrupts = <0 139 4>;
624			fifo-depth = <0x400>;
625			#address-cells = <1>;
626			#size-cells = <0>;
627			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
628			clock-names = "biu", "ciu";
629		};
630
631		qspi: spi@ff705000 {
632			compatible = "cadence,qspi";
633			#address-cells = <1>;
634			#size-cells = <0>;
635			reg = <0xff705000 0x1000>,
636				<0xffa00000 0x1000>;
637			interrupts = <0 151 4>;
638			clocks = <&qspi_clk>;
639			ext-decoder = <0>;  /* external decoder */
640			num-chipselect = <4>;
641			fifo-depth = <128>;
642			bus-num = <2>;
643			status = "disabled";
644		};
645
646		spi0: spi@fff00000 {
647			compatible = "snps,dw-spi-mmio";
648			#address-cells = <1>;
649			#size-cells = <0>;
650			reg = <0xfff00000 0x1000>;
651			interrupts = <0 154 4>;
652			num-chipselect = <4>;
653			bus-num = <0>;
654			tx-dma-channel = <&pdma 16>;
655			rx-dma-channel = <&pdma 17>;
656			clocks = <&per_base_clk>;
657			status = "disabled";
658		};
659
660		spi1: spi@fff01000 {
661			compatible = "snps,dw-spi-mmio";
662			#address-cells = <1>;
663			#size-cells = <0>;
664			reg = <0xfff01000 0x1000>;
665			interrupts = <0 156 4>;
666			num-chipselect = <4>;
667			bus-num = <1>;
668			tx-dma-channel = <&pdma 20>;
669			rx-dma-channel = <&pdma 21>;
670			clocks = <&per_base_clk>;
671			status = "disabled";
672		};
673
674		/* Local timer */
675		timer@fffec600 {
676			compatible = "arm,cortex-a9-twd-timer";
677			reg = <0xfffec600 0x100>;
678			interrupts = <1 13 0xf04>;
679			clocks = <&mpu_periph_clk>;
680		};
681
682		timer0: timer0@ffc08000 {
683			compatible = "snps,dw-apb-timer";
684			interrupts = <0 167 4>;
685			reg = <0xffc08000 0x1000>;
686			clocks = <&l4_sp_clk>;
687			clock-names = "timer";
688		};
689
690		timer1: timer1@ffc09000 {
691			compatible = "snps,dw-apb-timer";
692			interrupts = <0 168 4>;
693			reg = <0xffc09000 0x1000>;
694			clocks = <&l4_sp_clk>;
695			clock-names = "timer";
696		};
697
698		timer2: timer2@ffd00000 {
699			compatible = "snps,dw-apb-timer";
700			interrupts = <0 169 4>;
701			reg = <0xffd00000 0x1000>;
702			clocks = <&osc1>;
703			clock-names = "timer";
704		};
705
706		timer3: timer3@ffd01000 {
707			compatible = "snps,dw-apb-timer";
708			interrupts = <0 170 4>;
709			reg = <0xffd01000 0x1000>;
710			clocks = <&osc1>;
711			clock-names = "timer";
712		};
713
714		uart0: serial0@ffc02000 {
715			compatible = "snps,dw-apb-uart";
716			reg = <0xffc02000 0x1000>;
717			interrupts = <0 162 4>;
718			reg-shift = <2>;
719			reg-io-width = <4>;
720			clocks = <&l4_sp_clk>;
721		};
722
723		uart1: serial1@ffc03000 {
724			compatible = "snps,dw-apb-uart";
725			reg = <0xffc03000 0x1000>;
726			interrupts = <0 163 4>;
727			reg-shift = <2>;
728			reg-io-width = <4>;
729			clocks = <&l4_sp_clk>;
730		};
731
732		rst: rstmgr@ffd05000 {
733			#reset-cells = <1>;
734			compatible = "altr,rst-mgr";
735			reg = <0xffd05000 0x1000>;
736		};
737
738		usbphy0: usbphy@0 {
739			#phy-cells = <0>;
740			compatible = "usb-nop-xceiv";
741			status = "okay";
742		};
743
744		usb0: usb@ffb00000 {
745			compatible = "snps,dwc2";
746			reg = <0xffb00000 0xffff>;
747			interrupts = <0 125 4>;
748			clocks = <&usb_mp_clk>;
749			clock-names = "otg";
750			phys = <&usbphy0>;
751			phy-names = "usb2-phy";
752			status = "disabled";
753		};
754
755		usb1: usb@ffb40000 {
756			compatible = "snps,dwc2";
757			reg = <0xffb40000 0xffff>;
758			interrupts = <0 128 4>;
759			clocks = <&usb_mp_clk>;
760			clock-names = "otg";
761			phys = <&usbphy0>;
762			phy-names = "usb2-phy";
763			status = "disabled";
764		};
765
766		watchdog0: watchdog@ffd02000 {
767			compatible = "snps,dw-wdt";
768			reg = <0xffd02000 0x1000>;
769			interrupts = <0 171 4>;
770			clocks = <&osc1>;
771			status = "disabled";
772		};
773
774		watchdog1: watchdog@ffd03000 {
775			compatible = "snps,dw-wdt";
776			reg = <0xffd03000 0x1000>;
777			interrupts = <0 172 4>;
778			clocks = <&osc1>;
779			status = "disabled";
780		};
781
782		sysmgr: sysmgr@ffd08000 {
783			compatible = "altr,sys-mgr", "syscon";
784			reg = <0xffd08000 0x4000>;
785		};
786	};
787};
788