1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#define USB_CLASS_HUB 9 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 serial3 = &uart3; 26 serial4 = &uart4; 27 mmc0 = &sdhci; 28 mmc1 = &sdmmc; 29 }; 30 31 cpus { 32 #address-cells = <2>; 33 #size-cells = <0>; 34 35 cpu-map { 36 cluster0 { 37 core0 { 38 cpu = <&cpu_l0>; 39 }; 40 core1 { 41 cpu = <&cpu_l1>; 42 }; 43 core2 { 44 cpu = <&cpu_l2>; 45 }; 46 core3 { 47 cpu = <&cpu_l3>; 48 }; 49 }; 50 51 cluster1 { 52 core0 { 53 cpu = <&cpu_b0>; 54 }; 55 core1 { 56 cpu = <&cpu_b1>; 57 }; 58 }; 59 }; 60 61 cpu_l0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53", "arm,armv8"; 64 reg = <0x0 0x0>; 65 enable-method = "psci"; 66 #cooling-cells = <2>; /* min followed by max */ 67 clocks = <&cru ARMCLKL>; 68 }; 69 70 cpu_l1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53", "arm,armv8"; 73 reg = <0x0 0x1>; 74 enable-method = "psci"; 75 clocks = <&cru ARMCLKL>; 76 }; 77 78 cpu_l2: cpu@2 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 reg = <0x0 0x2>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLKL>; 84 }; 85 86 cpu_l3: cpu@3 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53", "arm,armv8"; 89 reg = <0x0 0x3>; 90 enable-method = "psci"; 91 clocks = <&cru ARMCLKL>; 92 }; 93 94 cpu_b0: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a72", "arm,armv8"; 97 reg = <0x0 0x100>; 98 enable-method = "psci"; 99 #cooling-cells = <2>; /* min followed by max */ 100 clocks = <&cru ARMCLKB>; 101 }; 102 103 cpu_b1: cpu@101 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a72", "arm,armv8"; 106 reg = <0x0 0x101>; 107 enable-method = "psci"; 108 clocks = <&cru ARMCLKB>; 109 }; 110 }; 111 112 psci { 113 compatible = "arm,psci-1.0"; 114 method = "smc"; 115 }; 116 117 timer { 118 compatible = "arm,armv8-timer"; 119 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 120 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 121 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 122 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 123 }; 124 125 xin24m: xin24m { 126 compatible = "fixed-clock"; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 #clock-cells = <0>; 130 }; 131 132 amba { 133 compatible = "simple-bus"; 134 #address-cells = <2>; 135 #size-cells = <2>; 136 ranges; 137 138 dmac_bus: dma-controller@ff6d0000 { 139 compatible = "arm,pl330", "arm,primecell"; 140 reg = <0x0 0xff6d0000 0x0 0x4000>; 141 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 143 #dma-cells = <1>; 144 clocks = <&cru ACLK_DMAC0_PERILP>; 145 clock-names = "apb_pclk"; 146 }; 147 148 dmac_peri: dma-controller@ff6e0000 { 149 compatible = "arm,pl330", "arm,primecell"; 150 reg = <0x0 0xff6e0000 0x0 0x4000>; 151 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 153 #dma-cells = <1>; 154 clocks = <&cru ACLK_DMAC1_PERILP>; 155 clock-names = "apb_pclk"; 156 }; 157 }; 158 159 sdio0: dwmmc@fe310000 { 160 compatible = "rockchip,rk3399-dw-mshc", 161 "rockchip,rk3288-dw-mshc"; 162 reg = <0x0 0xfe310000 0x0 0x4000>; 163 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 164 clock-freq-min-max = <400000 150000000>; 165 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 166 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 167 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 168 fifo-depth = <0x100>; 169 status = "disabled"; 170 }; 171 172 sdmmc: dwmmc@fe320000 { 173 compatible = "rockchip,rk3399-dw-mshc", 174 "rockchip,rk3288-dw-mshc"; 175 reg = <0x0 0xfe320000 0x0 0x4000>; 176 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 177 clock-freq-min-max = <400000 150000000>; 178 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, 179 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 180 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&sdmmc_clk>; 183 fifo-depth = <0x100>; 184 status = "disabled"; 185 }; 186 187 sdhci: sdhci@fe330000 { 188 u-boot,dm-pre-reloc; 189 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 190 reg = <0x0 0xfe330000 0x0 0x10000>; 191 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 192 assigned-clocks = <&cru SCLK_EMMC>; 193 assigned-clock-rates = <200000000>; 194 max-frequency = <200000000>; 195 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 196 clock-names = "clk_xin", "clk_ahb"; 197 phys = <&emmc_phy>; 198 phy-names = "phy_arasan"; 199 status = "disabled"; 200 }; 201 202 usb_host0_ehci: usb@fe380000 { 203 compatible = "generic-ehci"; 204 reg = <0x0 0xfe380000 0x0 0x20000>; 205 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 207 clock-names = "hclk_host0", "hclk_host0_arb"; 208 status = "disabled"; 209 }; 210 211 usb_host0_ohci: usb@fe3a0000 { 212 compatible = "generic-ohci"; 213 reg = <0x0 0xfe3a0000 0x0 0x20000>; 214 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 216 clock-names = "hclk_host0", "hclk_host0_arb"; 217 status = "disabled"; 218 }; 219 220 usb_host1_ehci: usb@fe3c0000 { 221 compatible = "generic-ehci"; 222 reg = <0x0 0xfe3c0000 0x0 0x20000>; 223 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 225 clock-names = "hclk_host1", "hclk_host1_arb"; 226 status = "disabled"; 227 }; 228 229 usb_host1_ohci: usb@fe3e0000 { 230 compatible = "generic-ohci"; 231 reg = <0x0 0xfe3e0000 0x0 0x20000>; 232 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 234 clock-names = "hclk_host1", "hclk_host1_arb"; 235 status = "disabled"; 236 }; 237 238 dwc3_typec0: usb@fe800000 { 239 compatible = "rockchip,rk3399-xhci"; 240 reg = <0x0 0xfe800000 0x0 0x100000>; 241 status = "disabled"; 242 snps,dis-enblslpm-quirk; 243 snps,phyif-utmi-bits = <16>; 244 snps,dis-u2-freeclk-exists-quirk; 245 snps,dis-u2-susphy-quirk; 246 247 #address-cells = <2>; 248 #size-cells = <2>; 249 hub { 250 compatible = "usb-hub"; 251 usb,device-class = <USB_CLASS_HUB>; 252 }; 253 typec_phy0 { 254 compatible = "rockchip,rk3399-usb3-phy"; 255 reg = <0x0 0xff7c0000 0x0 0x40000>; 256 }; 257 }; 258 259 dwc3_typec1: usb@fe900000 { 260 compatible = "rockchip,rk3399-xhci"; 261 reg = <0x0 0xfe900000 0x0 0x100000>; 262 status = "disabled"; 263 snps,dis-enblslpm-quirk; 264 snps,phyif-utmi-bits = <16>; 265 snps,dis-u2-freeclk-exists-quirk; 266 snps,dis-u2-susphy-quirk; 267 268 #address-cells = <2>; 269 #size-cells = <2>; 270 hub { 271 compatible = "usb-hub"; 272 usb,device-class = <USB_CLASS_HUB>; 273 }; 274 typec_phy1 { 275 compatible = "rockchip,rk3399-usb3-phy"; 276 reg = <0x0 0xff800000 0x0 0x40000>; 277 }; 278 }; 279 280 gic: interrupt-controller@fee00000 { 281 compatible = "arm,gic-v3"; 282 #interrupt-cells = <3>; 283 #address-cells = <2>; 284 #size-cells = <2>; 285 ranges; 286 interrupt-controller; 287 288 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 289 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 290 <0x0 0xfff00000 0 0x10000>, /* GICC */ 291 <0x0 0xfff10000 0 0x10000>, /* GICH */ 292 <0x0 0xfff20000 0 0x10000>; /* GICV */ 293 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 294 its: interrupt-controller@fee20000 { 295 compatible = "arm,gic-v3-its"; 296 msi-controller; 297 reg = <0x0 0xfee20000 0x0 0x20000>; 298 }; 299 }; 300 301 uart0: serial@ff180000 { 302 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 303 reg = <0x0 0xff180000 0x0 0x100>; 304 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 305 clock-names = "baudclk", "apb_pclk"; 306 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 307 reg-shift = <2>; 308 reg-io-width = <4>; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&uart0_xfer>; 311 status = "disabled"; 312 }; 313 314 uart1: serial@ff190000 { 315 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 316 reg = <0x0 0xff190000 0x0 0x100>; 317 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 318 clock-names = "baudclk", "apb_pclk"; 319 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 320 reg-shift = <2>; 321 reg-io-width = <4>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&uart1_xfer>; 324 status = "disabled"; 325 }; 326 327 uart2: serial@ff1a0000 { 328 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 329 reg = <0x0 0xff1a0000 0x0 0x100>; 330 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 331 clock-names = "baudclk", "apb_pclk"; 332 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 333 clock-frequency = <24000000>; 334 reg-shift = <2>; 335 reg-io-width = <4>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&uart2c_xfer>; 338 status = "disabled"; 339 }; 340 341 uart3: serial@ff1b0000 { 342 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 343 reg = <0x0 0xff1b0000 0x0 0x100>; 344 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 345 clock-names = "baudclk", "apb_pclk"; 346 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 347 reg-shift = <2>; 348 reg-io-width = <4>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&uart3_xfer>; 351 status = "disabled"; 352 }; 353 354 spi0: spi@ff1c0000 { 355 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 356 reg = <0x0 0xff1c0000 0x0 0x1000>; 357 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 358 clock-names = "spiclk", "apb_pclk"; 359 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 status = "disabled"; 365 }; 366 367 spi1: spi@ff1d0000 { 368 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 369 reg = <0x0 0xff1d0000 0x0 0x1000>; 370 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 371 clock-names = "spiclk", "apb_pclk"; 372 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 status = "disabled"; 378 }; 379 380 spi2: spi@ff1e0000 { 381 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 382 reg = <0x0 0xff1e0000 0x0 0x1000>; 383 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 384 clock-names = "spiclk", "apb_pclk"; 385 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 spi4: spi@ff1f0000 { 394 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 395 reg = <0x0 0xff1f0000 0x0 0x1000>; 396 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 397 clock-names = "spiclk", "apb_pclk"; 398 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 status = "disabled"; 404 }; 405 406 spi5: spi@ff200000 { 407 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 408 reg = <0x0 0xff200000 0x0 0x1000>; 409 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 410 clock-names = "spiclk", "apb_pclk"; 411 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 status = "disabled"; 417 }; 418 419 pmugrf: syscon@ff320000 { 420 u-boot,dm-pre-reloc; 421 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 422 reg = <0x0 0xff320000 0x0 0x1000>; 423 #address-cells = <1>; 424 #size-cells = <1>; 425 426 pmu_io_domains: io-domains { 427 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 428 status = "disabled"; 429 }; 430 }; 431 432 pmusgrf: syscon@ff330000 { 433 u-boot,dm-pre-reloc; 434 compatible = "rockchip,rk3399-pmusgrf", "syscon"; 435 reg = <0x0 0xff330000 0x0 0xe3d4>; 436 }; 437 438 spi3: spi@ff350000 { 439 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 440 reg = <0x0 0xff350000 0x0 0x1000>; 441 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 442 clock-names = "spiclk", "apb_pclk"; 443 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 status = "disabled"; 449 }; 450 451 uart4: serial@ff370000 { 452 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 453 reg = <0x0 0xff370000 0x0 0x100>; 454 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 455 clock-names = "baudclk", "apb_pclk"; 456 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 457 reg-shift = <2>; 458 reg-io-width = <4>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&uart4_xfer>; 461 status = "disabled"; 462 }; 463 464 pwm0: pwm@ff420000 { 465 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 466 reg = <0x0 0xff420000 0x0 0x10>; 467 #pwm-cells = <3>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pwm0_pin>; 470 clocks = <&pmucru PCLK_RKPWM_PMU>; 471 clock-names = "pwm"; 472 status = "disabled"; 473 }; 474 475 pwm1: pwm@ff420010 { 476 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 477 reg = <0x0 0xff420010 0x0 0x10>; 478 #pwm-cells = <3>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pwm1_pin>; 481 clocks = <&pmucru PCLK_RKPWM_PMU>; 482 clock-names = "pwm"; 483 status = "disabled"; 484 }; 485 486 pwm2: pwm@ff420020 { 487 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 488 reg = <0x0 0xff420020 0x0 0x10>; 489 #pwm-cells = <3>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pwm2_pin>; 492 clocks = <&pmucru PCLK_RKPWM_PMU>; 493 clock-names = "pwm"; 494 status = "disabled"; 495 }; 496 497 pwm3: pwm@ff420030 { 498 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 499 reg = <0x0 0xff420030 0x0 0x10>; 500 #pwm-cells = <3>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&pwm3a_pin>; 503 clocks = <&pmucru PCLK_RKPWM_PMU>; 504 clock-names = "pwm"; 505 status = "disabled"; 506 }; 507 508 cic: syscon@ff620000 { 509 u-boot,dm-pre-reloc; 510 compatible = "rockchip,rk3399-cic", "syscon"; 511 reg = <0x0 0xff620000 0x0 0x100>; 512 }; 513 514 dfi: dfi@ff630000 { 515 reg = <0x00 0xff630000 0x00 0x4000>; 516 compatible = "rockchip,rk3399-dfi"; 517 rockchip,pmu = <&pmugrf>; 518 clocks = <&cru PCLK_DDR_MON>; 519 clock-names = "pclk_ddr_mon"; 520 status = "disabled"; 521 }; 522 523 dmc: dmc { 524 u-boot,dm-pre-reloc; 525 compatible = "rockchip,rk3399-dmc"; 526 devfreq-events = <&dfi>; 527 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 528 clocks = <&cru SCLK_DDRCLK>; 529 clock-names = "dmc_clk"; 530 reg = <0x0 0xffa80000 0x0 0x0800 531 0x0 0xffa80800 0x0 0x1800 532 0x0 0xffa82000 0x0 0x2000 533 0x0 0xffa84000 0x0 0x1000 534 0x0 0xffa88000 0x0 0x0800 535 0x0 0xffa88800 0x0 0x1800 536 0x0 0xffa8a000 0x0 0x2000 537 0x0 0xffa8c000 0x0 0x1000>; 538 }; 539 540 pmucru: pmu-clock-controller@ff750000 { 541 u-boot,dm-pre-reloc; 542 compatible = "rockchip,rk3399-pmucru"; 543 reg = <0x0 0xff750000 0x0 0x1000>; 544 #clock-cells = <1>; 545 #reset-cells = <1>; 546 assigned-clocks = <&pmucru PLL_PPLL>; 547 assigned-clock-rates = <676000000>; 548 }; 549 550 cru: clock-controller@ff760000 { 551 u-boot,dm-pre-reloc; 552 compatible = "rockchip,rk3399-cru"; 553 reg = <0x0 0xff760000 0x0 0x1000>; 554 #clock-cells = <1>; 555 #reset-cells = <1>; 556 assigned-clocks = 557 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 558 <&cru PLL_NPLL>, 559 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 560 <&cru PCLK_PERIHP>, 561 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 562 <&cru PCLK_PERILP0>, 563 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 564 assigned-clock-rates = 565 <594000000>, <800000000>, 566 <1000000000>, 567 <150000000>, <75000000>, 568 <37500000>, 569 <100000000>, <100000000>, 570 <50000000>, 571 <100000000>, <50000000>; 572 }; 573 574 grf: syscon@ff770000 { 575 u-boot,dm-pre-reloc; 576 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 577 reg = <0x0 0xff770000 0x0 0x10000>; 578 #address-cells = <1>; 579 #size-cells = <1>; 580 581 io_domains: io-domains { 582 compatible = "rockchip,rk3399-io-voltage-domain"; 583 status = "disabled"; 584 }; 585 586 emmc_phy: phy@f780 { 587 compatible = "rockchip,rk3399-emmc-phy"; 588 reg = <0xf780 0x24>; 589 #phy-cells = <0>; 590 status = "disabled"; 591 }; 592 }; 593 594 watchdog@ff840000 { 595 compatible = "snps,dw-wdt"; 596 reg = <0x0 0xff840000 0x0 0x100>; 597 clocks = <&cru PCLK_WDT>; 598 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 599 }; 600 601 gmac: eth@fe300000 { 602 compatible = "rockchip,rk3399-gmac"; 603 reg = <0x0 0xfe300000 0x0 0x10000>; 604 rockchip,grf = <&grf>; 605 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 606 interrupt-names = "macirq"; 607 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 608 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 609 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 610 <&cru PCLK_GMAC>; 611 clock-names = "stmmaceth", "mac_clk_rx", 612 "mac_clk_tx", "clk_mac_ref", 613 "clk_mac_refout", "aclk_mac", 614 "pclk_mac"; 615 resets = <&cru SRST_A_GMAC>; 616 reset-names = "stmmaceth"; 617 status = "disabled"; 618 }; 619 620 spdif: spdif@ff870000 { 621 compatible = "rockchip,rk3399-spdif"; 622 reg = <0x0 0xff870000 0x0 0x1000>; 623 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 624 dmas = <&dmac_bus 7>; 625 dma-names = "tx"; 626 clock-names = "mclk", "hclk"; 627 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&spdif_bus>; 630 status = "disabled"; 631 }; 632 633 i2s0: i2s@ff880000 { 634 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 635 reg = <0x0 0xff880000 0x0 0x1000>; 636 rockchip,grf = <&grf>; 637 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 638 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 639 dma-names = "tx", "rx"; 640 clock-names = "i2s_clk", "i2s_hclk"; 641 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&i2s0_8ch_bus>; 644 status = "disabled"; 645 }; 646 647 i2s1: i2s@ff890000 { 648 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 649 reg = <0x0 0xff890000 0x0 0x1000>; 650 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 651 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 652 dma-names = "tx", "rx"; 653 clock-names = "i2s_clk", "i2s_hclk"; 654 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&i2s1_2ch_bus>; 657 status = "disabled"; 658 }; 659 660 i2s2: i2s@ff8a0000 { 661 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 662 reg = <0x0 0xff8a0000 0x0 0x1000>; 663 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 664 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 665 dma-names = "tx", "rx"; 666 clock-names = "i2s_clk", "i2s_hclk"; 667 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 668 status = "disabled"; 669 }; 670 671 pinctrl: pinctrl { 672 u-boot,dm-pre-reloc; 673 compatible = "rockchip,rk3399-pinctrl"; 674 rockchip,grf = <&grf>; 675 rockchip,pmu = <&pmugrf>; 676 #address-cells = <2>; 677 #size-cells = <2>; 678 ranges; 679 680 gpio0: gpio0@ff720000 { 681 compatible = "rockchip,gpio-bank"; 682 reg = <0x0 0xff720000 0x0 0x100>; 683 clocks = <&pmucru PCLK_GPIO0_PMU>; 684 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 685 686 gpio-controller; 687 #gpio-cells = <0x2>; 688 689 interrupt-controller; 690 #interrupt-cells = <0x2>; 691 }; 692 693 gpio1: gpio1@ff730000 { 694 compatible = "rockchip,gpio-bank"; 695 reg = <0x0 0xff730000 0x0 0x100>; 696 clocks = <&pmucru PCLK_GPIO1_PMU>; 697 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 698 699 gpio-controller; 700 #gpio-cells = <0x2>; 701 702 interrupt-controller; 703 #interrupt-cells = <0x2>; 704 }; 705 706 gpio2: gpio2@ff780000 { 707 compatible = "rockchip,gpio-bank"; 708 reg = <0x0 0xff780000 0x0 0x100>; 709 clocks = <&cru PCLK_GPIO2>; 710 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 711 712 gpio-controller; 713 #gpio-cells = <0x2>; 714 715 interrupt-controller; 716 #interrupt-cells = <0x2>; 717 }; 718 719 gpio3: gpio3@ff788000 { 720 compatible = "rockchip,gpio-bank"; 721 reg = <0x0 0xff788000 0x0 0x100>; 722 clocks = <&cru PCLK_GPIO3>; 723 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 724 725 gpio-controller; 726 #gpio-cells = <0x2>; 727 728 interrupt-controller; 729 #interrupt-cells = <0x2>; 730 }; 731 732 gpio4: gpio4@ff790000 { 733 compatible = "rockchip,gpio-bank"; 734 reg = <0x0 0xff790000 0x0 0x100>; 735 clocks = <&cru PCLK_GPIO4>; 736 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 737 738 gpio-controller; 739 #gpio-cells = <0x2>; 740 741 interrupt-controller; 742 #interrupt-cells = <0x2>; 743 }; 744 745 pcfg_pull_up: pcfg-pull-up { 746 bias-pull-up; 747 }; 748 749 pcfg_pull_down: pcfg-pull-down { 750 bias-pull-down; 751 }; 752 753 pcfg_pull_none: pcfg-pull-none { 754 bias-disable; 755 }; 756 757 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 758 bias-disable; 759 drive-strength = <12>; 760 }; 761 762 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 763 bias-pull-up; 764 drive-strength = <8>; 765 }; 766 767 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 768 bias-pull-down; 769 drive-strength = <4>; 770 }; 771 772 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 773 bias-pull-up; 774 drive-strength = <2>; 775 }; 776 777 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 778 bias-pull-down; 779 drive-strength = <12>; 780 }; 781 782 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 783 bias-disable; 784 drive-strength = <13>; 785 }; 786 787 i2c0 { 788 i2c0_xfer: i2c0-xfer { 789 rockchip,pins = 790 <1 15 RK_FUNC_2 &pcfg_pull_none>, 791 <1 16 RK_FUNC_2 &pcfg_pull_none>; 792 }; 793 }; 794 795 i2c1 { 796 i2c1_xfer: i2c1-xfer { 797 rockchip,pins = 798 <4 2 RK_FUNC_1 &pcfg_pull_none>, 799 <4 1 RK_FUNC_1 &pcfg_pull_none>; 800 }; 801 }; 802 803 i2c2 { 804 i2c2_xfer: i2c2-xfer { 805 rockchip,pins = 806 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 807 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 808 }; 809 }; 810 811 i2c3 { 812 i2c3_xfer: i2c3-xfer { 813 rockchip,pins = 814 <4 17 RK_FUNC_1 &pcfg_pull_none>, 815 <4 16 RK_FUNC_1 &pcfg_pull_none>; 816 }; 817 }; 818 819 i2c4 { 820 i2c4_xfer: i2c4-xfer { 821 rockchip,pins = 822 <1 12 RK_FUNC_1 &pcfg_pull_none>, 823 <1 11 RK_FUNC_1 &pcfg_pull_none>; 824 }; 825 }; 826 827 i2c5 { 828 i2c5_xfer: i2c5-xfer { 829 rockchip,pins = 830 <3 11 RK_FUNC_2 &pcfg_pull_none>, 831 <3 10 RK_FUNC_2 &pcfg_pull_none>; 832 }; 833 }; 834 835 i2c6 { 836 i2c6_xfer: i2c6-xfer { 837 rockchip,pins = 838 <2 10 RK_FUNC_2 &pcfg_pull_none>, 839 <2 9 RK_FUNC_2 &pcfg_pull_none>; 840 }; 841 }; 842 843 i2c7 { 844 i2c7_xfer: i2c7-xfer { 845 rockchip,pins = 846 <2 8 RK_FUNC_2 &pcfg_pull_none>, 847 <2 7 RK_FUNC_2 &pcfg_pull_none>; 848 }; 849 }; 850 851 i2c8 { 852 i2c8_xfer: i2c8-xfer { 853 rockchip,pins = 854 <1 21 RK_FUNC_1 &pcfg_pull_none>, 855 <1 20 RK_FUNC_1 &pcfg_pull_none>; 856 }; 857 }; 858 859 i2s0 { 860 i2s0_8ch_bus: i2s0-8ch-bus { 861 rockchip,pins = 862 <3 24 RK_FUNC_1 &pcfg_pull_none>, 863 <3 25 RK_FUNC_1 &pcfg_pull_none>, 864 <3 26 RK_FUNC_1 &pcfg_pull_none>, 865 <3 27 RK_FUNC_1 &pcfg_pull_none>, 866 <3 28 RK_FUNC_1 &pcfg_pull_none>, 867 <3 29 RK_FUNC_1 &pcfg_pull_none>, 868 <3 30 RK_FUNC_1 &pcfg_pull_none>, 869 <3 31 RK_FUNC_1 &pcfg_pull_none>, 870 <4 0 RK_FUNC_1 &pcfg_pull_none>; 871 }; 872 }; 873 874 i2s1 { 875 i2s1_2ch_bus: i2s1-2ch-bus { 876 rockchip,pins = 877 <4 3 RK_FUNC_1 &pcfg_pull_none>, 878 <4 4 RK_FUNC_1 &pcfg_pull_none>, 879 <4 5 RK_FUNC_1 &pcfg_pull_none>, 880 <4 6 RK_FUNC_1 &pcfg_pull_none>, 881 <4 7 RK_FUNC_1 &pcfg_pull_none>; 882 }; 883 }; 884 885 gmac { 886 rgmii_pins: rgmii-pins { 887 rockchip,pins = 888 /* mac_txclk */ 889 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, 890 /* mac_rxclk */ 891 <3 14 RK_FUNC_1 &pcfg_pull_none>, 892 /* mac_mdio */ 893 <3 13 RK_FUNC_1 &pcfg_pull_none>, 894 /* mac_txen */ 895 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, 896 /* mac_clk */ 897 <3 11 RK_FUNC_1 &pcfg_pull_none>, 898 /* mac_rxdv */ 899 <3 9 RK_FUNC_1 &pcfg_pull_none>, 900 /* mac_mdc */ 901 <3 8 RK_FUNC_1 &pcfg_pull_none>, 902 /* mac_rxd1 */ 903 <3 7 RK_FUNC_1 &pcfg_pull_none>, 904 /* mac_rxd0 */ 905 <3 6 RK_FUNC_1 &pcfg_pull_none>, 906 /* mac_txd1 */ 907 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, 908 /* mac_txd0 */ 909 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, 910 /* mac_rxd3 */ 911 <3 3 RK_FUNC_1 &pcfg_pull_none>, 912 /* mac_rxd2 */ 913 <3 2 RK_FUNC_1 &pcfg_pull_none>, 914 /* mac_txd3 */ 915 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, 916 /* mac_txd2 */ 917 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; 918 }; 919 }; 920 921 sdmmc { 922 sdmmc_bus1: sdmmc-bus1 { 923 rockchip,pins = 924 <4 8 RK_FUNC_1 &pcfg_pull_up>; 925 }; 926 927 sdmmc_bus4: sdmmc-bus4 { 928 rockchip,pins = 929 <4 8 RK_FUNC_1 &pcfg_pull_up>, 930 <4 9 RK_FUNC_1 &pcfg_pull_up>, 931 <4 10 RK_FUNC_1 &pcfg_pull_up>, 932 <4 11 RK_FUNC_1 &pcfg_pull_up>; 933 }; 934 935 sdmmc_clk: sdmmc-clk { 936 rockchip,pins = 937 <4 12 RK_FUNC_1 &pcfg_pull_none>; 938 }; 939 940 sdmmc_cmd: sdmmc-cmd { 941 rockchip,pins = 942 <4 13 RK_FUNC_1 &pcfg_pull_up>; 943 }; 944 945 sdmmc_cd: sdmcc-cd { 946 rockchip,pins = 947 <0 7 RK_FUNC_1 &pcfg_pull_up>; 948 }; 949 950 sdmmc_wp: sdmmc-wp { 951 rockchip,pins = 952 <0 8 RK_FUNC_1 &pcfg_pull_up>; 953 }; 954 }; 955 956 spdif { 957 spdif_bus: spdif-bus { 958 rockchip,pins = 959 <4 21 RK_FUNC_1 &pcfg_pull_none>; 960 }; 961 }; 962 963 spi0 { 964 spi0_clk: spi0-clk { 965 rockchip,pins = 966 <3 6 RK_FUNC_2 &pcfg_pull_up>; 967 }; 968 spi0_cs0: spi0-cs0 { 969 rockchip,pins = 970 <3 7 RK_FUNC_2 &pcfg_pull_up>; 971 }; 972 spi0_cs1: spi0-cs1 { 973 rockchip,pins = 974 <3 8 RK_FUNC_2 &pcfg_pull_up>; 975 }; 976 spi0_tx: spi0-tx { 977 rockchip,pins = 978 <3 5 RK_FUNC_2 &pcfg_pull_up>; 979 }; 980 spi0_rx: spi0-rx { 981 rockchip,pins = 982 <3 4 RK_FUNC_2 &pcfg_pull_up>; 983 }; 984 }; 985 986 spi1 { 987 spi1_clk: spi1-clk { 988 rockchip,pins = 989 <1 9 RK_FUNC_2 &pcfg_pull_up>; 990 }; 991 spi1_cs0: spi1-cs0 { 992 rockchip,pins = 993 <1 10 RK_FUNC_2 &pcfg_pull_up>; 994 }; 995 spi1_rx: spi1-rx { 996 rockchip,pins = 997 <1 7 RK_FUNC_2 &pcfg_pull_up>; 998 }; 999 spi1_tx: spi1-tx { 1000 rockchip,pins = 1001 <1 8 RK_FUNC_2 &pcfg_pull_up>; 1002 }; 1003 }; 1004 1005 spi2 { 1006 spi2_clk: spi2-clk { 1007 rockchip,pins = 1008 <2 11 RK_FUNC_1 &pcfg_pull_up>; 1009 }; 1010 spi2_cs0: spi2-cs0 { 1011 rockchip,pins = 1012 <2 12 RK_FUNC_1 &pcfg_pull_up>; 1013 }; 1014 spi2_rx: spi2-rx { 1015 rockchip,pins = 1016 <2 9 RK_FUNC_1 &pcfg_pull_up>; 1017 }; 1018 spi2_tx: spi2-tx { 1019 rockchip,pins = 1020 <2 10 RK_FUNC_1 &pcfg_pull_up>; 1021 }; 1022 }; 1023 1024 spi3 { 1025 spi3_clk: spi3-clk { 1026 rockchip,pins = 1027 <1 17 RK_FUNC_1 &pcfg_pull_up>; 1028 }; 1029 spi3_cs0: spi3-cs0 { 1030 rockchip,pins = 1031 <1 18 RK_FUNC_1 &pcfg_pull_up>; 1032 }; 1033 spi3_rx: spi3-rx { 1034 rockchip,pins = 1035 <1 15 RK_FUNC_1 &pcfg_pull_up>; 1036 }; 1037 spi3_tx: spi3-tx { 1038 rockchip,pins = 1039 <1 16 RK_FUNC_1 &pcfg_pull_up>; 1040 }; 1041 }; 1042 1043 spi4 { 1044 spi4_clk: spi4-clk { 1045 rockchip,pins = 1046 <3 2 RK_FUNC_2 &pcfg_pull_up>; 1047 }; 1048 spi4_cs0: spi4-cs0 { 1049 rockchip,pins = 1050 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1051 }; 1052 spi4_rx: spi4-rx { 1053 rockchip,pins = 1054 <3 0 RK_FUNC_2 &pcfg_pull_up>; 1055 }; 1056 spi4_tx: spi4-tx { 1057 rockchip,pins = 1058 <3 1 RK_FUNC_2 &pcfg_pull_up>; 1059 }; 1060 }; 1061 1062 spi5 { 1063 spi5_clk: spi5-clk { 1064 rockchip,pins = 1065 <2 22 RK_FUNC_2 &pcfg_pull_up>; 1066 }; 1067 spi5_cs0: spi5-cs0 { 1068 rockchip,pins = 1069 <2 23 RK_FUNC_2 &pcfg_pull_up>; 1070 }; 1071 spi5_rx: spi5-rx { 1072 rockchip,pins = 1073 <2 20 RK_FUNC_2 &pcfg_pull_up>; 1074 }; 1075 spi5_tx: spi5-tx { 1076 rockchip,pins = 1077 <2 21 RK_FUNC_2 &pcfg_pull_up>; 1078 }; 1079 }; 1080 1081 uart0 { 1082 uart0_xfer: uart0-xfer { 1083 rockchip,pins = 1084 <2 16 RK_FUNC_1 &pcfg_pull_up>, 1085 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1086 }; 1087 1088 uart0_cts: uart0-cts { 1089 rockchip,pins = 1090 <2 18 RK_FUNC_1 &pcfg_pull_none>; 1091 }; 1092 1093 uart0_rts: uart0-rts { 1094 rockchip,pins = 1095 <2 19 RK_FUNC_1 &pcfg_pull_none>; 1096 }; 1097 }; 1098 1099 uart1 { 1100 uart1_xfer: uart1-xfer { 1101 rockchip,pins = 1102 <3 12 RK_FUNC_2 &pcfg_pull_up>, 1103 <3 13 RK_FUNC_2 &pcfg_pull_none>; 1104 }; 1105 }; 1106 1107 uart2a { 1108 uart2a_xfer: uart2a-xfer { 1109 rockchip,pins = 1110 <4 8 RK_FUNC_2 &pcfg_pull_up>, 1111 <4 9 RK_FUNC_2 &pcfg_pull_none>; 1112 }; 1113 }; 1114 1115 uart2b { 1116 uart2b_xfer: uart2b-xfer { 1117 rockchip,pins = 1118 <4 16 RK_FUNC_2 &pcfg_pull_up>, 1119 <4 17 RK_FUNC_2 &pcfg_pull_none>; 1120 }; 1121 }; 1122 1123 uart2c { 1124 uart2c_xfer: uart2c-xfer { 1125 rockchip,pins = 1126 <4 19 RK_FUNC_1 &pcfg_pull_up>, 1127 <4 20 RK_FUNC_1 &pcfg_pull_none>; 1128 }; 1129 }; 1130 1131 uart3 { 1132 uart3_xfer: uart3-xfer { 1133 rockchip,pins = 1134 <3 14 RK_FUNC_2 &pcfg_pull_up>, 1135 <3 15 RK_FUNC_2 &pcfg_pull_none>; 1136 }; 1137 1138 uart3_cts: uart3-cts { 1139 rockchip,pins = 1140 <3 18 RK_FUNC_2 &pcfg_pull_none>; 1141 }; 1142 1143 uart3_rts: uart3-rts { 1144 rockchip,pins = 1145 <3 19 RK_FUNC_2 &pcfg_pull_none>; 1146 }; 1147 }; 1148 1149 uart4 { 1150 uart4_xfer: uart4-xfer { 1151 rockchip,pins = 1152 <1 7 RK_FUNC_1 &pcfg_pull_up>, 1153 <1 8 RK_FUNC_1 &pcfg_pull_none>; 1154 }; 1155 }; 1156 1157 uarthdcp { 1158 uarthdcp_xfer: uarthdcp-xfer { 1159 rockchip,pins = 1160 <4 21 RK_FUNC_2 &pcfg_pull_up>, 1161 <4 22 RK_FUNC_2 &pcfg_pull_none>; 1162 }; 1163 }; 1164 1165 pwm0 { 1166 pwm0_pin: pwm0-pin { 1167 rockchip,pins = 1168 <4 18 RK_FUNC_1 &pcfg_pull_none>; 1169 }; 1170 1171 vop0_pwm_pin: vop0-pwm-pin { 1172 rockchip,pins = 1173 <4 18 RK_FUNC_2 &pcfg_pull_none>; 1174 }; 1175 }; 1176 1177 pwm1 { 1178 pwm1_pin: pwm1-pin { 1179 rockchip,pins = 1180 <4 22 RK_FUNC_1 &pcfg_pull_none>; 1181 }; 1182 1183 vop1_pwm_pin: vop1-pwm-pin { 1184 rockchip,pins = 1185 <4 18 RK_FUNC_3 &pcfg_pull_none>; 1186 }; 1187 }; 1188 1189 pwm2 { 1190 pwm2_pin: pwm2-pin { 1191 rockchip,pins = 1192 <1 19 RK_FUNC_1 &pcfg_pull_none>; 1193 }; 1194 }; 1195 1196 pwm3a { 1197 pwm3a_pin: pwm3a-pin { 1198 rockchip,pins = 1199 <0 6 RK_FUNC_1 &pcfg_pull_none>; 1200 }; 1201 }; 1202 1203 pwm3b { 1204 pwm3b_pin: pwm3b-pin { 1205 rockchip,pins = 1206 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1207 }; 1208 }; 1209 }; 1210}; 1211