1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#define USB_CLASS_HUB 9 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 serial3 = &uart3; 26 serial4 = &uart4; 27 }; 28 29 cpus { 30 #address-cells = <2>; 31 #size-cells = <0>; 32 33 cpu-map { 34 cluster0 { 35 core0 { 36 cpu = <&cpu_l0>; 37 }; 38 core1 { 39 cpu = <&cpu_l1>; 40 }; 41 core2 { 42 cpu = <&cpu_l2>; 43 }; 44 core3 { 45 cpu = <&cpu_l3>; 46 }; 47 }; 48 49 cluster1 { 50 core0 { 51 cpu = <&cpu_b0>; 52 }; 53 core1 { 54 cpu = <&cpu_b1>; 55 }; 56 }; 57 }; 58 59 cpu_l0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <0x0 0x0>; 63 enable-method = "psci"; 64 #cooling-cells = <2>; /* min followed by max */ 65 clocks = <&cru ARMCLKL>; 66 }; 67 68 cpu_l1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53", "arm,armv8"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 clocks = <&cru ARMCLKL>; 74 }; 75 76 cpu_l2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 clocks = <&cru ARMCLKL>; 82 }; 83 84 cpu_l3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53", "arm,armv8"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 clocks = <&cru ARMCLKL>; 90 }; 91 92 cpu_b0: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a72", "arm,armv8"; 95 reg = <0x0 0x100>; 96 enable-method = "psci"; 97 #cooling-cells = <2>; /* min followed by max */ 98 clocks = <&cru ARMCLKB>; 99 }; 100 101 cpu_b1: cpu@101 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a72", "arm,armv8"; 104 reg = <0x0 0x101>; 105 enable-method = "psci"; 106 clocks = <&cru ARMCLKB>; 107 }; 108 }; 109 110 psci { 111 compatible = "arm,psci-1.0"; 112 method = "smc"; 113 }; 114 115 timer { 116 compatible = "arm,armv8-timer"; 117 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 118 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 119 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 120 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 121 }; 122 123 xin24m: xin24m { 124 compatible = "fixed-clock"; 125 clock-frequency = <24000000>; 126 clock-output-names = "xin24m"; 127 #clock-cells = <0>; 128 }; 129 130 amba { 131 compatible = "simple-bus"; 132 #address-cells = <2>; 133 #size-cells = <2>; 134 ranges; 135 136 dmac_bus: dma-controller@ff6d0000 { 137 compatible = "arm,pl330", "arm,primecell"; 138 reg = <0x0 0xff6d0000 0x0 0x4000>; 139 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 141 #dma-cells = <1>; 142 clocks = <&cru ACLK_DMAC0_PERILP>; 143 clock-names = "apb_pclk"; 144 }; 145 146 dmac_peri: dma-controller@ff6e0000 { 147 compatible = "arm,pl330", "arm,primecell"; 148 reg = <0x0 0xff6e0000 0x0 0x4000>; 149 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 151 #dma-cells = <1>; 152 clocks = <&cru ACLK_DMAC1_PERILP>; 153 clock-names = "apb_pclk"; 154 }; 155 }; 156 157 sdio0: dwmmc@fe310000 { 158 compatible = "rockchip,rk3399-dw-mshc", 159 "rockchip,rk3288-dw-mshc"; 160 reg = <0x0 0xfe310000 0x0 0x4000>; 161 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 162 clock-freq-min-max = <400000 150000000>; 163 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 164 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 165 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 166 fifo-depth = <0x100>; 167 status = "disabled"; 168 }; 169 170 sdmmc: dwmmc@fe320000 { 171 compatible = "rockchip,rk3399-dw-mshc", 172 "rockchip,rk3288-dw-mshc"; 173 reg = <0x0 0xfe320000 0x0 0x4000>; 174 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 175 clock-freq-min-max = <400000 150000000>; 176 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, 177 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 178 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&sdmmc_clk>; 181 fifo-depth = <0x100>; 182 status = "disabled"; 183 }; 184 185 sdhci: sdhci@fe330000 { 186 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 187 reg = <0x0 0xfe330000 0x0 0x10000>; 188 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 189 assigned-clocks = <&cru SCLK_EMMC>; 190 assigned-clock-rates = <200000000>; 191 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 192 clock-names = "clk_xin", "clk_ahb"; 193 phys = <&emmc_phy>; 194 phy-names = "phy_arasan"; 195 status = "disabled"; 196 }; 197 198 usb_host0_ehci: usb@fe380000 { 199 compatible = "generic-ehci"; 200 reg = <0x0 0xfe380000 0x0 0x20000>; 201 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 203 clock-names = "hclk_host0", "hclk_host0_arb"; 204 status = "disabled"; 205 }; 206 207 usb_host0_ohci: usb@fe3a0000 { 208 compatible = "generic-ohci"; 209 reg = <0x0 0xfe3a0000 0x0 0x20000>; 210 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 212 clock-names = "hclk_host0", "hclk_host0_arb"; 213 status = "disabled"; 214 }; 215 216 usb_host1_ehci: usb@fe3c0000 { 217 compatible = "generic-ehci"; 218 reg = <0x0 0xfe3c0000 0x0 0x20000>; 219 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 221 clock-names = "hclk_host1", "hclk_host1_arb"; 222 status = "disabled"; 223 }; 224 225 usb_host1_ohci: usb@fe3e0000 { 226 compatible = "generic-ohci"; 227 reg = <0x0 0xfe3e0000 0x0 0x20000>; 228 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 230 clock-names = "hclk_host1", "hclk_host1_arb"; 231 status = "disabled"; 232 }; 233 234 dwc3_typec0: usb@fe800000 { 235 compatible = "rockchip,rk3399-xhci"; 236 reg = <0x0 0xfe800000 0x0 0x100000>; 237 status = "disabled"; 238 rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; 239 snps,dis-enblslpm-quirk; 240 snps,phyif-utmi-bits = <16>; 241 snps,dis-u2-freeclk-exists-quirk; 242 snps,dis-u2-susphy-quirk; 243 244 #address-cells = <2>; 245 #size-cells = <2>; 246 hub { 247 compatible = "usb-hub"; 248 usb,device-class = <USB_CLASS_HUB>; 249 }; 250 typec_phy0 { 251 compatible = "rockchip,rk3399-usb3-phy"; 252 reg = <0x0 0xff7c0000 0x0 0x40000>; 253 }; 254 }; 255 256 dwc3_typec1: usb@fe900000 { 257 compatible = "rockchip,rk3399-xhci"; 258 reg = <0x0 0xfe900000 0x0 0x100000>; 259 status = "disabled"; 260 rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 261 snps,dis-enblslpm-quirk; 262 snps,phyif-utmi-bits = <16>; 263 snps,dis-u2-freeclk-exists-quirk; 264 snps,dis-u2-susphy-quirk; 265 266 #address-cells = <2>; 267 #size-cells = <2>; 268 hub { 269 compatible = "usb-hub"; 270 usb,device-class = <USB_CLASS_HUB>; 271 }; 272 typec_phy1 { 273 compatible = "rockchip,rk3399-usb3-phy"; 274 reg = <0x0 0xff800000 0x0 0x40000>; 275 }; 276 }; 277 278 gic: interrupt-controller@fee00000 { 279 compatible = "arm,gic-v3"; 280 #interrupt-cells = <3>; 281 #address-cells = <2>; 282 #size-cells = <2>; 283 ranges; 284 interrupt-controller; 285 286 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 287 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 288 <0x0 0xfff00000 0 0x10000>, /* GICC */ 289 <0x0 0xfff10000 0 0x10000>, /* GICH */ 290 <0x0 0xfff20000 0 0x10000>; /* GICV */ 291 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 292 its: interrupt-controller@fee20000 { 293 compatible = "arm,gic-v3-its"; 294 msi-controller; 295 reg = <0x0 0xfee20000 0x0 0x20000>; 296 }; 297 }; 298 299 uart0: serial@ff180000 { 300 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 301 reg = <0x0 0xff180000 0x0 0x100>; 302 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 303 clock-names = "baudclk", "apb_pclk"; 304 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 305 reg-shift = <2>; 306 reg-io-width = <4>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&uart0_xfer>; 309 status = "disabled"; 310 }; 311 312 uart1: serial@ff190000 { 313 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 314 reg = <0x0 0xff190000 0x0 0x100>; 315 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 316 clock-names = "baudclk", "apb_pclk"; 317 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 318 reg-shift = <2>; 319 reg-io-width = <4>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&uart1_xfer>; 322 status = "disabled"; 323 }; 324 325 uart2: serial@ff1a0000 { 326 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 327 reg = <0x0 0xff1a0000 0x0 0x100>; 328 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 329 clock-names = "baudclk", "apb_pclk"; 330 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 331 clock-frequency = <24000000>; 332 reg-shift = <2>; 333 reg-io-width = <4>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&uart2c_xfer>; 336 status = "disabled"; 337 }; 338 339 uart3: serial@ff1b0000 { 340 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 341 reg = <0x0 0xff1b0000 0x0 0x100>; 342 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 343 clock-names = "baudclk", "apb_pclk"; 344 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 345 reg-shift = <2>; 346 reg-io-width = <4>; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&uart3_xfer>; 349 status = "disabled"; 350 }; 351 352 spi0: spi@ff1c0000 { 353 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 354 reg = <0x0 0xff1c0000 0x0 0x1000>; 355 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 356 clock-names = "spiclk", "apb_pclk"; 357 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 status = "disabled"; 363 }; 364 365 spi1: spi@ff1d0000 { 366 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 367 reg = <0x0 0xff1d0000 0x0 0x1000>; 368 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 369 clock-names = "spiclk", "apb_pclk"; 370 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 spi2: spi@ff1e0000 { 379 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 380 reg = <0x0 0xff1e0000 0x0 0x1000>; 381 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 382 clock-names = "spiclk", "apb_pclk"; 383 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 status = "disabled"; 389 }; 390 391 spi4: spi@ff1f0000 { 392 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 393 reg = <0x0 0xff1f0000 0x0 0x1000>; 394 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 395 clock-names = "spiclk", "apb_pclk"; 396 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 status = "disabled"; 402 }; 403 404 spi5: spi@ff200000 { 405 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 406 reg = <0x0 0xff200000 0x0 0x1000>; 407 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 408 clock-names = "spiclk", "apb_pclk"; 409 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 status = "disabled"; 415 }; 416 417 pmugrf: syscon@ff320000 { 418 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 419 reg = <0x0 0xff320000 0x0 0x1000>; 420 #address-cells = <1>; 421 #size-cells = <1>; 422 423 pmu_io_domains: io-domains { 424 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 425 status = "disabled"; 426 }; 427 }; 428 429 spi3: spi@ff350000 { 430 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 431 reg = <0x0 0xff350000 0x0 0x1000>; 432 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 433 clock-names = "spiclk", "apb_pclk"; 434 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 status = "disabled"; 440 }; 441 442 uart4: serial@ff370000 { 443 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 444 reg = <0x0 0xff370000 0x0 0x100>; 445 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 446 clock-names = "baudclk", "apb_pclk"; 447 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 448 reg-shift = <2>; 449 reg-io-width = <4>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&uart4_xfer>; 452 status = "disabled"; 453 }; 454 455 pwm0: pwm@ff420000 { 456 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 457 reg = <0x0 0xff420000 0x0 0x10>; 458 #pwm-cells = <3>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&pwm0_pin>; 461 clocks = <&pmucru PCLK_RKPWM_PMU>; 462 clock-names = "pwm"; 463 status = "disabled"; 464 }; 465 466 pwm1: pwm@ff420010 { 467 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 468 reg = <0x0 0xff420010 0x0 0x10>; 469 #pwm-cells = <3>; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&pwm1_pin>; 472 clocks = <&pmucru PCLK_RKPWM_PMU>; 473 clock-names = "pwm"; 474 status = "disabled"; 475 }; 476 477 pwm2: pwm@ff420020 { 478 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 479 reg = <0x0 0xff420020 0x0 0x10>; 480 #pwm-cells = <3>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pwm2_pin>; 483 clocks = <&pmucru PCLK_RKPWM_PMU>; 484 clock-names = "pwm"; 485 status = "disabled"; 486 }; 487 488 pwm3: pwm@ff420030 { 489 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 490 reg = <0x0 0xff420030 0x0 0x10>; 491 #pwm-cells = <3>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pwm3a_pin>; 494 clocks = <&pmucru PCLK_RKPWM_PMU>; 495 clock-names = "pwm"; 496 status = "disabled"; 497 }; 498 499 pmucru: pmu-clock-controller@ff750000 { 500 compatible = "rockchip,rk3399-pmucru"; 501 reg = <0x0 0xff750000 0x0 0x1000>; 502 #clock-cells = <1>; 503 #reset-cells = <1>; 504 assigned-clocks = <&pmucru PLL_PPLL>; 505 assigned-clock-rates = <676000000>; 506 }; 507 508 cru: clock-controller@ff760000 { 509 compatible = "rockchip,rk3399-cru"; 510 reg = <0x0 0xff760000 0x0 0x1000>; 511 #clock-cells = <1>; 512 #reset-cells = <1>; 513 assigned-clocks = 514 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 515 <&cru PLL_NPLL>, 516 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 517 <&cru PCLK_PERIHP>, 518 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 519 <&cru PCLK_PERILP0>, 520 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 521 assigned-clock-rates = 522 <594000000>, <800000000>, 523 <1000000000>, 524 <150000000>, <75000000>, 525 <37500000>, 526 <100000000>, <100000000>, 527 <50000000>, 528 <100000000>, <50000000>; 529 }; 530 531 grf: syscon@ff770000 { 532 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 533 reg = <0x0 0xff770000 0x0 0x10000>; 534 #address-cells = <1>; 535 #size-cells = <1>; 536 537 io_domains: io-domains { 538 compatible = "rockchip,rk3399-io-voltage-domain"; 539 status = "disabled"; 540 }; 541 542 emmc_phy: phy@f780 { 543 compatible = "rockchip,rk3399-emmc-phy"; 544 reg = <0xf780 0x24>; 545 #phy-cells = <0>; 546 status = "disabled"; 547 }; 548 }; 549 550 watchdog@ff840000 { 551 compatible = "snps,dw-wdt"; 552 reg = <0x0 0xff840000 0x0 0x100>; 553 clocks = <&cru PCLK_WDT>; 554 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 555 }; 556 557 spdif: spdif@ff870000 { 558 compatible = "rockchip,rk3399-spdif"; 559 reg = <0x0 0xff870000 0x0 0x1000>; 560 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 561 dmas = <&dmac_bus 7>; 562 dma-names = "tx"; 563 clock-names = "mclk", "hclk"; 564 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&spdif_bus>; 567 status = "disabled"; 568 }; 569 570 i2s0: i2s@ff880000 { 571 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 572 reg = <0x0 0xff880000 0x0 0x1000>; 573 rockchip,grf = <&grf>; 574 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 575 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 576 dma-names = "tx", "rx"; 577 clock-names = "i2s_clk", "i2s_hclk"; 578 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&i2s0_8ch_bus>; 581 status = "disabled"; 582 }; 583 584 i2s1: i2s@ff890000 { 585 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 586 reg = <0x0 0xff890000 0x0 0x1000>; 587 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 588 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 589 dma-names = "tx", "rx"; 590 clock-names = "i2s_clk", "i2s_hclk"; 591 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&i2s1_2ch_bus>; 594 status = "disabled"; 595 }; 596 597 i2s2: i2s@ff8a0000 { 598 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 599 reg = <0x0 0xff8a0000 0x0 0x1000>; 600 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 601 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 602 dma-names = "tx", "rx"; 603 clock-names = "i2s_clk", "i2s_hclk"; 604 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 605 status = "disabled"; 606 }; 607 608 pinctrl: pinctrl { 609 compatible = "rockchip,rk3399-pinctrl"; 610 rockchip,grf = <&grf>; 611 rockchip,pmu = <&pmugrf>; 612 #address-cells = <2>; 613 #size-cells = <2>; 614 ranges; 615 616 gpio0: gpio0@ff720000 { 617 compatible = "rockchip,gpio-bank"; 618 reg = <0x0 0xff720000 0x0 0x100>; 619 clocks = <&pmucru PCLK_GPIO0_PMU>; 620 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 621 622 gpio-controller; 623 #gpio-cells = <0x2>; 624 625 interrupt-controller; 626 #interrupt-cells = <0x2>; 627 }; 628 629 gpio1: gpio1@ff730000 { 630 compatible = "rockchip,gpio-bank"; 631 reg = <0x0 0xff730000 0x0 0x100>; 632 clocks = <&pmucru PCLK_GPIO1_PMU>; 633 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 634 635 gpio-controller; 636 #gpio-cells = <0x2>; 637 638 interrupt-controller; 639 #interrupt-cells = <0x2>; 640 }; 641 642 gpio2: gpio2@ff780000 { 643 compatible = "rockchip,gpio-bank"; 644 reg = <0x0 0xff780000 0x0 0x100>; 645 clocks = <&cru PCLK_GPIO2>; 646 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 647 648 gpio-controller; 649 #gpio-cells = <0x2>; 650 651 interrupt-controller; 652 #interrupt-cells = <0x2>; 653 }; 654 655 gpio3: gpio3@ff788000 { 656 compatible = "rockchip,gpio-bank"; 657 reg = <0x0 0xff788000 0x0 0x100>; 658 clocks = <&cru PCLK_GPIO3>; 659 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 660 661 gpio-controller; 662 #gpio-cells = <0x2>; 663 664 interrupt-controller; 665 #interrupt-cells = <0x2>; 666 }; 667 668 gpio4: gpio4@ff790000 { 669 compatible = "rockchip,gpio-bank"; 670 reg = <0x0 0xff790000 0x0 0x100>; 671 clocks = <&cru PCLK_GPIO4>; 672 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 673 674 gpio-controller; 675 #gpio-cells = <0x2>; 676 677 interrupt-controller; 678 #interrupt-cells = <0x2>; 679 }; 680 681 pcfg_pull_up: pcfg-pull-up { 682 bias-pull-up; 683 }; 684 685 pcfg_pull_down: pcfg-pull-down { 686 bias-pull-down; 687 }; 688 689 pcfg_pull_none: pcfg-pull-none { 690 bias-disable; 691 }; 692 693 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 694 bias-disable; 695 drive-strength = <12>; 696 }; 697 698 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 699 bias-pull-up; 700 drive-strength = <8>; 701 }; 702 703 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 704 bias-pull-down; 705 drive-strength = <4>; 706 }; 707 708 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 709 bias-pull-up; 710 drive-strength = <2>; 711 }; 712 713 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 714 bias-pull-down; 715 drive-strength = <12>; 716 }; 717 718 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 719 bias-disable; 720 drive-strength = <13>; 721 }; 722 723 i2c0 { 724 i2c0_xfer: i2c0-xfer { 725 rockchip,pins = 726 <1 15 RK_FUNC_2 &pcfg_pull_none>, 727 <1 16 RK_FUNC_2 &pcfg_pull_none>; 728 }; 729 }; 730 731 i2c1 { 732 i2c1_xfer: i2c1-xfer { 733 rockchip,pins = 734 <4 2 RK_FUNC_1 &pcfg_pull_none>, 735 <4 1 RK_FUNC_1 &pcfg_pull_none>; 736 }; 737 }; 738 739 i2c2 { 740 i2c2_xfer: i2c2-xfer { 741 rockchip,pins = 742 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 743 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 744 }; 745 }; 746 747 i2c3 { 748 i2c3_xfer: i2c3-xfer { 749 rockchip,pins = 750 <4 17 RK_FUNC_1 &pcfg_pull_none>, 751 <4 16 RK_FUNC_1 &pcfg_pull_none>; 752 }; 753 }; 754 755 i2c4 { 756 i2c4_xfer: i2c4-xfer { 757 rockchip,pins = 758 <1 12 RK_FUNC_1 &pcfg_pull_none>, 759 <1 11 RK_FUNC_1 &pcfg_pull_none>; 760 }; 761 }; 762 763 i2c5 { 764 i2c5_xfer: i2c5-xfer { 765 rockchip,pins = 766 <3 11 RK_FUNC_2 &pcfg_pull_none>, 767 <3 10 RK_FUNC_2 &pcfg_pull_none>; 768 }; 769 }; 770 771 i2c6 { 772 i2c6_xfer: i2c6-xfer { 773 rockchip,pins = 774 <2 10 RK_FUNC_2 &pcfg_pull_none>, 775 <2 9 RK_FUNC_2 &pcfg_pull_none>; 776 }; 777 }; 778 779 i2c7 { 780 i2c7_xfer: i2c7-xfer { 781 rockchip,pins = 782 <2 8 RK_FUNC_2 &pcfg_pull_none>, 783 <2 7 RK_FUNC_2 &pcfg_pull_none>; 784 }; 785 }; 786 787 i2c8 { 788 i2c8_xfer: i2c8-xfer { 789 rockchip,pins = 790 <1 21 RK_FUNC_1 &pcfg_pull_none>, 791 <1 20 RK_FUNC_1 &pcfg_pull_none>; 792 }; 793 }; 794 795 i2s0 { 796 i2s0_8ch_bus: i2s0-8ch-bus { 797 rockchip,pins = 798 <3 24 RK_FUNC_1 &pcfg_pull_none>, 799 <3 25 RK_FUNC_1 &pcfg_pull_none>, 800 <3 26 RK_FUNC_1 &pcfg_pull_none>, 801 <3 27 RK_FUNC_1 &pcfg_pull_none>, 802 <3 28 RK_FUNC_1 &pcfg_pull_none>, 803 <3 29 RK_FUNC_1 &pcfg_pull_none>, 804 <3 30 RK_FUNC_1 &pcfg_pull_none>, 805 <3 31 RK_FUNC_1 &pcfg_pull_none>, 806 <4 0 RK_FUNC_1 &pcfg_pull_none>; 807 }; 808 }; 809 810 i2s1 { 811 i2s1_2ch_bus: i2s1-2ch-bus { 812 rockchip,pins = 813 <4 3 RK_FUNC_1 &pcfg_pull_none>, 814 <4 4 RK_FUNC_1 &pcfg_pull_none>, 815 <4 5 RK_FUNC_1 &pcfg_pull_none>, 816 <4 6 RK_FUNC_1 &pcfg_pull_none>, 817 <4 7 RK_FUNC_1 &pcfg_pull_none>; 818 }; 819 }; 820 821 sdmmc { 822 sdmmc_bus1: sdmmc-bus1 { 823 rockchip,pins = 824 <4 8 RK_FUNC_1 &pcfg_pull_up>; 825 }; 826 827 sdmmc_bus4: sdmmc-bus4 { 828 rockchip,pins = 829 <4 8 RK_FUNC_1 &pcfg_pull_up>, 830 <4 9 RK_FUNC_1 &pcfg_pull_up>, 831 <4 10 RK_FUNC_1 &pcfg_pull_up>, 832 <4 11 RK_FUNC_1 &pcfg_pull_up>; 833 }; 834 835 sdmmc_clk: sdmmc-clk { 836 rockchip,pins = 837 <4 12 RK_FUNC_1 &pcfg_pull_none>; 838 }; 839 840 sdmmc_cmd: sdmmc-cmd { 841 rockchip,pins = 842 <4 13 RK_FUNC_1 &pcfg_pull_up>; 843 }; 844 845 sdmmc_cd: sdmcc-cd { 846 rockchip,pins = 847 <0 7 RK_FUNC_1 &pcfg_pull_up>; 848 }; 849 850 sdmmc_wp: sdmmc-wp { 851 rockchip,pins = 852 <0 8 RK_FUNC_1 &pcfg_pull_up>; 853 }; 854 }; 855 856 spdif { 857 spdif_bus: spdif-bus { 858 rockchip,pins = 859 <4 21 RK_FUNC_1 &pcfg_pull_none>; 860 }; 861 }; 862 863 spi0 { 864 spi0_clk: spi0-clk { 865 rockchip,pins = 866 <3 6 RK_FUNC_2 &pcfg_pull_up>; 867 }; 868 spi0_cs0: spi0-cs0 { 869 rockchip,pins = 870 <3 7 RK_FUNC_2 &pcfg_pull_up>; 871 }; 872 spi0_cs1: spi0-cs1 { 873 rockchip,pins = 874 <3 8 RK_FUNC_2 &pcfg_pull_up>; 875 }; 876 spi0_tx: spi0-tx { 877 rockchip,pins = 878 <3 5 RK_FUNC_2 &pcfg_pull_up>; 879 }; 880 spi0_rx: spi0-rx { 881 rockchip,pins = 882 <3 4 RK_FUNC_2 &pcfg_pull_up>; 883 }; 884 }; 885 886 spi1 { 887 spi1_clk: spi1-clk { 888 rockchip,pins = 889 <1 9 RK_FUNC_2 &pcfg_pull_up>; 890 }; 891 spi1_cs0: spi1-cs0 { 892 rockchip,pins = 893 <1 10 RK_FUNC_2 &pcfg_pull_up>; 894 }; 895 spi1_rx: spi1-rx { 896 rockchip,pins = 897 <1 7 RK_FUNC_2 &pcfg_pull_up>; 898 }; 899 spi1_tx: spi1-tx { 900 rockchip,pins = 901 <1 8 RK_FUNC_2 &pcfg_pull_up>; 902 }; 903 }; 904 905 spi2 { 906 spi2_clk: spi2-clk { 907 rockchip,pins = 908 <2 11 RK_FUNC_1 &pcfg_pull_up>; 909 }; 910 spi2_cs0: spi2-cs0 { 911 rockchip,pins = 912 <2 12 RK_FUNC_1 &pcfg_pull_up>; 913 }; 914 spi2_rx: spi2-rx { 915 rockchip,pins = 916 <2 9 RK_FUNC_1 &pcfg_pull_up>; 917 }; 918 spi2_tx: spi2-tx { 919 rockchip,pins = 920 <2 10 RK_FUNC_1 &pcfg_pull_up>; 921 }; 922 }; 923 924 spi3 { 925 spi3_clk: spi3-clk { 926 rockchip,pins = 927 <1 17 RK_FUNC_1 &pcfg_pull_up>; 928 }; 929 spi3_cs0: spi3-cs0 { 930 rockchip,pins = 931 <1 18 RK_FUNC_1 &pcfg_pull_up>; 932 }; 933 spi3_rx: spi3-rx { 934 rockchip,pins = 935 <1 15 RK_FUNC_1 &pcfg_pull_up>; 936 }; 937 spi3_tx: spi3-tx { 938 rockchip,pins = 939 <1 16 RK_FUNC_1 &pcfg_pull_up>; 940 }; 941 }; 942 943 spi4 { 944 spi4_clk: spi4-clk { 945 rockchip,pins = 946 <3 2 RK_FUNC_2 &pcfg_pull_up>; 947 }; 948 spi4_cs0: spi4-cs0 { 949 rockchip,pins = 950 <3 3 RK_FUNC_2 &pcfg_pull_up>; 951 }; 952 spi4_rx: spi4-rx { 953 rockchip,pins = 954 <3 0 RK_FUNC_2 &pcfg_pull_up>; 955 }; 956 spi4_tx: spi4-tx { 957 rockchip,pins = 958 <3 1 RK_FUNC_2 &pcfg_pull_up>; 959 }; 960 }; 961 962 spi5 { 963 spi5_clk: spi5-clk { 964 rockchip,pins = 965 <2 22 RK_FUNC_2 &pcfg_pull_up>; 966 }; 967 spi5_cs0: spi5-cs0 { 968 rockchip,pins = 969 <2 23 RK_FUNC_2 &pcfg_pull_up>; 970 }; 971 spi5_rx: spi5-rx { 972 rockchip,pins = 973 <2 20 RK_FUNC_2 &pcfg_pull_up>; 974 }; 975 spi5_tx: spi5-tx { 976 rockchip,pins = 977 <2 21 RK_FUNC_2 &pcfg_pull_up>; 978 }; 979 }; 980 981 uart0 { 982 uart0_xfer: uart0-xfer { 983 rockchip,pins = 984 <2 16 RK_FUNC_1 &pcfg_pull_up>, 985 <2 17 RK_FUNC_1 &pcfg_pull_none>; 986 }; 987 988 uart0_cts: uart0-cts { 989 rockchip,pins = 990 <2 18 RK_FUNC_1 &pcfg_pull_none>; 991 }; 992 993 uart0_rts: uart0-rts { 994 rockchip,pins = 995 <2 19 RK_FUNC_1 &pcfg_pull_none>; 996 }; 997 }; 998 999 uart1 { 1000 uart1_xfer: uart1-xfer { 1001 rockchip,pins = 1002 <3 12 RK_FUNC_2 &pcfg_pull_up>, 1003 <3 13 RK_FUNC_2 &pcfg_pull_none>; 1004 }; 1005 }; 1006 1007 uart2a { 1008 uart2a_xfer: uart2a-xfer { 1009 rockchip,pins = 1010 <4 8 RK_FUNC_2 &pcfg_pull_up>, 1011 <4 9 RK_FUNC_2 &pcfg_pull_none>; 1012 }; 1013 }; 1014 1015 uart2b { 1016 uart2b_xfer: uart2b-xfer { 1017 rockchip,pins = 1018 <4 16 RK_FUNC_2 &pcfg_pull_up>, 1019 <4 17 RK_FUNC_2 &pcfg_pull_none>; 1020 }; 1021 }; 1022 1023 uart2c { 1024 uart2c_xfer: uart2c-xfer { 1025 rockchip,pins = 1026 <4 19 RK_FUNC_1 &pcfg_pull_up>, 1027 <4 20 RK_FUNC_1 &pcfg_pull_none>; 1028 }; 1029 }; 1030 1031 uart3 { 1032 uart3_xfer: uart3-xfer { 1033 rockchip,pins = 1034 <3 14 RK_FUNC_2 &pcfg_pull_up>, 1035 <3 15 RK_FUNC_2 &pcfg_pull_none>; 1036 }; 1037 1038 uart3_cts: uart3-cts { 1039 rockchip,pins = 1040 <3 18 RK_FUNC_2 &pcfg_pull_none>; 1041 }; 1042 1043 uart3_rts: uart3-rts { 1044 rockchip,pins = 1045 <3 19 RK_FUNC_2 &pcfg_pull_none>; 1046 }; 1047 }; 1048 1049 uart4 { 1050 uart4_xfer: uart4-xfer { 1051 rockchip,pins = 1052 <1 7 RK_FUNC_1 &pcfg_pull_up>, 1053 <1 8 RK_FUNC_1 &pcfg_pull_none>; 1054 }; 1055 }; 1056 1057 uarthdcp { 1058 uarthdcp_xfer: uarthdcp-xfer { 1059 rockchip,pins = 1060 <4 21 RK_FUNC_2 &pcfg_pull_up>, 1061 <4 22 RK_FUNC_2 &pcfg_pull_none>; 1062 }; 1063 }; 1064 1065 pwm0 { 1066 pwm0_pin: pwm0-pin { 1067 rockchip,pins = 1068 <4 18 RK_FUNC_1 &pcfg_pull_none>; 1069 }; 1070 1071 vop0_pwm_pin: vop0-pwm-pin { 1072 rockchip,pins = 1073 <4 18 RK_FUNC_2 &pcfg_pull_none>; 1074 }; 1075 }; 1076 1077 pwm1 { 1078 pwm1_pin: pwm1-pin { 1079 rockchip,pins = 1080 <4 22 RK_FUNC_1 &pcfg_pull_none>; 1081 }; 1082 1083 vop1_pwm_pin: vop1-pwm-pin { 1084 rockchip,pins = 1085 <4 18 RK_FUNC_3 &pcfg_pull_none>; 1086 }; 1087 }; 1088 1089 pwm2 { 1090 pwm2_pin: pwm2-pin { 1091 rockchip,pins = 1092 <1 19 RK_FUNC_1 &pcfg_pull_none>; 1093 }; 1094 }; 1095 1096 pwm3a { 1097 pwm3a_pin: pwm3a-pin { 1098 rockchip,pins = 1099 <0 6 RK_FUNC_1 &pcfg_pull_none>; 1100 }; 1101 }; 1102 1103 pwm3b { 1104 pwm3b_pin: pwm3b-pin { 1105 rockchip,pins = 1106 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1107 }; 1108 }; 1109 }; 1110}; 1111