1/* 2 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/rk3399-power.h> 13#include <dt-bindings/thermal/thermal.h> 14#define USB_CLASS_HUB 9 15 16/ { 17 compatible = "rockchip,rk3399"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 mmc0 = &sdhci; 39 mmc1 = &sdmmc; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu_l0>; 50 }; 51 core1 { 52 cpu = <&cpu_l1>; 53 }; 54 core2 { 55 cpu = <&cpu_l2>; 56 }; 57 core3 { 58 cpu = <&cpu_l3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu_b0>; 65 }; 66 core1 { 67 cpu = <&cpu_b1>; 68 }; 69 }; 70 }; 71 72 cpu_l0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53", "arm,armv8"; 75 reg = <0x0 0x0>; 76 enable-method = "psci"; 77 #cooling-cells = <2>; /* min followed by max */ 78 clocks = <&cru ARMCLKL>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53", "arm,armv8"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 clocks = <&cru ARMCLKL>; 87 }; 88 89 cpu_l2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53", "arm,armv8"; 92 reg = <0x0 0x2>; 93 enable-method = "psci"; 94 clocks = <&cru ARMCLKL>; 95 }; 96 97 cpu_l3: cpu@3 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53", "arm,armv8"; 100 reg = <0x0 0x3>; 101 enable-method = "psci"; 102 clocks = <&cru ARMCLKL>; 103 }; 104 105 cpu_b0: cpu@100 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a72", "arm,armv8"; 108 reg = <0x0 0x100>; 109 enable-method = "psci"; 110 #cooling-cells = <2>; /* min followed by max */ 111 clocks = <&cru ARMCLKB>; 112 }; 113 114 cpu_b1: cpu@101 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a72", "arm,armv8"; 117 reg = <0x0 0x101>; 118 enable-method = "psci"; 119 clocks = <&cru ARMCLKB>; 120 }; 121 }; 122 123 pmu_a53 { 124 compatible = "arm,cortex-a53-pmu"; 125 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 126 }; 127 128 pmu_a72 { 129 compatible = "arm,cortex-a72-pmu"; 130 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 131 }; 132 133 psci { 134 compatible = "arm,psci-1.0"; 135 method = "smc"; 136 }; 137 138 timer { 139 compatible = "arm,armv8-timer"; 140 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 141 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 142 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 143 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 144 arm,no-tick-in-suspend; 145 }; 146 147 xin24m: xin24m { 148 compatible = "fixed-clock"; 149 clock-frequency = <24000000>; 150 clock-output-names = "xin24m"; 151 #clock-cells = <0>; 152 }; 153 154 amba { 155 compatible = "simple-bus"; 156 #address-cells = <2>; 157 #size-cells = <2>; 158 ranges; 159 160 dmac_bus: dma-controller@ff6d0000 { 161 compatible = "arm,pl330", "arm,primecell"; 162 reg = <0x0 0xff6d0000 0x0 0x4000>; 163 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 164 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 165 #dma-cells = <1>; 166 clocks = <&cru ACLK_DMAC0_PERILP>; 167 clock-names = "apb_pclk"; 168 }; 169 170 dmac_peri: dma-controller@ff6e0000 { 171 compatible = "arm,pl330", "arm,primecell"; 172 reg = <0x0 0xff6e0000 0x0 0x4000>; 173 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 174 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 175 #dma-cells = <1>; 176 clocks = <&cru ACLK_DMAC1_PERILP>; 177 clock-names = "apb_pclk"; 178 }; 179 }; 180 181 pcie0: pcie@f8000000 { 182 compatible = "rockchip,rk3399-pcie"; 183 reg = <0x0 0xf8000000 0x0 0x2000000>, 184 <0x0 0xfd000000 0x0 0x1000000>; 185 reg-names = "axi-base", "apb-base"; 186 #address-cells = <3>; 187 #size-cells = <2>; 188 #interrupt-cells = <1>; 189 aspm-no-l0s; 190 bus-range = <0x0 0x1>; 191 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 192 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 193 clock-names = "aclk", "aclk-perf", 194 "hclk", "pm"; 195 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 196 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 197 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 198 interrupt-names = "sys", "legacy", "client"; 199 interrupt-map-mask = <0 0 0 7>; 200 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 201 <0 0 0 2 &pcie0_intc 1>, 202 <0 0 0 3 &pcie0_intc 2>, 203 <0 0 0 4 &pcie0_intc 3>; 204 linux,pci-domain = <0>; 205 max-link-speed = <1>; 206 msi-map = <0x0 &its 0x0 0x1000>; 207 phys = <&pcie_phy>; 208 phy-names = "pcie-phy"; 209 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 210 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 211 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 212 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 213 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 214 <&cru SRST_A_PCIE>; 215 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 216 "pm", "pclk", "aclk"; 217 status = "disabled"; 218 219 pcie0_intc: interrupt-controller { 220 interrupt-controller; 221 #address-cells = <0>; 222 #interrupt-cells = <1>; 223 }; 224 }; 225 226 gmac: ethernet@fe300000 { 227 compatible = "rockchip,rk3399-gmac"; 228 reg = <0x0 0xfe300000 0x0 0x10000>; 229 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 230 interrupt-names = "macirq"; 231 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 232 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 233 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 234 <&cru PCLK_GMAC>; 235 clock-names = "stmmaceth", "mac_clk_rx", 236 "mac_clk_tx", "clk_mac_ref", 237 "clk_mac_refout", "aclk_mac", 238 "pclk_mac"; 239 power-domains = <&power RK3399_PD_GMAC>; 240 resets = <&cru SRST_A_GMAC>; 241 reset-names = "stmmaceth"; 242 rockchip,grf = <&grf>; 243 status = "disabled"; 244 }; 245 246 sdio0: dwmmc@fe310000 { 247 compatible = "rockchip,rk3399-dw-mshc", 248 "rockchip,rk3288-dw-mshc"; 249 reg = <0x0 0xfe310000 0x0 0x4000>; 250 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 251 max-frequency = <150000000>; 252 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 253 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 254 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 255 fifo-depth = <0x100>; 256 power-domains = <&power RK3399_PD_SDIOAUDIO>; 257 resets = <&cru SRST_SDIO0>; 258 reset-names = "reset"; 259 status = "disabled"; 260 }; 261 262 sdmmc: dwmmc@fe320000 { 263 compatible = "rockchip,rk3399-dw-mshc", 264 "rockchip,rk3288-dw-mshc"; 265 reg = <0x0 0xfe320000 0x0 0x4000>; 266 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 267 max-frequency = <150000000>; 268 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 269 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 270 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 271 fifo-depth = <0x100>; 272 power-domains = <&power RK3399_PD_SD>; 273 resets = <&cru SRST_SDMMC>; 274 reset-names = "reset"; 275 status = "disabled"; 276 }; 277 278 sdhci: sdhci@fe330000 { 279 u-boot,dm-pre-reloc; 280 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 281 reg = <0x0 0xfe330000 0x0 0x10000>; 282 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 283 arasan,soc-ctl-syscon = <&grf>; 284 assigned-clocks = <&cru SCLK_EMMC>; 285 assigned-clock-rates = <200000000>; 286 max-frequency = <200000000>; 287 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 288 clock-names = "clk_xin", "clk_ahb"; 289 clock-output-names = "emmc_cardclock"; 290 #clock-cells = <0>; 291 phys = <&emmc_phy>; 292 phy-names = "phy_arasan"; 293 power-domains = <&power RK3399_PD_EMMC>; 294 status = "disabled"; 295 }; 296 297 usb_host0_ehci: usb@fe380000 { 298 compatible = "generic-ehci"; 299 reg = <0x0 0xfe380000 0x0 0x20000>; 300 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 301 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 302 <&u2phy0>; 303 clock-names = "usbhost", "arbiter", 304 "utmi"; 305 phys = <&u2phy0_host>; 306 phy-names = "usb"; 307 power-domains = <&power RK3399_PD_PERIHP>; 308 status = "disabled"; 309 }; 310 311 usb_host0_ohci: usb@fe3a0000 { 312 compatible = "generic-ohci"; 313 reg = <0x0 0xfe3a0000 0x0 0x20000>; 314 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 315 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 316 <&u2phy0>; 317 clock-names = "usbhost", "arbiter", 318 "utmi"; 319 phys = <&u2phy0_host>; 320 phy-names = "usb"; 321 power-domains = <&power RK3399_PD_PERIHP>; 322 status = "disabled"; 323 }; 324 325 usb_host1_ehci: usb@fe3c0000 { 326 compatible = "generic-ehci"; 327 reg = <0x0 0xfe3c0000 0x0 0x20000>; 328 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 329 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 330 <&u2phy1>; 331 clock-names = "usbhost", "arbiter", 332 "utmi"; 333 phys = <&u2phy1_host>; 334 phy-names = "usb"; 335 power-domains = <&power RK3399_PD_PERIHP>; 336 status = "disabled"; 337 }; 338 339 usb_host1_ohci: usb@fe3e0000 { 340 compatible = "generic-ohci"; 341 reg = <0x0 0xfe3e0000 0x0 0x20000>; 342 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 343 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 344 <&u2phy1>; 345 clock-names = "usbhost", "arbiter", 346 "utmi"; 347 phys = <&u2phy1_host>; 348 phy-names = "usb"; 349 power-domains = <&power RK3399_PD_PERIHP>; 350 status = "disabled"; 351 }; 352 353 dwc3_typec0: usb@fe800000 { 354 compatible = "rockchip,rk3399-xhci"; 355 reg = <0x0 0xfe800000 0x0 0x100000>; 356 status = "disabled"; 357 snps,dis-enblslpm-quirk; 358 snps,phyif-utmi-bits = <16>; 359 snps,dis-u2-freeclk-exists-quirk; 360 snps,dis-u2-susphy-quirk; 361 362 #address-cells = <2>; 363 #size-cells = <2>; 364 hub { 365 compatible = "usb-hub"; 366 usb,device-class = <USB_CLASS_HUB>; 367 }; 368 typec_phy0 { 369 compatible = "rockchip,rk3399-usb3-phy"; 370 reg = <0x0 0xff7c0000 0x0 0x40000>; 371 }; 372 }; 373 374 dwc3_typec1: usb@fe900000 { 375 compatible = "rockchip,rk3399-xhci"; 376 reg = <0x0 0xfe900000 0x0 0x100000>; 377 status = "disabled"; 378 snps,dis-enblslpm-quirk; 379 snps,phyif-utmi-bits = <16>; 380 snps,dis-u2-freeclk-exists-quirk; 381 snps,dis-u2-susphy-quirk; 382 383 #address-cells = <2>; 384 #size-cells = <2>; 385 hub { 386 compatible = "usb-hub"; 387 usb,device-class = <USB_CLASS_HUB>; 388 }; 389 typec_phy1 { 390 compatible = "rockchip,rk3399-usb3-phy"; 391 reg = <0x0 0xff800000 0x0 0x40000>; 392 }; 393 }; 394 395 gic: interrupt-controller@fee00000 { 396 compatible = "arm,gic-v3"; 397 #interrupt-cells = <4>; 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 interrupt-controller; 402 403 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 404 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 405 <0x0 0xfff00000 0 0x10000>, /* GICC */ 406 <0x0 0xfff10000 0 0x10000>, /* GICH */ 407 <0x0 0xfff20000 0 0x10000>; /* GICV */ 408 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 409 its: interrupt-controller@fee20000 { 410 compatible = "arm,gic-v3-its"; 411 msi-controller; 412 reg = <0x0 0xfee20000 0x0 0x20000>; 413 }; 414 415 ppi-partitions { 416 ppi_cluster0: interrupt-partition-0 { 417 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 418 }; 419 420 ppi_cluster1: interrupt-partition-1 { 421 affinity = <&cpu_b0 &cpu_b1>; 422 }; 423 }; 424 }; 425 426 saradc: saradc@ff100000 { 427 compatible = "rockchip,rk3399-saradc"; 428 reg = <0x0 0xff100000 0x0 0x100>; 429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 430 #io-channel-cells = <1>; 431 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 432 clock-names = "saradc", "apb_pclk"; 433 resets = <&cru SRST_P_SARADC>; 434 reset-names = "saradc-apb"; 435 status = "disabled"; 436 }; 437 438 i2c1: i2c@ff110000 { 439 compatible = "rockchip,rk3399-i2c"; 440 reg = <0x0 0xff110000 0x0 0x1000>; 441 assigned-clocks = <&cru SCLK_I2C1>; 442 assigned-clock-rates = <200000000>; 443 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 444 clock-names = "i2c", "pclk"; 445 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&i2c1_xfer>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 status = "disabled"; 451 }; 452 453 i2c2: i2c@ff120000 { 454 compatible = "rockchip,rk3399-i2c"; 455 reg = <0x0 0xff120000 0x0 0x1000>; 456 assigned-clocks = <&cru SCLK_I2C2>; 457 assigned-clock-rates = <200000000>; 458 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 459 clock-names = "i2c", "pclk"; 460 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&i2c2_xfer>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 }; 467 468 i2c3: i2c@ff130000 { 469 compatible = "rockchip,rk3399-i2c"; 470 reg = <0x0 0xff130000 0x0 0x1000>; 471 assigned-clocks = <&cru SCLK_I2C3>; 472 assigned-clock-rates = <200000000>; 473 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 474 clock-names = "i2c", "pclk"; 475 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&i2c3_xfer>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 status = "disabled"; 481 }; 482 483 i2c5: i2c@ff140000 { 484 compatible = "rockchip,rk3399-i2c"; 485 reg = <0x0 0xff140000 0x0 0x1000>; 486 assigned-clocks = <&cru SCLK_I2C5>; 487 assigned-clock-rates = <200000000>; 488 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 489 clock-names = "i2c", "pclk"; 490 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&i2c5_xfer>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 i2c6: i2c@ff150000 { 499 compatible = "rockchip,rk3399-i2c"; 500 reg = <0x0 0xff150000 0x0 0x1000>; 501 assigned-clocks = <&cru SCLK_I2C6>; 502 assigned-clock-rates = <200000000>; 503 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 504 clock-names = "i2c", "pclk"; 505 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&i2c6_xfer>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 status = "disabled"; 511 }; 512 513 i2c7: i2c@ff160000 { 514 compatible = "rockchip,rk3399-i2c"; 515 reg = <0x0 0xff160000 0x0 0x1000>; 516 assigned-clocks = <&cru SCLK_I2C7>; 517 assigned-clock-rates = <200000000>; 518 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 519 clock-names = "i2c", "pclk"; 520 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&i2c7_xfer>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 status = "disabled"; 526 }; 527 528 uart0: serial@ff180000 { 529 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 530 reg = <0x0 0xff180000 0x0 0x100>; 531 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 532 clock-names = "baudclk", "apb_pclk"; 533 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 534 reg-shift = <2>; 535 reg-io-width = <4>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&uart0_xfer>; 538 status = "disabled"; 539 }; 540 541 uart1: serial@ff190000 { 542 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 543 reg = <0x0 0xff190000 0x0 0x100>; 544 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 545 clock-names = "baudclk", "apb_pclk"; 546 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 547 reg-shift = <2>; 548 reg-io-width = <4>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&uart1_xfer>; 551 status = "disabled"; 552 }; 553 554 uart2: serial@ff1a0000 { 555 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 556 reg = <0x0 0xff1a0000 0x0 0x100>; 557 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 558 clock-names = "baudclk", "apb_pclk"; 559 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 560 clock-frequency = <24000000>; 561 reg-shift = <2>; 562 reg-io-width = <4>; 563 pinctrl-names = "default"; 564 pinctrl-0 = <&uart2c_xfer>; 565 status = "disabled"; 566 }; 567 568 uart3: serial@ff1b0000 { 569 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 570 reg = <0x0 0xff1b0000 0x0 0x100>; 571 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 572 clock-names = "baudclk", "apb_pclk"; 573 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 574 reg-shift = <2>; 575 reg-io-width = <4>; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&uart3_xfer>; 578 status = "disabled"; 579 }; 580 581 spi0: spi@ff1c0000 { 582 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 583 reg = <0x0 0xff1c0000 0x0 0x1000>; 584 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 585 clock-names = "spiclk", "apb_pclk"; 586 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 }; 593 594 spi1: spi@ff1d0000 { 595 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 596 reg = <0x0 0xff1d0000 0x0 0x1000>; 597 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 598 clock-names = "spiclk", "apb_pclk"; 599 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 600 pinctrl-names = "default"; 601 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 status = "disabled"; 605 }; 606 607 spi2: spi@ff1e0000 { 608 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 609 reg = <0x0 0xff1e0000 0x0 0x1000>; 610 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 611 clock-names = "spiclk", "apb_pclk"; 612 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 }; 619 620 spi4: spi@ff1f0000 { 621 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 622 reg = <0x0 0xff1f0000 0x0 0x1000>; 623 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 624 clock-names = "spiclk", "apb_pclk"; 625 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 }; 632 633 spi5: spi@ff200000 { 634 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 635 reg = <0x0 0xff200000 0x0 0x1000>; 636 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 637 clock-names = "spiclk", "apb_pclk"; 638 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 status = "disabled"; 644 }; 645 646 thermal_zones: thermal-zones { 647 cpu_thermal: cpu { 648 polling-delay-passive = <100>; 649 polling-delay = <1000>; 650 651 thermal-sensors = <&tsadc 0>; 652 653 trips { 654 cpu_alert0: cpu_alert0 { 655 temperature = <70000>; 656 hysteresis = <2000>; 657 type = "passive"; 658 }; 659 cpu_alert1: cpu_alert1 { 660 temperature = <75000>; 661 hysteresis = <2000>; 662 type = "passive"; 663 }; 664 cpu_crit: cpu_crit { 665 temperature = <95000>; 666 hysteresis = <2000>; 667 type = "critical"; 668 }; 669 }; 670 671 cooling-maps { 672 map0 { 673 trip = <&cpu_alert0>; 674 cooling-device = 675 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 676 }; 677 map1 { 678 trip = <&cpu_alert1>; 679 cooling-device = 680 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 681 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 682 }; 683 }; 684 }; 685 686 gpu_thermal: gpu { 687 polling-delay-passive = <100>; 688 polling-delay = <1000>; 689 690 thermal-sensors = <&tsadc 1>; 691 692 trips { 693 gpu_alert0: gpu_alert0 { 694 temperature = <75000>; 695 hysteresis = <2000>; 696 type = "passive"; 697 }; 698 gpu_crit: gpu_crit { 699 temperature = <95000>; 700 hysteresis = <2000>; 701 type = "critical"; 702 }; 703 }; 704 705 cooling-maps { 706 map0 { 707 trip = <&gpu_alert0>; 708 cooling-device = 709 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 710 }; 711 }; 712 }; 713 }; 714 715 tsadc: tsadc@ff260000 { 716 compatible = "rockchip,rk3399-tsadc"; 717 reg = <0x0 0xff260000 0x0 0x100>; 718 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 719 assigned-clocks = <&cru SCLK_TSADC>; 720 assigned-clock-rates = <750000>; 721 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 722 clock-names = "tsadc", "apb_pclk"; 723 resets = <&cru SRST_TSADC>; 724 reset-names = "tsadc-apb"; 725 rockchip,grf = <&grf>; 726 rockchip,hw-tshut-temp = <95000>; 727 pinctrl-names = "init", "default", "sleep"; 728 pinctrl-0 = <&otp_gpio>; 729 pinctrl-1 = <&otp_out>; 730 pinctrl-2 = <&otp_gpio>; 731 #thermal-sensor-cells = <1>; 732 status = "disabled"; 733 }; 734 735 qos_emmc: qos@ffa58000 { 736 compatible = "syscon"; 737 reg = <0x0 0xffa58000 0x0 0x20>; 738 }; 739 740 qos_gmac: qos@ffa5c000 { 741 compatible = "syscon"; 742 reg = <0x0 0xffa5c000 0x0 0x20>; 743 }; 744 745 qos_pcie: qos@ffa60080 { 746 compatible = "syscon"; 747 reg = <0x0 0xffa60080 0x0 0x20>; 748 }; 749 750 qos_usb_host0: qos@ffa60100 { 751 compatible = "syscon"; 752 reg = <0x0 0xffa60100 0x0 0x20>; 753 }; 754 755 qos_usb_host1: qos@ffa60180 { 756 compatible = "syscon"; 757 reg = <0x0 0xffa60180 0x0 0x20>; 758 }; 759 760 qos_usb_otg0: qos@ffa70000 { 761 compatible = "syscon"; 762 reg = <0x0 0xffa70000 0x0 0x20>; 763 }; 764 765 qos_usb_otg1: qos@ffa70080 { 766 compatible = "syscon"; 767 reg = <0x0 0xffa70080 0x0 0x20>; 768 }; 769 770 qos_sd: qos@ffa74000 { 771 compatible = "syscon"; 772 reg = <0x0 0xffa74000 0x0 0x20>; 773 }; 774 775 qos_sdioaudio: qos@ffa76000 { 776 compatible = "syscon"; 777 reg = <0x0 0xffa76000 0x0 0x20>; 778 }; 779 780 qos_hdcp: qos@ffa90000 { 781 compatible = "syscon"; 782 reg = <0x0 0xffa90000 0x0 0x20>; 783 }; 784 785 qos_iep: qos@ffa98000 { 786 compatible = "syscon"; 787 reg = <0x0 0xffa98000 0x0 0x20>; 788 }; 789 790 qos_isp0_m0: qos@ffaa0000 { 791 compatible = "syscon"; 792 reg = <0x0 0xffaa0000 0x0 0x20>; 793 }; 794 795 qos_isp0_m1: qos@ffaa0080 { 796 compatible = "syscon"; 797 reg = <0x0 0xffaa0080 0x0 0x20>; 798 }; 799 800 qos_isp1_m0: qos@ffaa8000 { 801 compatible = "syscon"; 802 reg = <0x0 0xffaa8000 0x0 0x20>; 803 }; 804 805 qos_isp1_m1: qos@ffaa8080 { 806 compatible = "syscon"; 807 reg = <0x0 0xffaa8080 0x0 0x20>; 808 }; 809 810 qos_rga_r: qos@ffab0000 { 811 compatible = "syscon"; 812 reg = <0x0 0xffab0000 0x0 0x20>; 813 }; 814 815 qos_rga_w: qos@ffab0080 { 816 compatible = "syscon"; 817 reg = <0x0 0xffab0080 0x0 0x20>; 818 }; 819 820 qos_video_m0: qos@ffab8000 { 821 compatible = "syscon"; 822 reg = <0x0 0xffab8000 0x0 0x20>; 823 }; 824 825 qos_video_m1_r: qos@ffac0000 { 826 compatible = "syscon"; 827 reg = <0x0 0xffac0000 0x0 0x20>; 828 }; 829 830 qos_video_m1_w: qos@ffac0080 { 831 compatible = "syscon"; 832 reg = <0x0 0xffac0080 0x0 0x20>; 833 }; 834 835 qos_vop_big_r: qos@ffac8000 { 836 compatible = "syscon"; 837 reg = <0x0 0xffac8000 0x0 0x20>; 838 }; 839 840 qos_vop_big_w: qos@ffac8080 { 841 compatible = "syscon"; 842 reg = <0x0 0xffac8080 0x0 0x20>; 843 }; 844 845 qos_vop_little: qos@ffad0000 { 846 compatible = "syscon"; 847 reg = <0x0 0xffad0000 0x0 0x20>; 848 }; 849 850 qos_perihp: qos@ffad8080 { 851 compatible = "syscon"; 852 reg = <0x0 0xffad8080 0x0 0x20>; 853 }; 854 855 qos_gpu: qos@ffae0000 { 856 compatible = "syscon"; 857 reg = <0x0 0xffae0000 0x0 0x20>; 858 }; 859 860 pmu: power-management@ff310000 { 861 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 862 reg = <0x0 0xff310000 0x0 0x1000>; 863 864 /* 865 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 866 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 867 * Some of the power domains are grouped together for every 868 * voltage domain. 869 * The detail contents as below. 870 */ 871 power: power-controller { 872 compatible = "rockchip,rk3399-power-controller"; 873 #power-domain-cells = <1>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 877 /* These power domains are grouped by VD_CENTER */ 878 pd_iep@RK3399_PD_IEP { 879 reg = <RK3399_PD_IEP>; 880 clocks = <&cru ACLK_IEP>, 881 <&cru HCLK_IEP>; 882 pm_qos = <&qos_iep>; 883 }; 884 pd_rga@RK3399_PD_RGA { 885 reg = <RK3399_PD_RGA>; 886 clocks = <&cru ACLK_RGA>, 887 <&cru HCLK_RGA>; 888 pm_qos = <&qos_rga_r>, 889 <&qos_rga_w>; 890 }; 891 pd_vcodec@RK3399_PD_VCODEC { 892 reg = <RK3399_PD_VCODEC>; 893 clocks = <&cru ACLK_VCODEC>, 894 <&cru HCLK_VCODEC>; 895 pm_qos = <&qos_video_m0>; 896 }; 897 pd_vdu@RK3399_PD_VDU { 898 reg = <RK3399_PD_VDU>; 899 clocks = <&cru ACLK_VDU>, 900 <&cru HCLK_VDU>; 901 pm_qos = <&qos_video_m1_r>, 902 <&qos_video_m1_w>; 903 }; 904 905 /* These power domains are grouped by VD_GPU */ 906 pd_gpu@RK3399_PD_GPU { 907 reg = <RK3399_PD_GPU>; 908 clocks = <&cru ACLK_GPU>; 909 pm_qos = <&qos_gpu>; 910 }; 911 912 /* These power domains are grouped by VD_LOGIC */ 913 pd_edp@RK3399_PD_EDP { 914 reg = <RK3399_PD_EDP>; 915 clocks = <&cru PCLK_EDP_CTRL>; 916 }; 917 pd_emmc@RK3399_PD_EMMC { 918 reg = <RK3399_PD_EMMC>; 919 clocks = <&cru ACLK_EMMC>; 920 pm_qos = <&qos_emmc>; 921 }; 922 pd_gmac@RK3399_PD_GMAC { 923 reg = <RK3399_PD_GMAC>; 924 clocks = <&cru ACLK_GMAC>, 925 <&cru PCLK_GMAC>; 926 pm_qos = <&qos_gmac>; 927 }; 928 pd_perihp@RK3399_PD_PERIHP { 929 reg = <RK3399_PD_PERIHP>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 clocks = <&cru ACLK_PERIHP>; 933 pm_qos = <&qos_perihp>, 934 <&qos_pcie>, 935 <&qos_usb_host0>, 936 <&qos_usb_host1>; 937 938 pd_sd@RK3399_PD_SD { 939 reg = <RK3399_PD_SD>; 940 clocks = <&cru HCLK_SDMMC>, 941 <&cru SCLK_SDMMC>; 942 pm_qos = <&qos_sd>; 943 }; 944 }; 945 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 946 reg = <RK3399_PD_SDIOAUDIO>; 947 clocks = <&cru HCLK_SDIO>; 948 pm_qos = <&qos_sdioaudio>; 949 }; 950 pd_usb3@RK3399_PD_USB3 { 951 reg = <RK3399_PD_USB3>; 952 clocks = <&cru ACLK_USB3>; 953 pm_qos = <&qos_usb_otg0>, 954 <&qos_usb_otg1>; 955 }; 956 pd_vio@RK3399_PD_VIO { 957 reg = <RK3399_PD_VIO>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 961 pd_hdcp@RK3399_PD_HDCP { 962 reg = <RK3399_PD_HDCP>; 963 clocks = <&cru ACLK_HDCP>, 964 <&cru HCLK_HDCP>, 965 <&cru PCLK_HDCP>; 966 pm_qos = <&qos_hdcp>; 967 }; 968 pd_isp0@RK3399_PD_ISP0 { 969 reg = <RK3399_PD_ISP0>; 970 clocks = <&cru ACLK_ISP0>, 971 <&cru HCLK_ISP0>; 972 pm_qos = <&qos_isp0_m0>, 973 <&qos_isp0_m1>; 974 }; 975 pd_isp1@RK3399_PD_ISP1 { 976 reg = <RK3399_PD_ISP1>; 977 clocks = <&cru ACLK_ISP1>, 978 <&cru HCLK_ISP1>; 979 pm_qos = <&qos_isp1_m0>, 980 <&qos_isp1_m1>; 981 }; 982 pd_tcpc0@RK3399_PD_TCPC0 { 983 reg = <RK3399_PD_TCPD0>; 984 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 985 <&cru SCLK_UPHY0_TCPDPHY_REF>; 986 }; 987 pd_tcpc1@RK3399_PD_TCPC1 { 988 reg = <RK3399_PD_TCPD1>; 989 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 990 <&cru SCLK_UPHY1_TCPDPHY_REF>; 991 }; 992 pd_vo@RK3399_PD_VO { 993 reg = <RK3399_PD_VO>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 997 pd_vopb@RK3399_PD_VOPB { 998 reg = <RK3399_PD_VOPB>; 999 clocks = <&cru ACLK_VOP0>, 1000 <&cru HCLK_VOP0>; 1001 pm_qos = <&qos_vop_big_r>, 1002 <&qos_vop_big_w>; 1003 }; 1004 pd_vopl@RK3399_PD_VOPL { 1005 reg = <RK3399_PD_VOPL>; 1006 clocks = <&cru ACLK_VOP1>, 1007 <&cru HCLK_VOP1>; 1008 pm_qos = <&qos_vop_little>; 1009 }; 1010 }; 1011 }; 1012 }; 1013 }; 1014 1015 pmugrf: syscon@ff320000 { 1016 u-boot,dm-pre-reloc; 1017 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1018 reg = <0x0 0xff320000 0x0 0x1000>; 1019 #address-cells = <1>; 1020 #size-cells = <1>; 1021 1022 pmu_io_domains: io-domains { 1023 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1024 status = "disabled"; 1025 }; 1026 }; 1027 1028 pmusgrf: syscon@ff330000 { 1029 u-boot,dm-pre-reloc; 1030 compatible = "rockchip,rk3399-pmusgrf", "syscon"; 1031 reg = <0x0 0xff330000 0x0 0xe3d4>; 1032 }; 1033 1034 spi3: spi@ff350000 { 1035 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1036 reg = <0x0 0xff350000 0x0 0x1000>; 1037 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1038 clock-names = "spiclk", "apb_pclk"; 1039 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 uart4: serial@ff370000 { 1048 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1049 reg = <0x0 0xff370000 0x0 0x100>; 1050 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1051 clock-names = "baudclk", "apb_pclk"; 1052 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1053 reg-shift = <2>; 1054 reg-io-width = <4>; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&uart4_xfer>; 1057 status = "disabled"; 1058 }; 1059 1060 i2c4: i2c@ff3d0000 { 1061 compatible = "rockchip,rk3399-i2c"; 1062 reg = <0x0 0xff3d0000 0x0 0x1000>; 1063 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1064 assigned-clock-rates = <200000000>; 1065 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1066 clock-names = "i2c", "pclk"; 1067 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&i2c4_xfer>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 i2c8: i2c@ff3e0000 { 1076 compatible = "rockchip,rk3399-i2c"; 1077 reg = <0x0 0xff3e0000 0x0 0x1000>; 1078 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1079 assigned-clock-rates = <200000000>; 1080 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1081 clock-names = "i2c", "pclk"; 1082 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&i2c8_xfer>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 pwm0: pwm@ff420000 { 1091 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1092 reg = <0x0 0xff420000 0x0 0x10>; 1093 #pwm-cells = <3>; 1094 pinctrl-names = "default"; 1095 pinctrl-0 = <&pwm0_pin>; 1096 clocks = <&pmucru PCLK_RKPWM_PMU>; 1097 clock-names = "pwm"; 1098 status = "disabled"; 1099 }; 1100 1101 pwm1: pwm@ff420010 { 1102 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1103 reg = <0x0 0xff420010 0x0 0x10>; 1104 #pwm-cells = <3>; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&pwm1_pin>; 1107 clocks = <&pmucru PCLK_RKPWM_PMU>; 1108 clock-names = "pwm"; 1109 status = "disabled"; 1110 }; 1111 1112 pwm2: pwm@ff420020 { 1113 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1114 reg = <0x0 0xff420020 0x0 0x10>; 1115 #pwm-cells = <3>; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&pwm2_pin>; 1118 clocks = <&pmucru PCLK_RKPWM_PMU>; 1119 clock-names = "pwm"; 1120 status = "disabled"; 1121 }; 1122 1123 pwm3: pwm@ff420030 { 1124 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1125 reg = <0x0 0xff420030 0x0 0x10>; 1126 #pwm-cells = <3>; 1127 pinctrl-names = "default"; 1128 pinctrl-0 = <&pwm3a_pin>; 1129 clocks = <&pmucru PCLK_RKPWM_PMU>; 1130 clock-names = "pwm"; 1131 status = "disabled"; 1132 }; 1133 1134 cic: syscon@ff620000 { 1135 u-boot,dm-pre-reloc; 1136 compatible = "rockchip,rk3399-cic", "syscon"; 1137 reg = <0x0 0xff620000 0x0 0x100>; 1138 }; 1139 1140 dfi: dfi@ff630000 { 1141 reg = <0x00 0xff630000 0x00 0x4000>; 1142 compatible = "rockchip,rk3399-dfi"; 1143 rockchip,pmu = <&pmugrf>; 1144 clocks = <&cru PCLK_DDR_MON>; 1145 clock-names = "pclk_ddr_mon"; 1146 status = "disabled"; 1147 }; 1148 1149 dmc: dmc { 1150 u-boot,dm-pre-reloc; 1151 compatible = "rockchip,rk3399-dmc"; 1152 devfreq-events = <&dfi>; 1153 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 1154 clocks = <&cru SCLK_DDRCLK>; 1155 clock-names = "dmc_clk"; 1156 reg = <0x0 0xffa80000 0x0 0x0800 1157 0x0 0xffa80800 0x0 0x1800 1158 0x0 0xffa82000 0x0 0x2000 1159 0x0 0xffa84000 0x0 0x1000 1160 0x0 0xffa88000 0x0 0x0800 1161 0x0 0xffa88800 0x0 0x1800 1162 0x0 0xffa8a000 0x0 0x2000 1163 0x0 0xffa8c000 0x0 0x1000>; 1164 }; 1165 1166 efuse0: efuse@ff690000 { 1167 compatible = "rockchip,rk3399-efuse"; 1168 reg = <0x0 0xff690000 0x0 0x80>; 1169 #address-cells = <1>; 1170 #size-cells = <1>; 1171 clocks = <&cru PCLK_EFUSE1024NS>; 1172 clock-names = "pclk_efuse"; 1173 1174 /* Data cells */ 1175 cpu_id: cpu-id@7 { 1176 reg = <0x07 0x10>; 1177 }; 1178 cpub_leakage: cpu-leakage@17 { 1179 reg = <0x17 0x1>; 1180 }; 1181 gpu_leakage: gpu-leakage@18 { 1182 reg = <0x18 0x1>; 1183 }; 1184 center_leakage: center-leakage@19 { 1185 reg = <0x19 0x1>; 1186 }; 1187 cpul_leakage: cpu-leakage@1a { 1188 reg = <0x1a 0x1>; 1189 }; 1190 logic_leakage: logic-leakage@1b { 1191 reg = <0x1b 0x1>; 1192 }; 1193 wafer_info: wafer-info@1c { 1194 reg = <0x1c 0x1>; 1195 }; 1196 }; 1197 1198 pmucru: pmu-clock-controller@ff750000 { 1199 u-boot,dm-pre-reloc; 1200 compatible = "rockchip,rk3399-pmucru"; 1201 reg = <0x0 0xff750000 0x0 0x1000>; 1202 rockchip,grf = <&pmugrf>; 1203 #clock-cells = <1>; 1204 #reset-cells = <1>; 1205 assigned-clocks = <&pmucru PLL_PPLL>; 1206 assigned-clock-rates = <676000000>; 1207 }; 1208 1209 cru: clock-controller@ff760000 { 1210 u-boot,dm-pre-reloc; 1211 compatible = "rockchip,rk3399-cru"; 1212 reg = <0x0 0xff760000 0x0 0x1000>; 1213 rockchip,grf = <&grf>; 1214 #clock-cells = <1>; 1215 #reset-cells = <1>; 1216 assigned-clocks = 1217 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1218 <&cru PLL_NPLL>, 1219 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1220 <&cru PCLK_PERIHP>, 1221 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1222 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1223 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1224 assigned-clock-rates = 1225 <594000000>, <800000000>, 1226 <1000000000>, 1227 <150000000>, <75000000>, 1228 <37500000>, 1229 <100000000>, <100000000>, 1230 <50000000>, <600000000>, 1231 <100000000>, <50000000>; 1232 }; 1233 1234 grf: syscon@ff770000 { 1235 u-boot,dm-pre-reloc; 1236 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1237 reg = <0x0 0xff770000 0x0 0x10000>; 1238 #address-cells = <1>; 1239 #size-cells = <1>; 1240 1241 io_domains: io-domains { 1242 compatible = "rockchip,rk3399-io-voltage-domain"; 1243 status = "disabled"; 1244 }; 1245 1246 u2phy0: usb2-phy@e450 { 1247 compatible = "rockchip,rk3399-usb2phy"; 1248 reg = <0xe450 0x10>; 1249 clocks = <&cru SCLK_USB2PHY0_REF>; 1250 clock-names = "phyclk"; 1251 #clock-cells = <0>; 1252 clock-output-names = "clk_usbphy0_480m"; 1253 status = "disabled"; 1254 1255 u2phy0_host: host-port { 1256 #phy-cells = <0>; 1257 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1258 interrupt-names = "linestate"; 1259 status = "disabled"; 1260 }; 1261 1262 u2phy0_otg: otg-port { 1263 #phy-cells = <0>; 1264 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1265 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1266 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1267 interrupt-names = "otg-bvalid", "otg-id", 1268 "linestate"; 1269 status = "disabled"; 1270 }; 1271 }; 1272 1273 u2phy1: usb2-phy@e460 { 1274 compatible = "rockchip,rk3399-usb2phy"; 1275 reg = <0xe460 0x10>; 1276 clocks = <&cru SCLK_USB2PHY1_REF>; 1277 clock-names = "phyclk"; 1278 #clock-cells = <0>; 1279 clock-output-names = "clk_usbphy1_480m"; 1280 status = "disabled"; 1281 1282 u2phy1_host: host-port { 1283 #phy-cells = <0>; 1284 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1285 interrupt-names = "linestate"; 1286 status = "disabled"; 1287 }; 1288 1289 u2phy1_otg: otg-port { 1290 #phy-cells = <0>; 1291 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1292 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1293 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1294 interrupt-names = "otg-bvalid", "otg-id", 1295 "linestate"; 1296 status = "disabled"; 1297 }; 1298 }; 1299 1300 emmc_phy: phy@f780 { 1301 compatible = "rockchip,rk3399-emmc-phy"; 1302 reg = <0xf780 0x24>; 1303 clocks = <&sdhci>; 1304 clock-names = "emmcclk"; 1305 #phy-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 pcie_phy: pcie-phy { 1310 compatible = "rockchip,rk3399-pcie-phy"; 1311 clocks = <&cru SCLK_PCIEPHY_REF>; 1312 clock-names = "refclk"; 1313 #phy-cells = <0>; 1314 resets = <&cru SRST_PCIEPHY>; 1315 reset-names = "phy"; 1316 status = "disabled"; 1317 }; 1318 }; 1319 1320 watchdog@ff848000 { 1321 compatible = "snps,dw-wdt"; 1322 reg = <0x0 0xff848000 0x0 0x100>; 1323 clocks = <&cru PCLK_WDT>; 1324 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1325 }; 1326 1327 rktimer: rktimer@ff850000 { 1328 compatible = "rockchip,rk3399-timer"; 1329 reg = <0x0 0xff850000 0x0 0x1000>; 1330 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1331 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1332 clock-names = "pclk", "timer"; 1333 }; 1334 1335 spdif: spdif@ff870000 { 1336 compatible = "rockchip,rk3399-spdif"; 1337 reg = <0x0 0xff870000 0x0 0x1000>; 1338 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1339 dmas = <&dmac_bus 7>; 1340 dma-names = "tx"; 1341 clock-names = "mclk", "hclk"; 1342 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&spdif_bus>; 1345 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1346 status = "disabled"; 1347 }; 1348 1349 i2s0: i2s@ff880000 { 1350 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1351 reg = <0x0 0xff880000 0x0 0x1000>; 1352 rockchip,grf = <&grf>; 1353 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1354 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1355 dma-names = "tx", "rx"; 1356 clock-names = "i2s_clk", "i2s_hclk"; 1357 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&i2s0_8ch_bus>; 1360 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1361 status = "disabled"; 1362 }; 1363 1364 i2s1: i2s@ff890000 { 1365 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1366 reg = <0x0 0xff890000 0x0 0x1000>; 1367 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1368 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1369 dma-names = "tx", "rx"; 1370 clock-names = "i2s_clk", "i2s_hclk"; 1371 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&i2s1_2ch_bus>; 1374 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1375 status = "disabled"; 1376 }; 1377 1378 i2s2: i2s@ff8a0000 { 1379 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1380 reg = <0x0 0xff8a0000 0x0 0x1000>; 1381 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1382 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1383 dma-names = "tx", "rx"; 1384 clock-names = "i2s_clk", "i2s_hclk"; 1385 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1386 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1387 status = "disabled"; 1388 }; 1389 1390 i2c0: i2c@ff3c0000 { 1391 compatible = "rockchip,rk3399-i2c"; 1392 reg = <0x0 0xff3c0000 0x0 0x1000>; 1393 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1394 assigned-clock-rates = <200000000>; 1395 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1396 clock-names = "i2c", "pclk"; 1397 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1398 pinctrl-names = "default"; 1399 pinctrl-0 = <&i2c0_xfer>; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 vopl: vop@ff8f0000 { 1406 u-boot,dm-pre-reloc; 1407 compatible = "rockchip,rk3399-vop-lit"; 1408 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1409 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1410 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1411 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1412 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1413 reset-names = "axi", "ahb", "dclk"; 1414 status = "disabled"; 1415 vopl_out: port { 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 vopl_out_mipi: endpoint@0 { 1419 reg = <3>; 1420 remote-endpoint = <&mipi_in_vopl>; 1421 }; 1422 1423 vopl_out_hdmi: endpoint@1 { 1424 reg = <1>; 1425 remote-endpoint = <&hdmi_in_vopl>; 1426 }; 1427 }; 1428 }; 1429 1430 vopb: vop@ff900000 { 1431 u-boot,dm-pre-reloc; 1432 compatible = "rockchip,rk3399-vop-big"; 1433 reg = <0x0 0xff900000 0x0 0x3efc>; 1434 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1435 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1436 #clock-cells = <0>; 1437 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1438 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1439 reset-names = "axi", "ahb", "dclk"; 1440 status = "disabled"; 1441 vopb_out: port { 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 vopb_out_mipi: endpoint@0 { 1445 reg = <3>; 1446 remote-endpoint = <&mipi_in_vopb>; 1447 }; 1448 1449 vopb_out_hdmi: endpoint@1 { 1450 reg = <1>; 1451 remote-endpoint = <&hdmi_in_vopb>; 1452 }; 1453 }; 1454 }; 1455 1456 hdmi: hdmi@ff940000 { 1457 compatible = "rockchip,rk3399-dw-hdmi"; 1458 reg = <0x0 0xff940000 0x0 0x20000>; 1459 reg-io-width = <4>; 1460 rockchip,grf = <&grf>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&hdmi_i2c_xfer>; 1463 power-domains = <&power RK3399_PD_HDCP>; 1464 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1465 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; 1466 clock-names = "iahb", "isfr", "vpll", "grf"; 1467 status = "disabled"; 1468 1469 ports { 1470 hdmi_in: port { 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 hdmi_in_vopb: endpoint@0 { 1474 reg = <0>; 1475 remote-endpoint = <&vopb_out_hdmi>; 1476 }; 1477 hdmi_in_vopl: endpoint@1 { 1478 reg = <1>; 1479 remote-endpoint = <&vopl_out_hdmi>; 1480 }; 1481 }; 1482 }; 1483 }; 1484 1485 mipi_dsi: mipi@ff960000 { 1486 compatible = "rockchip,rk3399_mipi_dsi"; 1487 reg = <0x0 0xff960000 0x0 0x8000>; 1488 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1489 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, 1490 <&cru SCLK_DPHY_TX0_CFG>; 1491 clock-names = "ref", "pclk", "phy_cfg"; 1492 rockchip,grf = <&grf>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 status = "disabled"; 1496 ports { 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 reg = <1>; 1500 mipi_in: port { 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 mipi_in_vopb: endpoint@0 { 1504 reg = <0>; 1505 remote-endpoint = <&vopb_out_mipi>; 1506 }; 1507 mipi_in_vopl: endpoint@1 { 1508 reg = <1>; 1509 remote-endpoint = <&vopl_out_mipi>; 1510 }; 1511 }; 1512 }; 1513 }; 1514 1515 pinctrl: pinctrl { 1516 u-boot,dm-pre-reloc; 1517 compatible = "rockchip,rk3399-pinctrl"; 1518 rockchip,grf = <&grf>; 1519 rockchip,pmu = <&pmugrf>; 1520 #address-cells = <2>; 1521 #size-cells = <2>; 1522 ranges; 1523 1524 gpio0: gpio0@ff720000 { 1525 compatible = "rockchip,gpio-bank"; 1526 reg = <0x0 0xff720000 0x0 0x100>; 1527 clocks = <&pmucru PCLK_GPIO0_PMU>; 1528 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1529 1530 gpio-controller; 1531 #gpio-cells = <0x2>; 1532 1533 interrupt-controller; 1534 #interrupt-cells = <0x2>; 1535 }; 1536 1537 gpio1: gpio1@ff730000 { 1538 compatible = "rockchip,gpio-bank"; 1539 reg = <0x0 0xff730000 0x0 0x100>; 1540 clocks = <&pmucru PCLK_GPIO1_PMU>; 1541 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1542 1543 gpio-controller; 1544 #gpio-cells = <0x2>; 1545 1546 interrupt-controller; 1547 #interrupt-cells = <0x2>; 1548 }; 1549 1550 gpio2: gpio2@ff780000 { 1551 compatible = "rockchip,gpio-bank"; 1552 reg = <0x0 0xff780000 0x0 0x100>; 1553 clocks = <&cru PCLK_GPIO2>; 1554 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1555 1556 gpio-controller; 1557 #gpio-cells = <0x2>; 1558 1559 interrupt-controller; 1560 #interrupt-cells = <0x2>; 1561 }; 1562 1563 gpio3: gpio3@ff788000 { 1564 compatible = "rockchip,gpio-bank"; 1565 reg = <0x0 0xff788000 0x0 0x100>; 1566 clocks = <&cru PCLK_GPIO3>; 1567 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1568 1569 gpio-controller; 1570 #gpio-cells = <0x2>; 1571 1572 interrupt-controller; 1573 #interrupt-cells = <0x2>; 1574 }; 1575 1576 gpio4: gpio4@ff790000 { 1577 compatible = "rockchip,gpio-bank"; 1578 reg = <0x0 0xff790000 0x0 0x100>; 1579 clocks = <&cru PCLK_GPIO4>; 1580 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1581 1582 gpio-controller; 1583 #gpio-cells = <0x2>; 1584 1585 interrupt-controller; 1586 #interrupt-cells = <0x2>; 1587 }; 1588 1589 pcfg_pull_up: pcfg-pull-up { 1590 bias-pull-up; 1591 }; 1592 1593 pcfg_pull_down: pcfg-pull-down { 1594 bias-pull-down; 1595 }; 1596 1597 pcfg_pull_none: pcfg-pull-none { 1598 bias-disable; 1599 }; 1600 1601 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1602 bias-disable; 1603 drive-strength = <12>; 1604 }; 1605 1606 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1607 bias-pull-up; 1608 drive-strength = <8>; 1609 }; 1610 1611 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1612 bias-pull-down; 1613 drive-strength = <4>; 1614 }; 1615 1616 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1617 bias-pull-up; 1618 drive-strength = <2>; 1619 }; 1620 1621 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1622 bias-pull-down; 1623 drive-strength = <12>; 1624 }; 1625 1626 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1627 bias-disable; 1628 drive-strength = <13>; 1629 }; 1630 1631 clock { 1632 clk_32k: clk-32k { 1633 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; 1634 }; 1635 }; 1636 1637 edp { 1638 edp_hpd: edp-hpd { 1639 rockchip,pins = 1640 <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1641 }; 1642 }; 1643 1644 gmac { 1645 rgmii_pins: rgmii-pins { 1646 rockchip,pins = 1647 /* mac_txclk */ 1648 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1649 /* mac_rxclk */ 1650 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1651 /* mac_mdio */ 1652 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1653 /* mac_txen */ 1654 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1655 /* mac_clk */ 1656 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1657 /* mac_rxdv */ 1658 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1659 /* mac_mdc */ 1660 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1661 /* mac_rxd1 */ 1662 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1663 /* mac_rxd0 */ 1664 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1665 /* mac_txd1 */ 1666 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1667 /* mac_txd0 */ 1668 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1669 /* mac_rxd3 */ 1670 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1671 /* mac_rxd2 */ 1672 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1673 /* mac_txd3 */ 1674 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1675 /* mac_txd2 */ 1676 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1677 }; 1678 1679 rmii_pins: rmii-pins { 1680 rockchip,pins = 1681 /* mac_mdio */ 1682 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1683 /* mac_txen */ 1684 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1685 /* mac_clk */ 1686 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1687 /* mac_rxer */ 1688 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1689 /* mac_rxdv */ 1690 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1691 /* mac_mdc */ 1692 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1693 /* mac_rxd1 */ 1694 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1695 /* mac_rxd0 */ 1696 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1697 /* mac_txd1 */ 1698 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1699 /* mac_txd0 */ 1700 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1701 }; 1702 }; 1703 1704 i2c0 { 1705 i2c0_xfer: i2c0-xfer { 1706 rockchip,pins = 1707 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 1708 <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1709 }; 1710 }; 1711 1712 i2c1 { 1713 i2c1_xfer: i2c1-xfer { 1714 rockchip,pins = 1715 <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1716 <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1717 }; 1718 }; 1719 1720 i2c2 { 1721 i2c2_xfer: i2c2-xfer { 1722 rockchip,pins = 1723 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1724 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1725 }; 1726 }; 1727 1728 i2c3 { 1729 i2c3_xfer: i2c3-xfer { 1730 rockchip,pins = 1731 <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1732 <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1733 }; 1734 }; 1735 1736 i2c4 { 1737 i2c4_xfer: i2c4-xfer { 1738 rockchip,pins = 1739 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1740 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1741 }; 1742 }; 1743 1744 i2c5 { 1745 i2c5_xfer: i2c5-xfer { 1746 rockchip,pins = 1747 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, 1748 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 1749 }; 1750 }; 1751 1752 i2c6 { 1753 i2c6_xfer: i2c6-xfer { 1754 rockchip,pins = 1755 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, 1756 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1757 }; 1758 }; 1759 1760 i2c7 { 1761 i2c7_xfer: i2c7-xfer { 1762 rockchip,pins = 1763 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, 1764 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1765 }; 1766 }; 1767 1768 i2c8 { 1769 i2c8_xfer: i2c8-xfer { 1770 rockchip,pins = 1771 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, 1772 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1773 }; 1774 }; 1775 1776 i2s0 { 1777 i2s0_8ch_bus: i2s0-8ch-bus { 1778 rockchip,pins = 1779 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, 1780 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 1781 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 1782 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, 1783 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, 1784 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, 1785 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, 1786 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, 1787 <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1788 }; 1789 }; 1790 1791 i2s1 { 1792 i2s1_2ch_bus: i2s1-2ch-bus { 1793 rockchip,pins = 1794 <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1795 <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1796 <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1797 <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1798 <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 1799 }; 1800 }; 1801 1802 sdio0 { 1803 sdio0_bus1: sdio0-bus1 { 1804 rockchip,pins = 1805 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1806 }; 1807 1808 sdio0_bus4: sdio0-bus4 { 1809 rockchip,pins = 1810 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 1811 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 1812 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1813 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 1814 }; 1815 1816 sdio0_cmd: sdio0-cmd { 1817 rockchip,pins = 1818 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 1819 }; 1820 1821 sdio0_clk: sdio0-clk { 1822 rockchip,pins = 1823 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 1824 }; 1825 1826 sdio0_cd: sdio0-cd { 1827 rockchip,pins = 1828 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 1829 }; 1830 1831 sdio0_pwr: sdio0-pwr { 1832 rockchip,pins = 1833 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 1834 }; 1835 1836 sdio0_bkpwr: sdio0-bkpwr { 1837 rockchip,pins = 1838 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 1839 }; 1840 1841 sdio0_wp: sdio0-wp { 1842 rockchip,pins = 1843 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 1844 }; 1845 1846 sdio0_int: sdio0-int { 1847 rockchip,pins = 1848 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 1849 }; 1850 }; 1851 1852 sdmmc { 1853 sdmmc_bus1: sdmmc-bus1 { 1854 rockchip,pins = 1855 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1856 }; 1857 1858 sdmmc_bus4: sdmmc-bus4 { 1859 rockchip,pins = 1860 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 1861 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 1862 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1863 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1864 }; 1865 1866 sdmmc_clk: sdmmc-clk { 1867 rockchip,pins = 1868 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1869 }; 1870 1871 sdmmc_cmd: sdmmc-cmd { 1872 rockchip,pins = 1873 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 1874 }; 1875 1876 sdmmc_cd: sdmcc-cd { 1877 rockchip,pins = 1878 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 1879 }; 1880 1881 sdmmc_wp: sdmmc-wp { 1882 rockchip,pins = 1883 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1884 }; 1885 }; 1886 1887 sleep { 1888 ap_pwroff: ap-pwroff { 1889 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 1890 }; 1891 1892 ddrio_pwroff: ddrio-pwroff { 1893 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1894 }; 1895 }; 1896 1897 spdif { 1898 spdif_bus: spdif-bus { 1899 rockchip,pins = 1900 <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1901 }; 1902 1903 spdif_bus_1: spdif-bus-1 { 1904 rockchip,pins = 1905 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 1906 }; 1907 }; 1908 1909 spi0 { 1910 spi0_clk: spi0-clk { 1911 rockchip,pins = 1912 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; 1913 }; 1914 spi0_cs0: spi0-cs0 { 1915 rockchip,pins = 1916 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 1917 }; 1918 spi0_cs1: spi0-cs1 { 1919 rockchip,pins = 1920 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 1921 }; 1922 spi0_tx: spi0-tx { 1923 rockchip,pins = 1924 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; 1925 }; 1926 spi0_rx: spi0-rx { 1927 rockchip,pins = 1928 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; 1929 }; 1930 }; 1931 1932 spi1 { 1933 spi1_clk: spi1-clk { 1934 rockchip,pins = 1935 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; 1936 }; 1937 spi1_cs0: spi1-cs0 { 1938 rockchip,pins = 1939 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; 1940 }; 1941 spi1_rx: spi1-rx { 1942 rockchip,pins = 1943 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 1944 }; 1945 spi1_tx: spi1-tx { 1946 rockchip,pins = 1947 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 1948 }; 1949 }; 1950 1951 spi2 { 1952 spi2_clk: spi2-clk { 1953 rockchip,pins = 1954 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1955 }; 1956 spi2_cs0: spi2-cs0 { 1957 rockchip,pins = 1958 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; 1959 }; 1960 spi2_rx: spi2-rx { 1961 rockchip,pins = 1962 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; 1963 }; 1964 spi2_tx: spi2-tx { 1965 rockchip,pins = 1966 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; 1967 }; 1968 }; 1969 1970 spi3 { 1971 spi3_clk: spi3-clk { 1972 rockchip,pins = 1973 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; 1974 }; 1975 spi3_cs0: spi3-cs0 { 1976 rockchip,pins = 1977 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; 1978 }; 1979 spi3_rx: spi3-rx { 1980 rockchip,pins = 1981 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; 1982 }; 1983 spi3_tx: spi3-tx { 1984 rockchip,pins = 1985 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; 1986 }; 1987 }; 1988 1989 spi4 { 1990 spi4_clk: spi4-clk { 1991 rockchip,pins = 1992 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; 1993 }; 1994 spi4_cs0: spi4-cs0 { 1995 rockchip,pins = 1996 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; 1997 }; 1998 spi4_rx: spi4-rx { 1999 rockchip,pins = 2000 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; 2001 }; 2002 spi4_tx: spi4-tx { 2003 rockchip,pins = 2004 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; 2005 }; 2006 }; 2007 2008 spi5 { 2009 spi5_clk: spi5-clk { 2010 rockchip,pins = 2011 <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; 2012 }; 2013 spi5_cs0: spi5-cs0 { 2014 rockchip,pins = 2015 <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; 2016 }; 2017 spi5_rx: spi5-rx { 2018 rockchip,pins = 2019 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; 2020 }; 2021 spi5_tx: spi5-tx { 2022 rockchip,pins = 2023 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; 2024 }; 2025 }; 2026 2027 tsadc { 2028 otp_gpio: otp-gpio { 2029 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2030 }; 2031 2032 otp_out: otp-out { 2033 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2034 }; 2035 }; 2036 2037 uart0 { 2038 uart0_xfer: uart0-xfer { 2039 rockchip,pins = 2040 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, 2041 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2042 }; 2043 2044 uart0_cts: uart0-cts { 2045 rockchip,pins = 2046 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2047 }; 2048 2049 uart0_rts: uart0-rts { 2050 rockchip,pins = 2051 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2052 }; 2053 }; 2054 2055 uart1 { 2056 uart1_xfer: uart1-xfer { 2057 rockchip,pins = 2058 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 2059 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 2060 }; 2061 }; 2062 2063 uart2a { 2064 uart2a_xfer: uart2a-xfer { 2065 rockchip,pins = 2066 <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, 2067 <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2068 }; 2069 }; 2070 2071 uart2b { 2072 uart2b_xfer: uart2b-xfer { 2073 rockchip,pins = 2074 <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 2075 <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 2076 }; 2077 }; 2078 2079 uart2c { 2080 uart2c_xfer: uart2c-xfer { 2081 rockchip,pins = 2082 <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, 2083 <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 2084 }; 2085 }; 2086 2087 uart3 { 2088 uart3_xfer: uart3-xfer { 2089 rockchip,pins = 2090 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 2091 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 2092 }; 2093 2094 uart3_cts: uart3-cts { 2095 rockchip,pins = 2096 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2097 }; 2098 2099 uart3_rts: uart3-rts { 2100 rockchip,pins = 2101 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 2102 }; 2103 }; 2104 2105 uart4 { 2106 uart4_xfer: uart4-xfer { 2107 rockchip,pins = 2108 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, 2109 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 2110 }; 2111 }; 2112 2113 uarthdcp { 2114 uarthdcp_xfer: uarthdcp-xfer { 2115 rockchip,pins = 2116 <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, 2117 <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 2118 }; 2119 }; 2120 2121 pwm0 { 2122 pwm0_pin: pwm0-pin { 2123 rockchip,pins = 2124 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2125 }; 2126 2127 vop0_pwm_pin: vop0-pwm-pin { 2128 rockchip,pins = 2129 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2130 }; 2131 }; 2132 2133 pwm1 { 2134 pwm1_pin: pwm1-pin { 2135 rockchip,pins = 2136 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2137 }; 2138 2139 vop1_pwm_pin: vop1-pwm-pin { 2140 rockchip,pins = 2141 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2142 }; 2143 }; 2144 2145 pwm2 { 2146 pwm2_pin: pwm2-pin { 2147 rockchip,pins = 2148 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2149 }; 2150 }; 2151 2152 pwm3a { 2153 pwm3a_pin: pwm3a-pin { 2154 rockchip,pins = 2155 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2156 }; 2157 }; 2158 2159 pwm3b { 2160 pwm3b_pin: pwm3b-pin { 2161 rockchip,pins = 2162 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2163 }; 2164 }; 2165 2166 hdmi { 2167 hdmi_i2c_xfer: hdmi-i2c-xfer { 2168 rockchip,pins = 2169 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2170 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2171 }; 2172 2173 hdmi_cec: hdmi-cec { 2174 rockchip,pins = 2175 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2176 }; 2177 }; 2178 2179 pcie { 2180 pcie_clkreqn: pci-clkreqn { 2181 rockchip,pins = 2182 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; 2183 }; 2184 2185 pcie_clkreqnb: pci-clkreqnb { 2186 rockchip,pins = 2187 <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 2188 }; 2189 2190 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2191 rockchip,pins = 2192 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2193 }; 2194 2195 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2196 rockchip,pins = 2197 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2198 }; 2199 }; 2200 2201 }; 2202}; 2203