1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3399-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3399"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu-map { 33 cluster0 { 34 core0 { 35 cpu = <&cpu_l0>; 36 }; 37 core1 { 38 cpu = <&cpu_l1>; 39 }; 40 core2 { 41 cpu = <&cpu_l2>; 42 }; 43 core3 { 44 cpu = <&cpu_l3>; 45 }; 46 }; 47 48 cluster1 { 49 core0 { 50 cpu = <&cpu_b0>; 51 }; 52 core1 { 53 cpu = <&cpu_b1>; 54 }; 55 }; 56 }; 57 58 cpu_l0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53", "arm,armv8"; 61 reg = <0x0 0x0>; 62 enable-method = "psci"; 63 #cooling-cells = <2>; /* min followed by max */ 64 clocks = <&cru ARMCLKL>; 65 }; 66 67 cpu_l1: cpu@1 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53", "arm,armv8"; 70 reg = <0x0 0x1>; 71 enable-method = "psci"; 72 clocks = <&cru ARMCLKL>; 73 }; 74 75 cpu_l2: cpu@2 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53", "arm,armv8"; 78 reg = <0x0 0x2>; 79 enable-method = "psci"; 80 clocks = <&cru ARMCLKL>; 81 }; 82 83 cpu_l3: cpu@3 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53", "arm,armv8"; 86 reg = <0x0 0x3>; 87 enable-method = "psci"; 88 clocks = <&cru ARMCLKL>; 89 }; 90 91 cpu_b0: cpu@100 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a72", "arm,armv8"; 94 reg = <0x0 0x100>; 95 enable-method = "psci"; 96 #cooling-cells = <2>; /* min followed by max */ 97 clocks = <&cru ARMCLKB>; 98 }; 99 100 cpu_b1: cpu@101 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a72", "arm,armv8"; 103 reg = <0x0 0x101>; 104 enable-method = "psci"; 105 clocks = <&cru ARMCLKB>; 106 }; 107 }; 108 109 psci { 110 compatible = "arm,psci-1.0"; 111 method = "smc"; 112 }; 113 114 timer { 115 compatible = "arm,armv8-timer"; 116 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 117 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 118 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 119 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 120 }; 121 122 xin24m: xin24m { 123 compatible = "fixed-clock"; 124 clock-frequency = <24000000>; 125 clock-output-names = "xin24m"; 126 #clock-cells = <0>; 127 }; 128 129 amba { 130 compatible = "simple-bus"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 135 dmac_bus: dma-controller@ff6d0000 { 136 compatible = "arm,pl330", "arm,primecell"; 137 reg = <0x0 0xff6d0000 0x0 0x4000>; 138 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 140 #dma-cells = <1>; 141 clocks = <&cru ACLK_DMAC0_PERILP>; 142 clock-names = "apb_pclk"; 143 }; 144 145 dmac_peri: dma-controller@ff6e0000 { 146 compatible = "arm,pl330", "arm,primecell"; 147 reg = <0x0 0xff6e0000 0x0 0x4000>; 148 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 150 #dma-cells = <1>; 151 clocks = <&cru ACLK_DMAC1_PERILP>; 152 clock-names = "apb_pclk"; 153 }; 154 }; 155 156 sdio0: dwmmc@fe310000 { 157 compatible = "rockchip,rk3399-dw-mshc", 158 "rockchip,rk3288-dw-mshc"; 159 reg = <0x0 0xfe310000 0x0 0x4000>; 160 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 161 clock-freq-min-max = <400000 150000000>; 162 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 163 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 164 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 165 fifo-depth = <0x100>; 166 status = "disabled"; 167 }; 168 169 sdmmc: dwmmc@fe320000 { 170 compatible = "rockchip,rk3399-dw-mshc", 171 "rockchip,rk3288-dw-mshc"; 172 reg = <0x0 0xfe320000 0x0 0x4000>; 173 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 174 clock-freq-min-max = <400000 150000000>; 175 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, 176 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 177 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; 178 fifo-depth = <0x100>; 179 status = "disabled"; 180 }; 181 182 sdhci: sdhci@fe330000 { 183 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 184 reg = <0x0 0xfe330000 0x0 0x10000>; 185 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 186 assigned-clocks = <&cru SCLK_EMMC>; 187 assigned-clock-rates = <200000000>; 188 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 189 clock-names = "clk_xin", "clk_ahb"; 190 phys = <&emmc_phy>; 191 phy-names = "phy_arasan"; 192 status = "disabled"; 193 }; 194 195 usb_host0_ehci: usb@fe380000 { 196 compatible = "generic-ehci"; 197 reg = <0x0 0xfe380000 0x0 0x20000>; 198 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 200 clock-names = "hclk_host0", "hclk_host0_arb"; 201 status = "disabled"; 202 }; 203 204 usb_host0_ohci: usb@fe3a0000 { 205 compatible = "generic-ohci"; 206 reg = <0x0 0xfe3a0000 0x0 0x20000>; 207 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; 209 clock-names = "hclk_host0", "hclk_host0_arb"; 210 status = "disabled"; 211 }; 212 213 usb_host1_ehci: usb@fe3c0000 { 214 compatible = "generic-ehci"; 215 reg = <0x0 0xfe3c0000 0x0 0x20000>; 216 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 218 clock-names = "hclk_host1", "hclk_host1_arb"; 219 status = "disabled"; 220 }; 221 222 usb_host1_ohci: usb@fe3e0000 { 223 compatible = "generic-ohci"; 224 reg = <0x0 0xfe3e0000 0x0 0x20000>; 225 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; 227 clock-names = "hclk_host1", "hclk_host1_arb"; 228 status = "disabled"; 229 }; 230 231 gic: interrupt-controller@fee00000 { 232 compatible = "arm,gic-v3"; 233 #interrupt-cells = <3>; 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 interrupt-controller; 238 239 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 240 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 241 <0x0 0xfff00000 0 0x10000>, /* GICC */ 242 <0x0 0xfff10000 0 0x10000>, /* GICH */ 243 <0x0 0xfff20000 0 0x10000>; /* GICV */ 244 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 245 its: interrupt-controller@fee20000 { 246 compatible = "arm,gic-v3-its"; 247 msi-controller; 248 reg = <0x0 0xfee20000 0x0 0x20000>; 249 }; 250 }; 251 252 uart0: serial@ff180000 { 253 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 254 reg = <0x0 0xff180000 0x0 0x100>; 255 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 256 clock-names = "baudclk", "apb_pclk"; 257 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 258 reg-shift = <2>; 259 reg-io-width = <4>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&uart0_xfer>; 262 status = "disabled"; 263 }; 264 265 uart1: serial@ff190000 { 266 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 267 reg = <0x0 0xff190000 0x0 0x100>; 268 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 269 clock-names = "baudclk", "apb_pclk"; 270 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 271 reg-shift = <2>; 272 reg-io-width = <4>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&uart1_xfer>; 275 status = "disabled"; 276 }; 277 278 uart2: serial@ff1a0000 { 279 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 280 reg = <0x0 0xff1a0000 0x0 0x100>; 281 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 282 clock-names = "baudclk", "apb_pclk"; 283 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 284 clock-frequency = <24000000>; 285 reg-shift = <2>; 286 reg-io-width = <4>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&uart2c_xfer>; 289 status = "disabled"; 290 }; 291 292 uart3: serial@ff1b0000 { 293 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 294 reg = <0x0 0xff1b0000 0x0 0x100>; 295 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 296 clock-names = "baudclk", "apb_pclk"; 297 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 298 reg-shift = <2>; 299 reg-io-width = <4>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&uart3_xfer>; 302 status = "disabled"; 303 }; 304 305 spi0: spi@ff1c0000 { 306 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 307 reg = <0x0 0xff1c0000 0x0 0x1000>; 308 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 309 clock-names = "spiclk", "apb_pclk"; 310 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 }; 317 318 spi1: spi@ff1d0000 { 319 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 320 reg = <0x0 0xff1d0000 0x0 0x1000>; 321 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 322 clock-names = "spiclk", "apb_pclk"; 323 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 spi2: spi@ff1e0000 { 332 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 333 reg = <0x0 0xff1e0000 0x0 0x1000>; 334 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 335 clock-names = "spiclk", "apb_pclk"; 336 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 spi4: spi@ff1f0000 { 345 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 346 reg = <0x0 0xff1f0000 0x0 0x1000>; 347 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 348 clock-names = "spiclk", "apb_pclk"; 349 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 status = "disabled"; 355 }; 356 357 spi5: spi@ff200000 { 358 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 359 reg = <0x0 0xff200000 0x0 0x1000>; 360 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 361 clock-names = "spiclk", "apb_pclk"; 362 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 status = "disabled"; 368 }; 369 370 pmugrf: syscon@ff320000 { 371 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 372 reg = <0x0 0xff320000 0x0 0x1000>; 373 #address-cells = <1>; 374 #size-cells = <1>; 375 376 pmu_io_domains: io-domains { 377 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 378 status = "disabled"; 379 }; 380 }; 381 382 spi3: spi@ff350000 { 383 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 384 reg = <0x0 0xff350000 0x0 0x1000>; 385 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 386 clock-names = "spiclk", "apb_pclk"; 387 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 status = "disabled"; 393 }; 394 395 uart4: serial@ff370000 { 396 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 397 reg = <0x0 0xff370000 0x0 0x100>; 398 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 399 clock-names = "baudclk", "apb_pclk"; 400 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 401 reg-shift = <2>; 402 reg-io-width = <4>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&uart4_xfer>; 405 status = "disabled"; 406 }; 407 408 pwm0: pwm@ff420000 { 409 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 410 reg = <0x0 0xff420000 0x0 0x10>; 411 #pwm-cells = <3>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pwm0_pin>; 414 clocks = <&pmucru PCLK_RKPWM_PMU>; 415 clock-names = "pwm"; 416 status = "disabled"; 417 }; 418 419 pwm1: pwm@ff420010 { 420 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 421 reg = <0x0 0xff420010 0x0 0x10>; 422 #pwm-cells = <3>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pwm1_pin>; 425 clocks = <&pmucru PCLK_RKPWM_PMU>; 426 clock-names = "pwm"; 427 status = "disabled"; 428 }; 429 430 pwm2: pwm@ff420020 { 431 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 432 reg = <0x0 0xff420020 0x0 0x10>; 433 #pwm-cells = <3>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pwm2_pin>; 436 clocks = <&pmucru PCLK_RKPWM_PMU>; 437 clock-names = "pwm"; 438 status = "disabled"; 439 }; 440 441 pwm3: pwm@ff420030 { 442 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 443 reg = <0x0 0xff420030 0x0 0x10>; 444 #pwm-cells = <3>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pwm3a_pin>; 447 clocks = <&pmucru PCLK_RKPWM_PMU>; 448 clock-names = "pwm"; 449 status = "disabled"; 450 }; 451 452 pmucru: pmu-clock-controller@ff750000 { 453 compatible = "rockchip,rk3399-pmucru"; 454 reg = <0x0 0xff750000 0x0 0x1000>; 455 #clock-cells = <1>; 456 #reset-cells = <1>; 457 assigned-clocks = <&pmucru PLL_PPLL>; 458 assigned-clock-rates = <676000000>; 459 }; 460 461 cru: clock-controller@ff760000 { 462 compatible = "rockchip,rk3399-cru"; 463 reg = <0x0 0xff760000 0x0 0x1000>; 464 #clock-cells = <1>; 465 #reset-cells = <1>; 466 assigned-clocks = 467 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 468 <&cru PLL_NPLL>, 469 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 470 <&cru PCLK_PERIHP>, 471 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 472 <&cru PCLK_PERILP0>, 473 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 474 assigned-clock-rates = 475 <594000000>, <800000000>, 476 <1000000000>, 477 <150000000>, <75000000>, 478 <37500000>, 479 <100000000>, <100000000>, 480 <50000000>, 481 <100000000>, <50000000>; 482 }; 483 484 grf: syscon@ff770000 { 485 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 486 reg = <0x0 0xff770000 0x0 0x10000>; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 490 io_domains: io-domains { 491 compatible = "rockchip,rk3399-io-voltage-domain"; 492 status = "disabled"; 493 }; 494 495 emmc_phy: phy@f780 { 496 compatible = "rockchip,rk3399-emmc-phy"; 497 reg = <0xf780 0x24>; 498 #phy-cells = <0>; 499 status = "disabled"; 500 }; 501 }; 502 503 watchdog@ff840000 { 504 compatible = "snps,dw-wdt"; 505 reg = <0x0 0xff840000 0x0 0x100>; 506 clocks = <&cru PCLK_WDT>; 507 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 508 }; 509 510 spdif: spdif@ff870000 { 511 compatible = "rockchip,rk3399-spdif"; 512 reg = <0x0 0xff870000 0x0 0x1000>; 513 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 514 dmas = <&dmac_bus 7>; 515 dma-names = "tx"; 516 clock-names = "mclk", "hclk"; 517 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&spdif_bus>; 520 status = "disabled"; 521 }; 522 523 i2s0: i2s@ff880000 { 524 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 525 reg = <0x0 0xff880000 0x0 0x1000>; 526 rockchip,grf = <&grf>; 527 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 528 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 529 dma-names = "tx", "rx"; 530 clock-names = "i2s_clk", "i2s_hclk"; 531 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&i2s0_8ch_bus>; 534 status = "disabled"; 535 }; 536 537 i2s1: i2s@ff890000 { 538 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 539 reg = <0x0 0xff890000 0x0 0x1000>; 540 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 541 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 542 dma-names = "tx", "rx"; 543 clock-names = "i2s_clk", "i2s_hclk"; 544 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&i2s1_2ch_bus>; 547 status = "disabled"; 548 }; 549 550 i2s2: i2s@ff8a0000 { 551 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 552 reg = <0x0 0xff8a0000 0x0 0x1000>; 553 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 554 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 555 dma-names = "tx", "rx"; 556 clock-names = "i2s_clk", "i2s_hclk"; 557 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 558 status = "disabled"; 559 }; 560 561 pinctrl: pinctrl { 562 compatible = "rockchip,rk3399-pinctrl"; 563 rockchip,grf = <&grf>; 564 rockchip,pmu = <&pmugrf>; 565 #address-cells = <2>; 566 #size-cells = <2>; 567 ranges; 568 569 gpio0: gpio0@ff720000 { 570 compatible = "rockchip,gpio-bank"; 571 reg = <0x0 0xff720000 0x0 0x100>; 572 clocks = <&pmucru PCLK_GPIO0_PMU>; 573 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 574 575 gpio-controller; 576 #gpio-cells = <0x2>; 577 578 interrupt-controller; 579 #interrupt-cells = <0x2>; 580 }; 581 582 gpio1: gpio1@ff730000 { 583 compatible = "rockchip,gpio-bank"; 584 reg = <0x0 0xff730000 0x0 0x100>; 585 clocks = <&pmucru PCLK_GPIO1_PMU>; 586 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 587 588 gpio-controller; 589 #gpio-cells = <0x2>; 590 591 interrupt-controller; 592 #interrupt-cells = <0x2>; 593 }; 594 595 gpio2: gpio2@ff780000 { 596 compatible = "rockchip,gpio-bank"; 597 reg = <0x0 0xff780000 0x0 0x100>; 598 clocks = <&cru PCLK_GPIO2>; 599 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 600 601 gpio-controller; 602 #gpio-cells = <0x2>; 603 604 interrupt-controller; 605 #interrupt-cells = <0x2>; 606 }; 607 608 gpio3: gpio3@ff788000 { 609 compatible = "rockchip,gpio-bank"; 610 reg = <0x0 0xff788000 0x0 0x100>; 611 clocks = <&cru PCLK_GPIO3>; 612 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 613 614 gpio-controller; 615 #gpio-cells = <0x2>; 616 617 interrupt-controller; 618 #interrupt-cells = <0x2>; 619 }; 620 621 gpio4: gpio4@ff790000 { 622 compatible = "rockchip,gpio-bank"; 623 reg = <0x0 0xff790000 0x0 0x100>; 624 clocks = <&cru PCLK_GPIO4>; 625 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 626 627 gpio-controller; 628 #gpio-cells = <0x2>; 629 630 interrupt-controller; 631 #interrupt-cells = <0x2>; 632 }; 633 634 pcfg_pull_up: pcfg-pull-up { 635 bias-pull-up; 636 }; 637 638 pcfg_pull_down: pcfg-pull-down { 639 bias-pull-down; 640 }; 641 642 pcfg_pull_none: pcfg-pull-none { 643 bias-disable; 644 }; 645 646 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 647 bias-disable; 648 drive-strength = <12>; 649 }; 650 651 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 652 bias-pull-up; 653 drive-strength = <8>; 654 }; 655 656 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 657 bias-pull-down; 658 drive-strength = <4>; 659 }; 660 661 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 662 bias-pull-up; 663 drive-strength = <2>; 664 }; 665 666 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 667 bias-pull-down; 668 drive-strength = <12>; 669 }; 670 671 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 672 bias-disable; 673 drive-strength = <13>; 674 }; 675 676 i2c0 { 677 i2c0_xfer: i2c0-xfer { 678 rockchip,pins = 679 <1 15 RK_FUNC_2 &pcfg_pull_none>, 680 <1 16 RK_FUNC_2 &pcfg_pull_none>; 681 }; 682 }; 683 684 i2c1 { 685 i2c1_xfer: i2c1-xfer { 686 rockchip,pins = 687 <4 2 RK_FUNC_1 &pcfg_pull_none>, 688 <4 1 RK_FUNC_1 &pcfg_pull_none>; 689 }; 690 }; 691 692 i2c2 { 693 i2c2_xfer: i2c2-xfer { 694 rockchip,pins = 695 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 696 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; 697 }; 698 }; 699 700 i2c3 { 701 i2c3_xfer: i2c3-xfer { 702 rockchip,pins = 703 <4 17 RK_FUNC_1 &pcfg_pull_none>, 704 <4 16 RK_FUNC_1 &pcfg_pull_none>; 705 }; 706 }; 707 708 i2c4 { 709 i2c4_xfer: i2c4-xfer { 710 rockchip,pins = 711 <1 12 RK_FUNC_1 &pcfg_pull_none>, 712 <1 11 RK_FUNC_1 &pcfg_pull_none>; 713 }; 714 }; 715 716 i2c5 { 717 i2c5_xfer: i2c5-xfer { 718 rockchip,pins = 719 <3 11 RK_FUNC_2 &pcfg_pull_none>, 720 <3 10 RK_FUNC_2 &pcfg_pull_none>; 721 }; 722 }; 723 724 i2c6 { 725 i2c6_xfer: i2c6-xfer { 726 rockchip,pins = 727 <2 10 RK_FUNC_2 &pcfg_pull_none>, 728 <2 9 RK_FUNC_2 &pcfg_pull_none>; 729 }; 730 }; 731 732 i2c7 { 733 i2c7_xfer: i2c7-xfer { 734 rockchip,pins = 735 <2 8 RK_FUNC_2 &pcfg_pull_none>, 736 <2 7 RK_FUNC_2 &pcfg_pull_none>; 737 }; 738 }; 739 740 i2c8 { 741 i2c8_xfer: i2c8-xfer { 742 rockchip,pins = 743 <1 21 RK_FUNC_1 &pcfg_pull_none>, 744 <1 20 RK_FUNC_1 &pcfg_pull_none>; 745 }; 746 }; 747 748 i2s0 { 749 i2s0_8ch_bus: i2s0-8ch-bus { 750 rockchip,pins = 751 <3 24 RK_FUNC_1 &pcfg_pull_none>, 752 <3 25 RK_FUNC_1 &pcfg_pull_none>, 753 <3 26 RK_FUNC_1 &pcfg_pull_none>, 754 <3 27 RK_FUNC_1 &pcfg_pull_none>, 755 <3 28 RK_FUNC_1 &pcfg_pull_none>, 756 <3 29 RK_FUNC_1 &pcfg_pull_none>, 757 <3 30 RK_FUNC_1 &pcfg_pull_none>, 758 <3 31 RK_FUNC_1 &pcfg_pull_none>, 759 <4 0 RK_FUNC_1 &pcfg_pull_none>; 760 }; 761 }; 762 763 i2s1 { 764 i2s1_2ch_bus: i2s1-2ch-bus { 765 rockchip,pins = 766 <4 3 RK_FUNC_1 &pcfg_pull_none>, 767 <4 4 RK_FUNC_1 &pcfg_pull_none>, 768 <4 5 RK_FUNC_1 &pcfg_pull_none>, 769 <4 6 RK_FUNC_1 &pcfg_pull_none>, 770 <4 7 RK_FUNC_1 &pcfg_pull_none>; 771 }; 772 }; 773 774 spdif { 775 spdif_bus: spdif-bus { 776 rockchip,pins = 777 <4 21 RK_FUNC_1 &pcfg_pull_none>; 778 }; 779 }; 780 781 spi0 { 782 spi0_clk: spi0-clk { 783 rockchip,pins = 784 <3 6 RK_FUNC_2 &pcfg_pull_up>; 785 }; 786 spi0_cs0: spi0-cs0 { 787 rockchip,pins = 788 <3 7 RK_FUNC_2 &pcfg_pull_up>; 789 }; 790 spi0_cs1: spi0-cs1 { 791 rockchip,pins = 792 <3 8 RK_FUNC_2 &pcfg_pull_up>; 793 }; 794 spi0_tx: spi0-tx { 795 rockchip,pins = 796 <3 5 RK_FUNC_2 &pcfg_pull_up>; 797 }; 798 spi0_rx: spi0-rx { 799 rockchip,pins = 800 <3 4 RK_FUNC_2 &pcfg_pull_up>; 801 }; 802 }; 803 804 spi1 { 805 spi1_clk: spi1-clk { 806 rockchip,pins = 807 <1 9 RK_FUNC_2 &pcfg_pull_up>; 808 }; 809 spi1_cs0: spi1-cs0 { 810 rockchip,pins = 811 <1 10 RK_FUNC_2 &pcfg_pull_up>; 812 }; 813 spi1_rx: spi1-rx { 814 rockchip,pins = 815 <1 7 RK_FUNC_2 &pcfg_pull_up>; 816 }; 817 spi1_tx: spi1-tx { 818 rockchip,pins = 819 <1 8 RK_FUNC_2 &pcfg_pull_up>; 820 }; 821 }; 822 823 spi2 { 824 spi2_clk: spi2-clk { 825 rockchip,pins = 826 <2 11 RK_FUNC_1 &pcfg_pull_up>; 827 }; 828 spi2_cs0: spi2-cs0 { 829 rockchip,pins = 830 <2 12 RK_FUNC_1 &pcfg_pull_up>; 831 }; 832 spi2_rx: spi2-rx { 833 rockchip,pins = 834 <2 9 RK_FUNC_1 &pcfg_pull_up>; 835 }; 836 spi2_tx: spi2-tx { 837 rockchip,pins = 838 <2 10 RK_FUNC_1 &pcfg_pull_up>; 839 }; 840 }; 841 842 spi3 { 843 spi3_clk: spi3-clk { 844 rockchip,pins = 845 <1 17 RK_FUNC_1 &pcfg_pull_up>; 846 }; 847 spi3_cs0: spi3-cs0 { 848 rockchip,pins = 849 <1 18 RK_FUNC_1 &pcfg_pull_up>; 850 }; 851 spi3_rx: spi3-rx { 852 rockchip,pins = 853 <1 15 RK_FUNC_1 &pcfg_pull_up>; 854 }; 855 spi3_tx: spi3-tx { 856 rockchip,pins = 857 <1 16 RK_FUNC_1 &pcfg_pull_up>; 858 }; 859 }; 860 861 spi4 { 862 spi4_clk: spi4-clk { 863 rockchip,pins = 864 <3 2 RK_FUNC_2 &pcfg_pull_up>; 865 }; 866 spi4_cs0: spi4-cs0 { 867 rockchip,pins = 868 <3 3 RK_FUNC_2 &pcfg_pull_up>; 869 }; 870 spi4_rx: spi4-rx { 871 rockchip,pins = 872 <3 0 RK_FUNC_2 &pcfg_pull_up>; 873 }; 874 spi4_tx: spi4-tx { 875 rockchip,pins = 876 <3 1 RK_FUNC_2 &pcfg_pull_up>; 877 }; 878 }; 879 880 spi5 { 881 spi5_clk: spi5-clk { 882 rockchip,pins = 883 <2 22 RK_FUNC_2 &pcfg_pull_up>; 884 }; 885 spi5_cs0: spi5-cs0 { 886 rockchip,pins = 887 <2 23 RK_FUNC_2 &pcfg_pull_up>; 888 }; 889 spi5_rx: spi5-rx { 890 rockchip,pins = 891 <2 20 RK_FUNC_2 &pcfg_pull_up>; 892 }; 893 spi5_tx: spi5-tx { 894 rockchip,pins = 895 <2 21 RK_FUNC_2 &pcfg_pull_up>; 896 }; 897 }; 898 899 uart0 { 900 uart0_xfer: uart0-xfer { 901 rockchip,pins = 902 <2 16 RK_FUNC_1 &pcfg_pull_up>, 903 <2 17 RK_FUNC_1 &pcfg_pull_none>; 904 }; 905 906 uart0_cts: uart0-cts { 907 rockchip,pins = 908 <2 18 RK_FUNC_1 &pcfg_pull_none>; 909 }; 910 911 uart0_rts: uart0-rts { 912 rockchip,pins = 913 <2 19 RK_FUNC_1 &pcfg_pull_none>; 914 }; 915 }; 916 917 uart1 { 918 uart1_xfer: uart1-xfer { 919 rockchip,pins = 920 <3 12 RK_FUNC_2 &pcfg_pull_up>, 921 <3 13 RK_FUNC_2 &pcfg_pull_none>; 922 }; 923 }; 924 925 uart2a { 926 uart2a_xfer: uart2a-xfer { 927 rockchip,pins = 928 <4 8 RK_FUNC_2 &pcfg_pull_up>, 929 <4 9 RK_FUNC_2 &pcfg_pull_none>; 930 }; 931 }; 932 933 uart2b { 934 uart2b_xfer: uart2b-xfer { 935 rockchip,pins = 936 <4 16 RK_FUNC_2 &pcfg_pull_up>, 937 <4 17 RK_FUNC_2 &pcfg_pull_none>; 938 }; 939 }; 940 941 uart2c { 942 uart2c_xfer: uart2c-xfer { 943 rockchip,pins = 944 <4 19 RK_FUNC_1 &pcfg_pull_up>, 945 <4 20 RK_FUNC_1 &pcfg_pull_none>; 946 }; 947 }; 948 949 uart3 { 950 uart3_xfer: uart3-xfer { 951 rockchip,pins = 952 <3 14 RK_FUNC_2 &pcfg_pull_up>, 953 <3 15 RK_FUNC_2 &pcfg_pull_none>; 954 }; 955 956 uart3_cts: uart3-cts { 957 rockchip,pins = 958 <3 18 RK_FUNC_2 &pcfg_pull_none>; 959 }; 960 961 uart3_rts: uart3-rts { 962 rockchip,pins = 963 <3 19 RK_FUNC_2 &pcfg_pull_none>; 964 }; 965 }; 966 967 uart4 { 968 uart4_xfer: uart4-xfer { 969 rockchip,pins = 970 <1 7 RK_FUNC_1 &pcfg_pull_up>, 971 <1 8 RK_FUNC_1 &pcfg_pull_none>; 972 }; 973 }; 974 975 uarthdcp { 976 uarthdcp_xfer: uarthdcp-xfer { 977 rockchip,pins = 978 <4 21 RK_FUNC_2 &pcfg_pull_up>, 979 <4 22 RK_FUNC_2 &pcfg_pull_none>; 980 }; 981 }; 982 983 pwm0 { 984 pwm0_pin: pwm0-pin { 985 rockchip,pins = 986 <4 18 RK_FUNC_1 &pcfg_pull_none>; 987 }; 988 989 vop0_pwm_pin: vop0-pwm-pin { 990 rockchip,pins = 991 <4 18 RK_FUNC_2 &pcfg_pull_none>; 992 }; 993 }; 994 995 pwm1 { 996 pwm1_pin: pwm1-pin { 997 rockchip,pins = 998 <4 22 RK_FUNC_1 &pcfg_pull_none>; 999 }; 1000 1001 vop1_pwm_pin: vop1-pwm-pin { 1002 rockchip,pins = 1003 <4 18 RK_FUNC_3 &pcfg_pull_none>; 1004 }; 1005 }; 1006 1007 pwm2 { 1008 pwm2_pin: pwm2-pin { 1009 rockchip,pins = 1010 <1 19 RK_FUNC_1 &pcfg_pull_none>; 1011 }; 1012 }; 1013 1014 pwm3a { 1015 pwm3a_pin: pwm3a-pin { 1016 rockchip,pins = 1017 <0 6 RK_FUNC_1 &pcfg_pull_none>; 1018 }; 1019 }; 1020 1021 pwm3b { 1022 pwm3b_pin: pwm3b-pin { 1023 rockchip,pins = 1024 <1 14 RK_FUNC_1 &pcfg_pull_none>; 1025 }; 1026 }; 1027 }; 1028}; 1029