1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13#define USB_CLASS_HUB 9 14 15/ { 16 compatible = "rockchip,rk3399"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 mmc0 = &sdhci; 38 mmc1 = &sdmmc; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu-map { 46 cluster0 { 47 core0 { 48 cpu = <&cpu_l0>; 49 }; 50 core1 { 51 cpu = <&cpu_l1>; 52 }; 53 core2 { 54 cpu = <&cpu_l2>; 55 }; 56 core3 { 57 cpu = <&cpu_l3>; 58 }; 59 }; 60 61 cluster1 { 62 core0 { 63 cpu = <&cpu_b0>; 64 }; 65 core1 { 66 cpu = <&cpu_b1>; 67 }; 68 }; 69 }; 70 71 cpu_l0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 reg = <0x0 0x0>; 75 enable-method = "psci"; 76 #cooling-cells = <2>; /* min followed by max */ 77 clocks = <&cru ARMCLKL>; 78 }; 79 80 cpu_l1: cpu@1 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53", "arm,armv8"; 83 reg = <0x0 0x1>; 84 enable-method = "psci"; 85 clocks = <&cru ARMCLKL>; 86 }; 87 88 cpu_l2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53", "arm,armv8"; 91 reg = <0x0 0x2>; 92 enable-method = "psci"; 93 clocks = <&cru ARMCLKL>; 94 }; 95 96 cpu_l3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53", "arm,armv8"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 clocks = <&cru ARMCLKL>; 102 }; 103 104 cpu_b0: cpu@100 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a72", "arm,armv8"; 107 reg = <0x0 0x100>; 108 enable-method = "psci"; 109 #cooling-cells = <2>; /* min followed by max */ 110 clocks = <&cru ARMCLKB>; 111 }; 112 113 cpu_b1: cpu@101 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a72", "arm,armv8"; 116 reg = <0x0 0x101>; 117 enable-method = "psci"; 118 clocks = <&cru ARMCLKB>; 119 }; 120 }; 121 122 pmu_a53 { 123 compatible = "arm,cortex-a53-pmu"; 124 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 125 }; 126 127 pmu_a72 { 128 compatible = "arm,cortex-a72-pmu"; 129 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 130 }; 131 132 psci { 133 compatible = "arm,psci-1.0"; 134 method = "smc"; 135 }; 136 137 timer { 138 compatible = "arm,armv8-timer"; 139 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 140 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 141 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 142 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 143 arm,no-tick-in-suspend; 144 }; 145 146 xin24m: xin24m { 147 compatible = "fixed-clock"; 148 clock-frequency = <24000000>; 149 clock-output-names = "xin24m"; 150 #clock-cells = <0>; 151 }; 152 153 amba { 154 compatible = "simple-bus"; 155 #address-cells = <2>; 156 #size-cells = <2>; 157 ranges; 158 159 dmac_bus: dma-controller@ff6d0000 { 160 compatible = "arm,pl330", "arm,primecell"; 161 reg = <0x0 0xff6d0000 0x0 0x4000>; 162 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 163 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 164 #dma-cells = <1>; 165 clocks = <&cru ACLK_DMAC0_PERILP>; 166 clock-names = "apb_pclk"; 167 }; 168 169 dmac_peri: dma-controller@ff6e0000 { 170 compatible = "arm,pl330", "arm,primecell"; 171 reg = <0x0 0xff6e0000 0x0 0x4000>; 172 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 173 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 174 #dma-cells = <1>; 175 clocks = <&cru ACLK_DMAC1_PERILP>; 176 clock-names = "apb_pclk"; 177 }; 178 }; 179 180 pcie0: pcie@f8000000 { 181 compatible = "rockchip,rk3399-pcie"; 182 reg = <0x0 0xf8000000 0x0 0x2000000>, 183 <0x0 0xfd000000 0x0 0x1000000>; 184 reg-names = "axi-base", "apb-base"; 185 #address-cells = <3>; 186 #size-cells = <2>; 187 #interrupt-cells = <1>; 188 aspm-no-l0s; 189 bus-range = <0x0 0x1>; 190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 191 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 192 clock-names = "aclk", "aclk-perf", 193 "hclk", "pm"; 194 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 195 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 196 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 197 interrupt-names = "sys", "legacy", "client"; 198 interrupt-map-mask = <0 0 0 7>; 199 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 200 <0 0 0 2 &pcie0_intc 1>, 201 <0 0 0 3 &pcie0_intc 2>, 202 <0 0 0 4 &pcie0_intc 3>; 203 linux,pci-domain = <0>; 204 max-link-speed = <1>; 205 msi-map = <0x0 &its 0x0 0x1000>; 206 phys = <&pcie_phy>; 207 phy-names = "pcie-phy"; 208 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 209 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 210 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 211 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 212 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 213 <&cru SRST_A_PCIE>; 214 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 215 "pm", "pclk", "aclk"; 216 status = "disabled"; 217 218 pcie0_intc: interrupt-controller { 219 interrupt-controller; 220 #address-cells = <0>; 221 #interrupt-cells = <1>; 222 }; 223 }; 224 225 gmac: ethernet@fe300000 { 226 compatible = "rockchip,rk3399-gmac"; 227 reg = <0x0 0xfe300000 0x0 0x10000>; 228 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 229 interrupt-names = "macirq"; 230 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 231 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 232 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 233 <&cru PCLK_GMAC>; 234 clock-names = "stmmaceth", "mac_clk_rx", 235 "mac_clk_tx", "clk_mac_ref", 236 "clk_mac_refout", "aclk_mac", 237 "pclk_mac"; 238 power-domains = <&power RK3399_PD_GMAC>; 239 resets = <&cru SRST_A_GMAC>; 240 reset-names = "stmmaceth"; 241 rockchip,grf = <&grf>; 242 status = "disabled"; 243 }; 244 245 sdio0: dwmmc@fe310000 { 246 compatible = "rockchip,rk3399-dw-mshc", 247 "rockchip,rk3288-dw-mshc"; 248 reg = <0x0 0xfe310000 0x0 0x4000>; 249 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 250 max-frequency = <150000000>; 251 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 252 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 253 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 254 fifo-depth = <0x100>; 255 power-domains = <&power RK3399_PD_SDIOAUDIO>; 256 resets = <&cru SRST_SDIO0>; 257 reset-names = "reset"; 258 status = "disabled"; 259 }; 260 261 sdmmc: dwmmc@fe320000 { 262 compatible = "rockchip,rk3399-dw-mshc", 263 "rockchip,rk3288-dw-mshc"; 264 reg = <0x0 0xfe320000 0x0 0x4000>; 265 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 266 max-frequency = <150000000>; 267 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 268 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 269 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 270 fifo-depth = <0x100>; 271 power-domains = <&power RK3399_PD_SD>; 272 resets = <&cru SRST_SDMMC>; 273 reset-names = "reset"; 274 status = "disabled"; 275 }; 276 277 sdhci: sdhci@fe330000 { 278 u-boot,dm-pre-reloc; 279 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 280 reg = <0x0 0xfe330000 0x0 0x10000>; 281 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 282 arasan,soc-ctl-syscon = <&grf>; 283 assigned-clocks = <&cru SCLK_EMMC>; 284 assigned-clock-rates = <200000000>; 285 max-frequency = <200000000>; 286 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 287 clock-names = "clk_xin", "clk_ahb"; 288 clock-output-names = "emmc_cardclock"; 289 #clock-cells = <0>; 290 phys = <&emmc_phy>; 291 phy-names = "phy_arasan"; 292 power-domains = <&power RK3399_PD_EMMC>; 293 status = "disabled"; 294 }; 295 296 usb_host0_ehci: usb@fe380000 { 297 compatible = "generic-ehci"; 298 reg = <0x0 0xfe380000 0x0 0x20000>; 299 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 300 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 301 <&u2phy0>; 302 clock-names = "usbhost", "arbiter", 303 "utmi"; 304 phys = <&u2phy0_host>; 305 phy-names = "usb"; 306 power-domains = <&power RK3399_PD_PERIHP>; 307 status = "disabled"; 308 }; 309 310 usb_host0_ohci: usb@fe3a0000 { 311 compatible = "generic-ohci"; 312 reg = <0x0 0xfe3a0000 0x0 0x20000>; 313 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 314 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 315 <&u2phy0>; 316 clock-names = "usbhost", "arbiter", 317 "utmi"; 318 phys = <&u2phy0_host>; 319 phy-names = "usb"; 320 power-domains = <&power RK3399_PD_PERIHP>; 321 status = "disabled"; 322 }; 323 324 usb_host1_ehci: usb@fe3c0000 { 325 compatible = "generic-ehci"; 326 reg = <0x0 0xfe3c0000 0x0 0x20000>; 327 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 328 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 329 <&u2phy1>; 330 clock-names = "usbhost", "arbiter", 331 "utmi"; 332 phys = <&u2phy1_host>; 333 phy-names = "usb"; 334 power-domains = <&power RK3399_PD_PERIHP>; 335 status = "disabled"; 336 }; 337 338 usb_host1_ohci: usb@fe3e0000 { 339 compatible = "generic-ohci"; 340 reg = <0x0 0xfe3e0000 0x0 0x20000>; 341 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 342 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 343 <&u2phy1>; 344 clock-names = "usbhost", "arbiter", 345 "utmi"; 346 phys = <&u2phy1_host>; 347 phy-names = "usb"; 348 power-domains = <&power RK3399_PD_PERIHP>; 349 status = "disabled"; 350 }; 351 352 dwc3_typec0: usb@fe800000 { 353 compatible = "rockchip,rk3399-xhci"; 354 reg = <0x0 0xfe800000 0x0 0x100000>; 355 status = "disabled"; 356 snps,dis-enblslpm-quirk; 357 snps,phyif-utmi-bits = <16>; 358 snps,dis-u2-freeclk-exists-quirk; 359 snps,dis-u2-susphy-quirk; 360 361 #address-cells = <2>; 362 #size-cells = <2>; 363 hub { 364 compatible = "usb-hub"; 365 usb,device-class = <USB_CLASS_HUB>; 366 }; 367 typec_phy0 { 368 compatible = "rockchip,rk3399-usb3-phy"; 369 reg = <0x0 0xff7c0000 0x0 0x40000>; 370 }; 371 }; 372 373 dwc3_typec1: usb@fe900000 { 374 compatible = "rockchip,rk3399-xhci"; 375 reg = <0x0 0xfe900000 0x0 0x100000>; 376 status = "disabled"; 377 snps,dis-enblslpm-quirk; 378 snps,phyif-utmi-bits = <16>; 379 snps,dis-u2-freeclk-exists-quirk; 380 snps,dis-u2-susphy-quirk; 381 382 #address-cells = <2>; 383 #size-cells = <2>; 384 hub { 385 compatible = "usb-hub"; 386 usb,device-class = <USB_CLASS_HUB>; 387 }; 388 typec_phy1 { 389 compatible = "rockchip,rk3399-usb3-phy"; 390 reg = <0x0 0xff800000 0x0 0x40000>; 391 }; 392 }; 393 394 gic: interrupt-controller@fee00000 { 395 compatible = "arm,gic-v3"; 396 #interrupt-cells = <4>; 397 #address-cells = <2>; 398 #size-cells = <2>; 399 ranges; 400 interrupt-controller; 401 402 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 403 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 404 <0x0 0xfff00000 0 0x10000>, /* GICC */ 405 <0x0 0xfff10000 0 0x10000>, /* GICH */ 406 <0x0 0xfff20000 0 0x10000>; /* GICV */ 407 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 408 its: interrupt-controller@fee20000 { 409 compatible = "arm,gic-v3-its"; 410 msi-controller; 411 reg = <0x0 0xfee20000 0x0 0x20000>; 412 }; 413 414 ppi-partitions { 415 ppi_cluster0: interrupt-partition-0 { 416 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 417 }; 418 419 ppi_cluster1: interrupt-partition-1 { 420 affinity = <&cpu_b0 &cpu_b1>; 421 }; 422 }; 423 }; 424 425 saradc: saradc@ff100000 { 426 compatible = "rockchip,rk3399-saradc"; 427 reg = <0x0 0xff100000 0x0 0x100>; 428 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 429 #io-channel-cells = <1>; 430 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 431 clock-names = "saradc", "apb_pclk"; 432 resets = <&cru SRST_P_SARADC>; 433 reset-names = "saradc-apb"; 434 status = "disabled"; 435 }; 436 437 i2c1: i2c@ff110000 { 438 compatible = "rockchip,rk3399-i2c"; 439 reg = <0x0 0xff110000 0x0 0x1000>; 440 assigned-clocks = <&cru SCLK_I2C1>; 441 assigned-clock-rates = <200000000>; 442 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 443 clock-names = "i2c", "pclk"; 444 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&i2c1_xfer>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 i2c2: i2c@ff120000 { 453 compatible = "rockchip,rk3399-i2c"; 454 reg = <0x0 0xff120000 0x0 0x1000>; 455 assigned-clocks = <&cru SCLK_I2C2>; 456 assigned-clock-rates = <200000000>; 457 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 458 clock-names = "i2c", "pclk"; 459 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&i2c2_xfer>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 status = "disabled"; 465 }; 466 467 i2c3: i2c@ff130000 { 468 compatible = "rockchip,rk3399-i2c"; 469 reg = <0x0 0xff130000 0x0 0x1000>; 470 assigned-clocks = <&cru SCLK_I2C3>; 471 assigned-clock-rates = <200000000>; 472 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 473 clock-names = "i2c", "pclk"; 474 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&i2c3_xfer>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 i2c5: i2c@ff140000 { 483 compatible = "rockchip,rk3399-i2c"; 484 reg = <0x0 0xff140000 0x0 0x1000>; 485 assigned-clocks = <&cru SCLK_I2C5>; 486 assigned-clock-rates = <200000000>; 487 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 488 clock-names = "i2c", "pclk"; 489 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&i2c5_xfer>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 status = "disabled"; 495 }; 496 497 i2c6: i2c@ff150000 { 498 compatible = "rockchip,rk3399-i2c"; 499 reg = <0x0 0xff150000 0x0 0x1000>; 500 assigned-clocks = <&cru SCLK_I2C6>; 501 assigned-clock-rates = <200000000>; 502 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 503 clock-names = "i2c", "pclk"; 504 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&i2c6_xfer>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 status = "disabled"; 510 }; 511 512 i2c7: i2c@ff160000 { 513 compatible = "rockchip,rk3399-i2c"; 514 reg = <0x0 0xff160000 0x0 0x1000>; 515 assigned-clocks = <&cru SCLK_I2C7>; 516 assigned-clock-rates = <200000000>; 517 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 518 clock-names = "i2c", "pclk"; 519 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&i2c7_xfer>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 uart0: serial@ff180000 { 528 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 529 reg = <0x0 0xff180000 0x0 0x100>; 530 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 531 clock-names = "baudclk", "apb_pclk"; 532 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 533 reg-shift = <2>; 534 reg-io-width = <4>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&uart0_xfer>; 537 status = "disabled"; 538 }; 539 540 uart1: serial@ff190000 { 541 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 542 reg = <0x0 0xff190000 0x0 0x100>; 543 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 544 clock-names = "baudclk", "apb_pclk"; 545 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 546 reg-shift = <2>; 547 reg-io-width = <4>; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&uart1_xfer>; 550 status = "disabled"; 551 }; 552 553 uart2: serial@ff1a0000 { 554 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 555 reg = <0x0 0xff1a0000 0x0 0x100>; 556 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 557 clock-names = "baudclk", "apb_pclk"; 558 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 559 clock-frequency = <24000000>; 560 reg-shift = <2>; 561 reg-io-width = <4>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&uart2c_xfer>; 564 status = "disabled"; 565 }; 566 567 uart3: serial@ff1b0000 { 568 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 569 reg = <0x0 0xff1b0000 0x0 0x100>; 570 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 571 clock-names = "baudclk", "apb_pclk"; 572 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 573 reg-shift = <2>; 574 reg-io-width = <4>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&uart3_xfer>; 577 status = "disabled"; 578 }; 579 580 spi0: spi@ff1c0000 { 581 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 582 reg = <0x0 0xff1c0000 0x0 0x1000>; 583 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 584 clock-names = "spiclk", "apb_pclk"; 585 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 status = "disabled"; 591 }; 592 593 spi1: spi@ff1d0000 { 594 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 595 reg = <0x0 0xff1d0000 0x0 0x1000>; 596 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 597 clock-names = "spiclk", "apb_pclk"; 598 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 status = "disabled"; 604 }; 605 606 spi2: spi@ff1e0000 { 607 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 608 reg = <0x0 0xff1e0000 0x0 0x1000>; 609 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 610 clock-names = "spiclk", "apb_pclk"; 611 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 status = "disabled"; 617 }; 618 619 spi4: spi@ff1f0000 { 620 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 621 reg = <0x0 0xff1f0000 0x0 0x1000>; 622 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 623 clock-names = "spiclk", "apb_pclk"; 624 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 status = "disabled"; 630 }; 631 632 spi5: spi@ff200000 { 633 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 634 reg = <0x0 0xff200000 0x0 0x1000>; 635 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 636 clock-names = "spiclk", "apb_pclk"; 637 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 status = "disabled"; 643 }; 644 645 thermal_zones: thermal-zones { 646 cpu_thermal: cpu { 647 polling-delay-passive = <100>; 648 polling-delay = <1000>; 649 650 thermal-sensors = <&tsadc 0>; 651 652 trips { 653 cpu_alert0: cpu_alert0 { 654 temperature = <70000>; 655 hysteresis = <2000>; 656 type = "passive"; 657 }; 658 cpu_alert1: cpu_alert1 { 659 temperature = <75000>; 660 hysteresis = <2000>; 661 type = "passive"; 662 }; 663 cpu_crit: cpu_crit { 664 temperature = <95000>; 665 hysteresis = <2000>; 666 type = "critical"; 667 }; 668 }; 669 670 cooling-maps { 671 map0 { 672 trip = <&cpu_alert0>; 673 cooling-device = 674 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 675 }; 676 map1 { 677 trip = <&cpu_alert1>; 678 cooling-device = 679 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 680 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 681 }; 682 }; 683 }; 684 685 gpu_thermal: gpu { 686 polling-delay-passive = <100>; 687 polling-delay = <1000>; 688 689 thermal-sensors = <&tsadc 1>; 690 691 trips { 692 gpu_alert0: gpu_alert0 { 693 temperature = <75000>; 694 hysteresis = <2000>; 695 type = "passive"; 696 }; 697 gpu_crit: gpu_crit { 698 temperature = <95000>; 699 hysteresis = <2000>; 700 type = "critical"; 701 }; 702 }; 703 704 cooling-maps { 705 map0 { 706 trip = <&gpu_alert0>; 707 cooling-device = 708 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 709 }; 710 }; 711 }; 712 }; 713 714 tsadc: tsadc@ff260000 { 715 compatible = "rockchip,rk3399-tsadc"; 716 reg = <0x0 0xff260000 0x0 0x100>; 717 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 718 assigned-clocks = <&cru SCLK_TSADC>; 719 assigned-clock-rates = <750000>; 720 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 721 clock-names = "tsadc", "apb_pclk"; 722 resets = <&cru SRST_TSADC>; 723 reset-names = "tsadc-apb"; 724 rockchip,grf = <&grf>; 725 rockchip,hw-tshut-temp = <95000>; 726 pinctrl-names = "init", "default", "sleep"; 727 pinctrl-0 = <&otp_gpio>; 728 pinctrl-1 = <&otp_out>; 729 pinctrl-2 = <&otp_gpio>; 730 #thermal-sensor-cells = <1>; 731 status = "disabled"; 732 }; 733 734 qos_emmc: qos@ffa58000 { 735 compatible = "syscon"; 736 reg = <0x0 0xffa58000 0x0 0x20>; 737 }; 738 739 qos_gmac: qos@ffa5c000 { 740 compatible = "syscon"; 741 reg = <0x0 0xffa5c000 0x0 0x20>; 742 }; 743 744 qos_pcie: qos@ffa60080 { 745 compatible = "syscon"; 746 reg = <0x0 0xffa60080 0x0 0x20>; 747 }; 748 749 qos_usb_host0: qos@ffa60100 { 750 compatible = "syscon"; 751 reg = <0x0 0xffa60100 0x0 0x20>; 752 }; 753 754 qos_usb_host1: qos@ffa60180 { 755 compatible = "syscon"; 756 reg = <0x0 0xffa60180 0x0 0x20>; 757 }; 758 759 qos_usb_otg0: qos@ffa70000 { 760 compatible = "syscon"; 761 reg = <0x0 0xffa70000 0x0 0x20>; 762 }; 763 764 qos_usb_otg1: qos@ffa70080 { 765 compatible = "syscon"; 766 reg = <0x0 0xffa70080 0x0 0x20>; 767 }; 768 769 qos_sd: qos@ffa74000 { 770 compatible = "syscon"; 771 reg = <0x0 0xffa74000 0x0 0x20>; 772 }; 773 774 qos_sdioaudio: qos@ffa76000 { 775 compatible = "syscon"; 776 reg = <0x0 0xffa76000 0x0 0x20>; 777 }; 778 779 qos_hdcp: qos@ffa90000 { 780 compatible = "syscon"; 781 reg = <0x0 0xffa90000 0x0 0x20>; 782 }; 783 784 qos_iep: qos@ffa98000 { 785 compatible = "syscon"; 786 reg = <0x0 0xffa98000 0x0 0x20>; 787 }; 788 789 qos_isp0_m0: qos@ffaa0000 { 790 compatible = "syscon"; 791 reg = <0x0 0xffaa0000 0x0 0x20>; 792 }; 793 794 qos_isp0_m1: qos@ffaa0080 { 795 compatible = "syscon"; 796 reg = <0x0 0xffaa0080 0x0 0x20>; 797 }; 798 799 qos_isp1_m0: qos@ffaa8000 { 800 compatible = "syscon"; 801 reg = <0x0 0xffaa8000 0x0 0x20>; 802 }; 803 804 qos_isp1_m1: qos@ffaa8080 { 805 compatible = "syscon"; 806 reg = <0x0 0xffaa8080 0x0 0x20>; 807 }; 808 809 qos_rga_r: qos@ffab0000 { 810 compatible = "syscon"; 811 reg = <0x0 0xffab0000 0x0 0x20>; 812 }; 813 814 qos_rga_w: qos@ffab0080 { 815 compatible = "syscon"; 816 reg = <0x0 0xffab0080 0x0 0x20>; 817 }; 818 819 qos_video_m0: qos@ffab8000 { 820 compatible = "syscon"; 821 reg = <0x0 0xffab8000 0x0 0x20>; 822 }; 823 824 qos_video_m1_r: qos@ffac0000 { 825 compatible = "syscon"; 826 reg = <0x0 0xffac0000 0x0 0x20>; 827 }; 828 829 qos_video_m1_w: qos@ffac0080 { 830 compatible = "syscon"; 831 reg = <0x0 0xffac0080 0x0 0x20>; 832 }; 833 834 qos_vop_big_r: qos@ffac8000 { 835 compatible = "syscon"; 836 reg = <0x0 0xffac8000 0x0 0x20>; 837 }; 838 839 qos_vop_big_w: qos@ffac8080 { 840 compatible = "syscon"; 841 reg = <0x0 0xffac8080 0x0 0x20>; 842 }; 843 844 qos_vop_little: qos@ffad0000 { 845 compatible = "syscon"; 846 reg = <0x0 0xffad0000 0x0 0x20>; 847 }; 848 849 qos_perihp: qos@ffad8080 { 850 compatible = "syscon"; 851 reg = <0x0 0xffad8080 0x0 0x20>; 852 }; 853 854 qos_gpu: qos@ffae0000 { 855 compatible = "syscon"; 856 reg = <0x0 0xffae0000 0x0 0x20>; 857 }; 858 859 pmu: power-management@ff310000 { 860 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 861 reg = <0x0 0xff310000 0x0 0x1000>; 862 863 /* 864 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 865 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 866 * Some of the power domains are grouped together for every 867 * voltage domain. 868 * The detail contents as below. 869 */ 870 power: power-controller { 871 compatible = "rockchip,rk3399-power-controller"; 872 #power-domain-cells = <1>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 876 /* These power domains are grouped by VD_CENTER */ 877 pd_iep@RK3399_PD_IEP { 878 reg = <RK3399_PD_IEP>; 879 clocks = <&cru ACLK_IEP>, 880 <&cru HCLK_IEP>; 881 pm_qos = <&qos_iep>; 882 }; 883 pd_rga@RK3399_PD_RGA { 884 reg = <RK3399_PD_RGA>; 885 clocks = <&cru ACLK_RGA>, 886 <&cru HCLK_RGA>; 887 pm_qos = <&qos_rga_r>, 888 <&qos_rga_w>; 889 }; 890 pd_vcodec@RK3399_PD_VCODEC { 891 reg = <RK3399_PD_VCODEC>; 892 clocks = <&cru ACLK_VCODEC>, 893 <&cru HCLK_VCODEC>; 894 pm_qos = <&qos_video_m0>; 895 }; 896 pd_vdu@RK3399_PD_VDU { 897 reg = <RK3399_PD_VDU>; 898 clocks = <&cru ACLK_VDU>, 899 <&cru HCLK_VDU>; 900 pm_qos = <&qos_video_m1_r>, 901 <&qos_video_m1_w>; 902 }; 903 904 /* These power domains are grouped by VD_GPU */ 905 pd_gpu@RK3399_PD_GPU { 906 reg = <RK3399_PD_GPU>; 907 clocks = <&cru ACLK_GPU>; 908 pm_qos = <&qos_gpu>; 909 }; 910 911 /* These power domains are grouped by VD_LOGIC */ 912 pd_edp@RK3399_PD_EDP { 913 reg = <RK3399_PD_EDP>; 914 clocks = <&cru PCLK_EDP_CTRL>; 915 }; 916 pd_emmc@RK3399_PD_EMMC { 917 reg = <RK3399_PD_EMMC>; 918 clocks = <&cru ACLK_EMMC>; 919 pm_qos = <&qos_emmc>; 920 }; 921 pd_gmac@RK3399_PD_GMAC { 922 reg = <RK3399_PD_GMAC>; 923 clocks = <&cru ACLK_GMAC>, 924 <&cru PCLK_GMAC>; 925 pm_qos = <&qos_gmac>; 926 }; 927 pd_perihp@RK3399_PD_PERIHP { 928 reg = <RK3399_PD_PERIHP>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 clocks = <&cru ACLK_PERIHP>; 932 pm_qos = <&qos_perihp>, 933 <&qos_pcie>, 934 <&qos_usb_host0>, 935 <&qos_usb_host1>; 936 937 pd_sd@RK3399_PD_SD { 938 reg = <RK3399_PD_SD>; 939 clocks = <&cru HCLK_SDMMC>, 940 <&cru SCLK_SDMMC>; 941 pm_qos = <&qos_sd>; 942 }; 943 }; 944 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 945 reg = <RK3399_PD_SDIOAUDIO>; 946 clocks = <&cru HCLK_SDIO>; 947 pm_qos = <&qos_sdioaudio>; 948 }; 949 pd_usb3@RK3399_PD_USB3 { 950 reg = <RK3399_PD_USB3>; 951 clocks = <&cru ACLK_USB3>; 952 pm_qos = <&qos_usb_otg0>, 953 <&qos_usb_otg1>; 954 }; 955 pd_vio@RK3399_PD_VIO { 956 reg = <RK3399_PD_VIO>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 pd_hdcp@RK3399_PD_HDCP { 961 reg = <RK3399_PD_HDCP>; 962 clocks = <&cru ACLK_HDCP>, 963 <&cru HCLK_HDCP>, 964 <&cru PCLK_HDCP>; 965 pm_qos = <&qos_hdcp>; 966 }; 967 pd_isp0@RK3399_PD_ISP0 { 968 reg = <RK3399_PD_ISP0>; 969 clocks = <&cru ACLK_ISP0>, 970 <&cru HCLK_ISP0>; 971 pm_qos = <&qos_isp0_m0>, 972 <&qos_isp0_m1>; 973 }; 974 pd_isp1@RK3399_PD_ISP1 { 975 reg = <RK3399_PD_ISP1>; 976 clocks = <&cru ACLK_ISP1>, 977 <&cru HCLK_ISP1>; 978 pm_qos = <&qos_isp1_m0>, 979 <&qos_isp1_m1>; 980 }; 981 pd_tcpc0@RK3399_PD_TCPC0 { 982 reg = <RK3399_PD_TCPD0>; 983 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 984 <&cru SCLK_UPHY0_TCPDPHY_REF>; 985 }; 986 pd_tcpc1@RK3399_PD_TCPC1 { 987 reg = <RK3399_PD_TCPD1>; 988 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 989 <&cru SCLK_UPHY1_TCPDPHY_REF>; 990 }; 991 pd_vo@RK3399_PD_VO { 992 reg = <RK3399_PD_VO>; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 996 pd_vopb@RK3399_PD_VOPB { 997 reg = <RK3399_PD_VOPB>; 998 clocks = <&cru ACLK_VOP0>, 999 <&cru HCLK_VOP0>; 1000 pm_qos = <&qos_vop_big_r>, 1001 <&qos_vop_big_w>; 1002 }; 1003 pd_vopl@RK3399_PD_VOPL { 1004 reg = <RK3399_PD_VOPL>; 1005 clocks = <&cru ACLK_VOP1>, 1006 <&cru HCLK_VOP1>; 1007 pm_qos = <&qos_vop_little>; 1008 }; 1009 }; 1010 }; 1011 }; 1012 }; 1013 1014 pmugrf: syscon@ff320000 { 1015 u-boot,dm-pre-reloc; 1016 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1017 reg = <0x0 0xff320000 0x0 0x1000>; 1018 1019 pmu_io_domains: io-domains { 1020 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1021 status = "disabled"; 1022 }; 1023 }; 1024 1025 pmusgrf: syscon@ff330000 { 1026 u-boot,dm-pre-reloc; 1027 compatible = "rockchip,rk3399-pmusgrf", "syscon"; 1028 reg = <0x0 0xff330000 0x0 0xe3d4>; 1029 }; 1030 1031 spi3: spi@ff350000 { 1032 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1033 reg = <0x0 0xff350000 0x0 0x1000>; 1034 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1035 clock-names = "spiclk", "apb_pclk"; 1036 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 status = "disabled"; 1042 }; 1043 1044 uart4: serial@ff370000 { 1045 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1046 reg = <0x0 0xff370000 0x0 0x100>; 1047 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1048 clock-names = "baudclk", "apb_pclk"; 1049 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1050 reg-shift = <2>; 1051 reg-io-width = <4>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&uart4_xfer>; 1054 status = "disabled"; 1055 }; 1056 1057 i2c4: i2c@ff3d0000 { 1058 compatible = "rockchip,rk3399-i2c"; 1059 reg = <0x0 0xff3d0000 0x0 0x1000>; 1060 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1061 assigned-clock-rates = <200000000>; 1062 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1063 clock-names = "i2c", "pclk"; 1064 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&i2c4_xfer>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 i2c8: i2c@ff3e0000 { 1073 compatible = "rockchip,rk3399-i2c"; 1074 reg = <0x0 0xff3e0000 0x0 0x1000>; 1075 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1076 assigned-clock-rates = <200000000>; 1077 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1078 clock-names = "i2c", "pclk"; 1079 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1080 pinctrl-names = "default"; 1081 pinctrl-0 = <&i2c8_xfer>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 pwm0: pwm@ff420000 { 1088 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1089 reg = <0x0 0xff420000 0x0 0x10>; 1090 #pwm-cells = <3>; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&pwm0_pin>; 1093 clocks = <&pmucru PCLK_RKPWM_PMU>; 1094 clock-names = "pwm"; 1095 status = "disabled"; 1096 }; 1097 1098 pwm1: pwm@ff420010 { 1099 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1100 reg = <0x0 0xff420010 0x0 0x10>; 1101 #pwm-cells = <3>; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&pwm1_pin>; 1104 clocks = <&pmucru PCLK_RKPWM_PMU>; 1105 clock-names = "pwm"; 1106 status = "disabled"; 1107 }; 1108 1109 pwm2: pwm@ff420020 { 1110 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1111 reg = <0x0 0xff420020 0x0 0x10>; 1112 #pwm-cells = <3>; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&pwm2_pin>; 1115 clocks = <&pmucru PCLK_RKPWM_PMU>; 1116 clock-names = "pwm"; 1117 status = "disabled"; 1118 }; 1119 1120 pwm3: pwm@ff420030 { 1121 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1122 reg = <0x0 0xff420030 0x0 0x10>; 1123 #pwm-cells = <3>; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&pwm3a_pin>; 1126 clocks = <&pmucru PCLK_RKPWM_PMU>; 1127 clock-names = "pwm"; 1128 status = "disabled"; 1129 }; 1130 1131 cic: syscon@ff620000 { 1132 u-boot,dm-pre-reloc; 1133 compatible = "rockchip,rk3399-cic", "syscon"; 1134 reg = <0x0 0xff620000 0x0 0x100>; 1135 }; 1136 1137 dfi: dfi@ff630000 { 1138 reg = <0x00 0xff630000 0x00 0x4000>; 1139 compatible = "rockchip,rk3399-dfi"; 1140 rockchip,pmu = <&pmugrf>; 1141 clocks = <&cru PCLK_DDR_MON>; 1142 clock-names = "pclk_ddr_mon"; 1143 status = "disabled"; 1144 }; 1145 1146 dmc: dmc { 1147 u-boot,dm-pre-reloc; 1148 compatible = "rockchip,rk3399-dmc"; 1149 devfreq-events = <&dfi>; 1150 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 1151 clocks = <&cru SCLK_DDRCLK>; 1152 clock-names = "dmc_clk"; 1153 reg = <0x0 0xffa80000 0x0 0x0800 1154 0x0 0xffa80800 0x0 0x1800 1155 0x0 0xffa82000 0x0 0x2000 1156 0x0 0xffa84000 0x0 0x1000 1157 0x0 0xffa88000 0x0 0x0800 1158 0x0 0xffa88800 0x0 0x1800 1159 0x0 0xffa8a000 0x0 0x2000 1160 0x0 0xffa8c000 0x0 0x1000>; 1161 }; 1162 1163 efuse0: efuse@ff690000 { 1164 compatible = "rockchip,rk3399-efuse"; 1165 reg = <0x0 0xff690000 0x0 0x80>; 1166 #address-cells = <1>; 1167 #size-cells = <1>; 1168 clocks = <&cru PCLK_EFUSE1024NS>; 1169 clock-names = "pclk_efuse"; 1170 1171 /* Data cells */ 1172 cpu_id: cpu-id@7 { 1173 reg = <0x07 0x10>; 1174 }; 1175 cpub_leakage: cpu-leakage@17 { 1176 reg = <0x17 0x1>; 1177 }; 1178 gpu_leakage: gpu-leakage@18 { 1179 reg = <0x18 0x1>; 1180 }; 1181 center_leakage: center-leakage@19 { 1182 reg = <0x19 0x1>; 1183 }; 1184 cpul_leakage: cpu-leakage@1a { 1185 reg = <0x1a 0x1>; 1186 }; 1187 logic_leakage: logic-leakage@1b { 1188 reg = <0x1b 0x1>; 1189 }; 1190 wafer_info: wafer-info@1c { 1191 reg = <0x1c 0x1>; 1192 }; 1193 }; 1194 1195 pmucru: pmu-clock-controller@ff750000 { 1196 u-boot,dm-pre-reloc; 1197 compatible = "rockchip,rk3399-pmucru"; 1198 reg = <0x0 0xff750000 0x0 0x1000>; 1199 rockchip,grf = <&pmugrf>; 1200 #clock-cells = <1>; 1201 #reset-cells = <1>; 1202 assigned-clocks = <&pmucru PLL_PPLL>; 1203 assigned-clock-rates = <676000000>; 1204 }; 1205 1206 cru: clock-controller@ff760000 { 1207 u-boot,dm-pre-reloc; 1208 compatible = "rockchip,rk3399-cru"; 1209 reg = <0x0 0xff760000 0x0 0x1000>; 1210 rockchip,grf = <&grf>; 1211 #clock-cells = <1>; 1212 #reset-cells = <1>; 1213 assigned-clocks = 1214 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1215 <&cru PLL_NPLL>, 1216 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1217 <&cru PCLK_PERIHP>, 1218 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1219 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1220 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; 1221 assigned-clock-rates = 1222 <594000000>, <800000000>, 1223 <1000000000>, 1224 <150000000>, <75000000>, 1225 <37500000>, 1226 <100000000>, <100000000>, 1227 <50000000>, <600000000>, 1228 <100000000>, <50000000>; 1229 }; 1230 1231 grf: syscon@ff770000 { 1232 u-boot,dm-pre-reloc; 1233 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1234 reg = <0x0 0xff770000 0x0 0x10000>; 1235 #address-cells = <1>; 1236 #size-cells = <1>; 1237 1238 io_domains: io-domains { 1239 compatible = "rockchip,rk3399-io-voltage-domain"; 1240 status = "disabled"; 1241 }; 1242 1243 u2phy0: usb2-phy@e450 { 1244 compatible = "rockchip,rk3399-usb2phy"; 1245 reg = <0xe450 0x10>; 1246 clocks = <&cru SCLK_USB2PHY0_REF>; 1247 clock-names = "phyclk"; 1248 #clock-cells = <0>; 1249 clock-output-names = "clk_usbphy0_480m"; 1250 status = "disabled"; 1251 1252 u2phy0_host: host-port { 1253 #phy-cells = <0>; 1254 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1255 interrupt-names = "linestate"; 1256 status = "disabled"; 1257 }; 1258 1259 u2phy0_otg: otg-port { 1260 #phy-cells = <0>; 1261 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1262 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1263 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1264 interrupt-names = "otg-bvalid", "otg-id", 1265 "linestate"; 1266 status = "disabled"; 1267 }; 1268 }; 1269 1270 u2phy1: usb2-phy@e460 { 1271 compatible = "rockchip,rk3399-usb2phy"; 1272 reg = <0xe460 0x10>; 1273 clocks = <&cru SCLK_USB2PHY1_REF>; 1274 clock-names = "phyclk"; 1275 #clock-cells = <0>; 1276 clock-output-names = "clk_usbphy1_480m"; 1277 status = "disabled"; 1278 1279 u2phy1_host: host-port { 1280 #phy-cells = <0>; 1281 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1282 interrupt-names = "linestate"; 1283 status = "disabled"; 1284 }; 1285 1286 u2phy1_otg: otg-port { 1287 #phy-cells = <0>; 1288 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1289 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1290 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1291 interrupt-names = "otg-bvalid", "otg-id", 1292 "linestate"; 1293 status = "disabled"; 1294 }; 1295 }; 1296 1297 emmc_phy: phy@f780 { 1298 compatible = "rockchip,rk3399-emmc-phy"; 1299 reg = <0xf780 0x24>; 1300 clocks = <&sdhci>; 1301 clock-names = "emmcclk"; 1302 #phy-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 pcie_phy: pcie-phy { 1307 compatible = "rockchip,rk3399-pcie-phy"; 1308 clocks = <&cru SCLK_PCIEPHY_REF>; 1309 clock-names = "refclk"; 1310 #phy-cells = <0>; 1311 resets = <&cru SRST_PCIEPHY>; 1312 reset-names = "phy"; 1313 status = "disabled"; 1314 }; 1315 }; 1316 1317 watchdog@ff848000 { 1318 compatible = "snps,dw-wdt"; 1319 reg = <0x0 0xff848000 0x0 0x100>; 1320 clocks = <&cru PCLK_WDT>; 1321 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1322 }; 1323 1324 rktimer: rktimer@ff850000 { 1325 compatible = "rockchip,rk3399-timer"; 1326 reg = <0x0 0xff850000 0x0 0x1000>; 1327 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1328 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1329 clock-names = "pclk", "timer"; 1330 }; 1331 1332 spdif: spdif@ff870000 { 1333 compatible = "rockchip,rk3399-spdif"; 1334 reg = <0x0 0xff870000 0x0 0x1000>; 1335 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1336 dmas = <&dmac_bus 7>; 1337 dma-names = "tx"; 1338 clock-names = "mclk", "hclk"; 1339 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&spdif_bus>; 1342 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1343 status = "disabled"; 1344 }; 1345 1346 i2s0: i2s@ff880000 { 1347 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1348 reg = <0x0 0xff880000 0x0 0x1000>; 1349 rockchip,grf = <&grf>; 1350 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1351 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1352 dma-names = "tx", "rx"; 1353 clock-names = "i2s_clk", "i2s_hclk"; 1354 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&i2s0_8ch_bus>; 1357 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1358 status = "disabled"; 1359 }; 1360 1361 i2s1: i2s@ff890000 { 1362 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1363 reg = <0x0 0xff890000 0x0 0x1000>; 1364 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1365 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1366 dma-names = "tx", "rx"; 1367 clock-names = "i2s_clk", "i2s_hclk"; 1368 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&i2s1_2ch_bus>; 1371 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1372 status = "disabled"; 1373 }; 1374 1375 i2s2: i2s@ff8a0000 { 1376 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1377 reg = <0x0 0xff8a0000 0x0 0x1000>; 1378 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1379 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1380 dma-names = "tx", "rx"; 1381 clock-names = "i2s_clk", "i2s_hclk"; 1382 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1383 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1384 status = "disabled"; 1385 }; 1386 1387 i2c0: i2c@ff3c0000 { 1388 compatible = "rockchip,rk3399-i2c"; 1389 reg = <0x0 0xff3c0000 0x0 0x1000>; 1390 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1391 assigned-clock-rates = <200000000>; 1392 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1393 clock-names = "i2c", "pclk"; 1394 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1395 pinctrl-names = "default"; 1396 pinctrl-0 = <&i2c0_xfer>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 1402 vopl: vop@ff8f0000 { 1403 u-boot,dm-pre-reloc; 1404 compatible = "rockchip,rk3399-vop-lit"; 1405 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1406 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1407 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1408 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1409 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1410 reset-names = "axi", "ahb", "dclk"; 1411 status = "disabled"; 1412 vopl_out: port { 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 vopl_out_mipi: endpoint@0 { 1416 reg = <3>; 1417 remote-endpoint = <&mipi_in_vopl>; 1418 }; 1419 1420 vopl_out_hdmi: endpoint@1 { 1421 reg = <1>; 1422 remote-endpoint = <&hdmi_in_vopl>; 1423 }; 1424 }; 1425 }; 1426 1427 vopb: vop@ff900000 { 1428 u-boot,dm-pre-reloc; 1429 compatible = "rockchip,rk3399-vop-big"; 1430 reg = <0x0 0xff900000 0x0 0x3efc>; 1431 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1432 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1433 #clock-cells = <0>; 1434 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1435 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1436 reset-names = "axi", "ahb", "dclk"; 1437 status = "disabled"; 1438 vopb_out: port { 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 vopb_out_mipi: endpoint@0 { 1442 reg = <3>; 1443 remote-endpoint = <&mipi_in_vopb>; 1444 }; 1445 1446 vopb_out_hdmi: endpoint@1 { 1447 reg = <1>; 1448 remote-endpoint = <&hdmi_in_vopb>; 1449 }; 1450 }; 1451 }; 1452 1453 hdmi: hdmi@ff940000 { 1454 compatible = "rockchip,rk3399-dw-hdmi"; 1455 reg = <0x0 0xff940000 0x0 0x20000>; 1456 reg-io-width = <4>; 1457 rockchip,grf = <&grf>; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&hdmi_i2c_xfer>; 1460 power-domains = <&power RK3399_PD_HDCP>; 1461 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1462 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; 1463 clock-names = "iahb", "isfr", "vpll", "grf"; 1464 status = "disabled"; 1465 1466 ports { 1467 hdmi_in: port { 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 hdmi_in_vopb: endpoint@0 { 1471 reg = <0>; 1472 remote-endpoint = <&vopb_out_hdmi>; 1473 }; 1474 hdmi_in_vopl: endpoint@1 { 1475 reg = <1>; 1476 remote-endpoint = <&vopl_out_hdmi>; 1477 }; 1478 }; 1479 }; 1480 }; 1481 1482 mipi_dsi: mipi@ff960000 { 1483 compatible = "rockchip,rk3399_mipi_dsi"; 1484 reg = <0x0 0xff960000 0x0 0x8000>; 1485 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1486 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, 1487 <&cru SCLK_DPHY_TX0_CFG>; 1488 clock-names = "ref", "pclk", "phy_cfg"; 1489 rockchip,grf = <&grf>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 ports { 1494 reg = <1>; 1495 mipi_in: port { 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 mipi_in_vopb: endpoint@0 { 1499 reg = <0>; 1500 remote-endpoint = <&vopb_out_mipi>; 1501 }; 1502 mipi_in_vopl: endpoint@1 { 1503 reg = <1>; 1504 remote-endpoint = <&vopl_out_mipi>; 1505 }; 1506 }; 1507 }; 1508 }; 1509 1510 pinctrl: pinctrl { 1511 u-boot,dm-pre-reloc; 1512 compatible = "rockchip,rk3399-pinctrl"; 1513 rockchip,grf = <&grf>; 1514 rockchip,pmu = <&pmugrf>; 1515 #address-cells = <2>; 1516 #size-cells = <2>; 1517 ranges; 1518 1519 gpio0: gpio0@ff720000 { 1520 compatible = "rockchip,gpio-bank"; 1521 reg = <0x0 0xff720000 0x0 0x100>; 1522 clocks = <&pmucru PCLK_GPIO0_PMU>; 1523 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1524 1525 gpio-controller; 1526 #gpio-cells = <0x2>; 1527 1528 interrupt-controller; 1529 #interrupt-cells = <0x2>; 1530 }; 1531 1532 gpio1: gpio1@ff730000 { 1533 compatible = "rockchip,gpio-bank"; 1534 reg = <0x0 0xff730000 0x0 0x100>; 1535 clocks = <&pmucru PCLK_GPIO1_PMU>; 1536 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1537 1538 gpio-controller; 1539 #gpio-cells = <0x2>; 1540 1541 interrupt-controller; 1542 #interrupt-cells = <0x2>; 1543 }; 1544 1545 gpio2: gpio2@ff780000 { 1546 compatible = "rockchip,gpio-bank"; 1547 reg = <0x0 0xff780000 0x0 0x100>; 1548 clocks = <&cru PCLK_GPIO2>; 1549 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1550 1551 gpio-controller; 1552 #gpio-cells = <0x2>; 1553 1554 interrupt-controller; 1555 #interrupt-cells = <0x2>; 1556 }; 1557 1558 gpio3: gpio3@ff788000 { 1559 compatible = "rockchip,gpio-bank"; 1560 reg = <0x0 0xff788000 0x0 0x100>; 1561 clocks = <&cru PCLK_GPIO3>; 1562 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1563 1564 gpio-controller; 1565 #gpio-cells = <0x2>; 1566 1567 interrupt-controller; 1568 #interrupt-cells = <0x2>; 1569 }; 1570 1571 gpio4: gpio4@ff790000 { 1572 compatible = "rockchip,gpio-bank"; 1573 reg = <0x0 0xff790000 0x0 0x100>; 1574 clocks = <&cru PCLK_GPIO4>; 1575 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1576 1577 gpio-controller; 1578 #gpio-cells = <0x2>; 1579 1580 interrupt-controller; 1581 #interrupt-cells = <0x2>; 1582 }; 1583 1584 pcfg_pull_up: pcfg-pull-up { 1585 bias-pull-up; 1586 }; 1587 1588 pcfg_pull_down: pcfg-pull-down { 1589 bias-pull-down; 1590 }; 1591 1592 pcfg_pull_none: pcfg-pull-none { 1593 bias-disable; 1594 }; 1595 1596 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1597 bias-disable; 1598 drive-strength = <12>; 1599 }; 1600 1601 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1602 bias-pull-up; 1603 drive-strength = <8>; 1604 }; 1605 1606 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1607 bias-pull-down; 1608 drive-strength = <4>; 1609 }; 1610 1611 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1612 bias-pull-up; 1613 drive-strength = <2>; 1614 }; 1615 1616 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1617 bias-pull-down; 1618 drive-strength = <12>; 1619 }; 1620 1621 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1622 bias-disable; 1623 drive-strength = <13>; 1624 }; 1625 1626 clock { 1627 clk_32k: clk-32k { 1628 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; 1629 }; 1630 }; 1631 1632 edp { 1633 edp_hpd: edp-hpd { 1634 rockchip,pins = 1635 <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1636 }; 1637 }; 1638 1639 gmac { 1640 rgmii_pins: rgmii-pins { 1641 rockchip,pins = 1642 /* mac_txclk */ 1643 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1644 /* mac_rxclk */ 1645 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1646 /* mac_mdio */ 1647 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1648 /* mac_txen */ 1649 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1650 /* mac_clk */ 1651 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1652 /* mac_rxdv */ 1653 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1654 /* mac_mdc */ 1655 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1656 /* mac_rxd1 */ 1657 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1658 /* mac_rxd0 */ 1659 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1660 /* mac_txd1 */ 1661 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1662 /* mac_txd0 */ 1663 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1664 /* mac_rxd3 */ 1665 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1666 /* mac_rxd2 */ 1667 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1668 /* mac_txd3 */ 1669 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1670 /* mac_txd2 */ 1671 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; 1672 }; 1673 1674 rmii_pins: rmii-pins { 1675 rockchip,pins = 1676 /* mac_mdio */ 1677 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1678 /* mac_txen */ 1679 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1680 /* mac_clk */ 1681 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1682 /* mac_rxer */ 1683 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1684 /* mac_rxdv */ 1685 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1686 /* mac_mdc */ 1687 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1688 /* mac_rxd1 */ 1689 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1690 /* mac_rxd0 */ 1691 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1692 /* mac_txd1 */ 1693 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 1694 /* mac_txd0 */ 1695 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; 1696 }; 1697 }; 1698 1699 i2c0 { 1700 i2c0_xfer: i2c0-xfer { 1701 rockchip,pins = 1702 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 1703 <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 1704 }; 1705 }; 1706 1707 i2c1 { 1708 i2c1_xfer: i2c1-xfer { 1709 rockchip,pins = 1710 <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1711 <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1712 }; 1713 }; 1714 1715 i2c2 { 1716 i2c2_xfer: i2c2-xfer { 1717 rockchip,pins = 1718 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 1719 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; 1720 }; 1721 }; 1722 1723 i2c3 { 1724 i2c3_xfer: i2c3-xfer { 1725 rockchip,pins = 1726 <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1727 <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 1728 }; 1729 }; 1730 1731 i2c4 { 1732 i2c4_xfer: i2c4-xfer { 1733 rockchip,pins = 1734 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1735 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 1736 }; 1737 }; 1738 1739 i2c5 { 1740 i2c5_xfer: i2c5-xfer { 1741 rockchip,pins = 1742 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, 1743 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 1744 }; 1745 }; 1746 1747 i2c6 { 1748 i2c6_xfer: i2c6-xfer { 1749 rockchip,pins = 1750 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, 1751 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 1752 }; 1753 }; 1754 1755 i2c7 { 1756 i2c7_xfer: i2c7-xfer { 1757 rockchip,pins = 1758 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, 1759 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 1760 }; 1761 }; 1762 1763 i2c8 { 1764 i2c8_xfer: i2c8-xfer { 1765 rockchip,pins = 1766 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, 1767 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 1768 }; 1769 }; 1770 1771 i2s0 { 1772 i2s0_8ch_bus: i2s0-8ch-bus { 1773 rockchip,pins = 1774 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, 1775 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 1776 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 1777 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, 1778 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, 1779 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, 1780 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, 1781 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, 1782 <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 1783 }; 1784 }; 1785 1786 i2s1 { 1787 i2s1_2ch_bus: i2s1-2ch-bus { 1788 rockchip,pins = 1789 <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1790 <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1791 <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1792 <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1793 <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 1794 }; 1795 }; 1796 1797 sdio0 { 1798 sdio0_bus1: sdio0-bus1 { 1799 rockchip,pins = 1800 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 1801 }; 1802 1803 sdio0_bus4: sdio0-bus4 { 1804 rockchip,pins = 1805 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 1806 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 1807 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 1808 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 1809 }; 1810 1811 sdio0_cmd: sdio0-cmd { 1812 rockchip,pins = 1813 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 1814 }; 1815 1816 sdio0_clk: sdio0-clk { 1817 rockchip,pins = 1818 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 1819 }; 1820 1821 sdio0_cd: sdio0-cd { 1822 rockchip,pins = 1823 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 1824 }; 1825 1826 sdio0_pwr: sdio0-pwr { 1827 rockchip,pins = 1828 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 1829 }; 1830 1831 sdio0_bkpwr: sdio0-bkpwr { 1832 rockchip,pins = 1833 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 1834 }; 1835 1836 sdio0_wp: sdio0-wp { 1837 rockchip,pins = 1838 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 1839 }; 1840 1841 sdio0_int: sdio0-int { 1842 rockchip,pins = 1843 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 1844 }; 1845 }; 1846 1847 sdmmc { 1848 sdmmc_bus1: sdmmc-bus1 { 1849 rockchip,pins = 1850 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1851 }; 1852 1853 sdmmc_bus4: sdmmc-bus4 { 1854 rockchip,pins = 1855 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 1856 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 1857 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 1858 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1859 }; 1860 1861 sdmmc_clk: sdmmc-clk { 1862 rockchip,pins = 1863 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 1864 }; 1865 1866 sdmmc_cmd: sdmmc-cmd { 1867 rockchip,pins = 1868 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 1869 }; 1870 1871 sdmmc_cd: sdmcc-cd { 1872 rockchip,pins = 1873 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 1874 }; 1875 1876 sdmmc_wp: sdmmc-wp { 1877 rockchip,pins = 1878 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 1879 }; 1880 }; 1881 1882 sleep { 1883 ap_pwroff: ap-pwroff { 1884 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 1885 }; 1886 1887 ddrio_pwroff: ddrio-pwroff { 1888 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 1889 }; 1890 }; 1891 1892 spdif { 1893 spdif_bus: spdif-bus { 1894 rockchip,pins = 1895 <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1896 }; 1897 1898 spdif_bus_1: spdif-bus-1 { 1899 rockchip,pins = 1900 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 1901 }; 1902 }; 1903 1904 spi0 { 1905 spi0_clk: spi0-clk { 1906 rockchip,pins = 1907 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; 1908 }; 1909 spi0_cs0: spi0-cs0 { 1910 rockchip,pins = 1911 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 1912 }; 1913 spi0_cs1: spi0-cs1 { 1914 rockchip,pins = 1915 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 1916 }; 1917 spi0_tx: spi0-tx { 1918 rockchip,pins = 1919 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; 1920 }; 1921 spi0_rx: spi0-rx { 1922 rockchip,pins = 1923 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; 1924 }; 1925 }; 1926 1927 spi1 { 1928 spi1_clk: spi1-clk { 1929 rockchip,pins = 1930 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; 1931 }; 1932 spi1_cs0: spi1-cs0 { 1933 rockchip,pins = 1934 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; 1935 }; 1936 spi1_rx: spi1-rx { 1937 rockchip,pins = 1938 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 1939 }; 1940 spi1_tx: spi1-tx { 1941 rockchip,pins = 1942 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 1943 }; 1944 }; 1945 1946 spi2 { 1947 spi2_clk: spi2-clk { 1948 rockchip,pins = 1949 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 1950 }; 1951 spi2_cs0: spi2-cs0 { 1952 rockchip,pins = 1953 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; 1954 }; 1955 spi2_rx: spi2-rx { 1956 rockchip,pins = 1957 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; 1958 }; 1959 spi2_tx: spi2-tx { 1960 rockchip,pins = 1961 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; 1962 }; 1963 }; 1964 1965 spi3 { 1966 spi3_clk: spi3-clk { 1967 rockchip,pins = 1968 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; 1969 }; 1970 spi3_cs0: spi3-cs0 { 1971 rockchip,pins = 1972 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; 1973 }; 1974 spi3_rx: spi3-rx { 1975 rockchip,pins = 1976 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; 1977 }; 1978 spi3_tx: spi3-tx { 1979 rockchip,pins = 1980 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; 1981 }; 1982 }; 1983 1984 spi4 { 1985 spi4_clk: spi4-clk { 1986 rockchip,pins = 1987 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; 1988 }; 1989 spi4_cs0: spi4-cs0 { 1990 rockchip,pins = 1991 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; 1992 }; 1993 spi4_rx: spi4-rx { 1994 rockchip,pins = 1995 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; 1996 }; 1997 spi4_tx: spi4-tx { 1998 rockchip,pins = 1999 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; 2000 }; 2001 }; 2002 2003 spi5 { 2004 spi5_clk: spi5-clk { 2005 rockchip,pins = 2006 <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; 2007 }; 2008 spi5_cs0: spi5-cs0 { 2009 rockchip,pins = 2010 <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; 2011 }; 2012 spi5_rx: spi5-rx { 2013 rockchip,pins = 2014 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; 2015 }; 2016 spi5_tx: spi5-tx { 2017 rockchip,pins = 2018 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; 2019 }; 2020 }; 2021 2022 tsadc { 2023 otp_gpio: otp-gpio { 2024 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2025 }; 2026 2027 otp_out: otp-out { 2028 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2029 }; 2030 }; 2031 2032 uart0 { 2033 uart0_xfer: uart0-xfer { 2034 rockchip,pins = 2035 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, 2036 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2037 }; 2038 2039 uart0_cts: uart0-cts { 2040 rockchip,pins = 2041 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2042 }; 2043 2044 uart0_rts: uart0-rts { 2045 rockchip,pins = 2046 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2047 }; 2048 }; 2049 2050 uart1 { 2051 uart1_xfer: uart1-xfer { 2052 rockchip,pins = 2053 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 2054 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 2055 }; 2056 }; 2057 2058 uart2a { 2059 uart2a_xfer: uart2a-xfer { 2060 rockchip,pins = 2061 <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, 2062 <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2063 }; 2064 }; 2065 2066 uart2b { 2067 uart2b_xfer: uart2b-xfer { 2068 rockchip,pins = 2069 <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 2070 <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 2071 }; 2072 }; 2073 2074 uart2c { 2075 uart2c_xfer: uart2c-xfer { 2076 rockchip,pins = 2077 <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, 2078 <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 2079 }; 2080 }; 2081 2082 uart3 { 2083 uart3_xfer: uart3-xfer { 2084 rockchip,pins = 2085 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 2086 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 2087 }; 2088 2089 uart3_cts: uart3-cts { 2090 rockchip,pins = 2091 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2092 }; 2093 2094 uart3_rts: uart3-rts { 2095 rockchip,pins = 2096 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 2097 }; 2098 }; 2099 2100 uart4 { 2101 uart4_xfer: uart4-xfer { 2102 rockchip,pins = 2103 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, 2104 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 2105 }; 2106 }; 2107 2108 uarthdcp { 2109 uarthdcp_xfer: uarthdcp-xfer { 2110 rockchip,pins = 2111 <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, 2112 <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 2113 }; 2114 }; 2115 2116 pwm0 { 2117 pwm0_pin: pwm0-pin { 2118 rockchip,pins = 2119 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2120 }; 2121 2122 vop0_pwm_pin: vop0-pwm-pin { 2123 rockchip,pins = 2124 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2125 }; 2126 }; 2127 2128 pwm1 { 2129 pwm1_pin: pwm1-pin { 2130 rockchip,pins = 2131 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2132 }; 2133 2134 vop1_pwm_pin: vop1-pwm-pin { 2135 rockchip,pins = 2136 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2137 }; 2138 }; 2139 2140 pwm2 { 2141 pwm2_pin: pwm2-pin { 2142 rockchip,pins = 2143 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2144 }; 2145 }; 2146 2147 pwm3a { 2148 pwm3a_pin: pwm3a-pin { 2149 rockchip,pins = 2150 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2151 }; 2152 }; 2153 2154 pwm3b { 2155 pwm3b_pin: pwm3b-pin { 2156 rockchip,pins = 2157 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2158 }; 2159 }; 2160 2161 hdmi { 2162 hdmi_i2c_xfer: hdmi-i2c-xfer { 2163 rockchip,pins = 2164 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2165 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2166 }; 2167 2168 hdmi_cec: hdmi-cec { 2169 rockchip,pins = 2170 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2171 }; 2172 }; 2173 2174 pcie { 2175 pcie_clkreqn: pci-clkreqn { 2176 rockchip,pins = 2177 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; 2178 }; 2179 2180 pcie_clkreqnb: pci-clkreqnb { 2181 rockchip,pins = 2182 <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 2183 }; 2184 2185 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2186 rockchip,pins = 2187 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2188 }; 2189 2190 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2191 rockchip,pins = 2192 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2193 }; 2194 }; 2195 2196 }; 2197}; 2198