1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru (and derivatives) board device tree source 4 * 5 * Copyright 2016-2017 Google, Inc 6 */ 7 8#include <dt-bindings/input/input.h> 9#include "rk3399.dtsi" 10#include "rk3399-op1-opp.dtsi" 11 12/ { 13 chosen { 14 u-boot,dm-pre-reloc; 15 stdout-path = "serial2:115200n8"; 16 u-boot,spl-boot-order = &spi_flash; 17 }; 18 19 config { 20 u-boot,spl-payload-offset = <0x40000>; 21 }; 22 23 /* 24 * Power Tree 25 * 26 * In general an attempt is made to include all rails called out by 27 * the schematic as long as those rails interact in some way with 28 * the AP. AKA: 29 * - Rails that only connect to the EC (or devices that the EC talks to) 30 * are not included. 31 * - Rails _are_ included if the rails go to the AP even if the AP 32 * doesn't currently care about them / they are always on. The idea 33 * here is that it makes it easier to map to the schematic or extend 34 * later. 35 * 36 * If two rails are substantially the same from the AP's point of 37 * view, though, we won't create a full fixed regulator. We'll just 38 * put the child rail as an alias of the parent rail. Sometimes rails 39 * look the same to the AP because one of these is true: 40 * - The EC controls the enable and the EC always enables a rail as 41 * long as the AP is running. 42 * - The rails are actually connected to each other by a jumper and 43 * the distinction is just there to add clarity/flexibility to the 44 * schematic. 45 */ 46 47 ppvar_sys: ppvar-sys { 48 compatible = "regulator-fixed"; 49 regulator-name = "ppvar_sys"; 50 regulator-always-on; 51 regulator-boot-on; 52 }; 53 54 pp1200_lpddr: pp1200-lpddr { 55 compatible = "regulator-fixed"; 56 regulator-name = "pp1200_lpddr"; 57 58 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 59 regulator-always-on; 60 regulator-boot-on; 61 regulator-min-microvolt = <1200000>; 62 regulator-max-microvolt = <1200000>; 63 64 vin-supply = <&ppvar_sys>; 65 }; 66 67 pp1800: pp1800 { 68 compatible = "regulator-fixed"; 69 regulator-name = "pp1800"; 70 71 /* Always on when ppvar_sys shows power good */ 72 regulator-always-on; 73 regulator-boot-on; 74 regulator-min-microvolt = <1800000>; 75 regulator-max-microvolt = <1800000>; 76 77 vin-supply = <&ppvar_sys>; 78 }; 79 80 pp3300: pp3300 { 81 compatible = "regulator-fixed"; 82 regulator-name = "pp3300"; 83 84 /* Always on; plain and simple */ 85 regulator-always-on; 86 regulator-boot-on; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 90 vin-supply = <&ppvar_sys>; 91 }; 92 93 pp5000: pp5000 { 94 compatible = "regulator-fixed"; 95 regulator-name = "pp5000"; 96 97 /* EC turns on w/ pp5000_en; always on for AP */ 98 regulator-always-on; 99 regulator-boot-on; 100 regulator-min-microvolt = <5000000>; 101 regulator-max-microvolt = <5000000>; 102 103 vin-supply = <&ppvar_sys>; 104 }; 105 106 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { 107 compatible = "pwm-regulator"; 108 regulator-name = "ppvar_bigcpu_pwm"; 109 110 pwms = <&pwm1 0 3337 0>; 111 pwm-supply = <&ppvar_sys>; 112 pwm-dutycycle-range = <100 0>; 113 pwm-dutycycle-unit = <100>; 114 115 /* EC turns on w/ ap_core_en; always on for AP */ 116 regulator-always-on; 117 regulator-boot-on; 118 regulator-min-microvolt = <800107>; 119 regulator-max-microvolt = <1302232>; 120 }; 121 122 ppvar_bigcpu: ppvar-bigcpu { 123 compatible = "vctrl-regulator"; 124 regulator-name = "ppvar_bigcpu"; 125 126 regulator-min-microvolt = <800107>; 127 regulator-max-microvolt = <1302232>; 128 129 ctrl-supply = <&ppvar_bigcpu_pwm>; 130 ctrl-voltage-range = <800107 1302232>; 131 132 regulator-settling-time-up-us = <322>; 133 }; 134 135 ppvar_litcpu_pwm: ppvar-litcpu-pwm { 136 compatible = "pwm-regulator"; 137 regulator-name = "ppvar_litcpu_pwm"; 138 139 pwms = <&pwm2 0 3337 0>; 140 pwm-supply = <&ppvar_sys>; 141 pwm-dutycycle-range = <100 0>; 142 pwm-dutycycle-unit = <100>; 143 144 /* EC turns on w/ ap_core_en; always on for AP */ 145 regulator-always-on; 146 regulator-boot-on; 147 regulator-min-microvolt = <797743>; 148 regulator-max-microvolt = <1307837>; 149 }; 150 151 ppvar_litcpu: ppvar-litcpu { 152 compatible = "vctrl-regulator"; 153 regulator-name = "ppvar_litcpu"; 154 155 regulator-min-microvolt = <797743>; 156 regulator-max-microvolt = <1307837>; 157 158 ctrl-supply = <&ppvar_litcpu_pwm>; 159 ctrl-voltage-range = <797743 1307837>; 160 161 regulator-settling-time-up-us = <384>; 162 }; 163 164 ppvar_gpu_pwm: ppvar-gpu-pwm { 165 compatible = "pwm-regulator"; 166 regulator-name = "ppvar_gpu_pwm"; 167 168 pwms = <&pwm0 0 3337 0>; 169 pwm-supply = <&ppvar_sys>; 170 pwm-dutycycle-range = <100 0>; 171 pwm-dutycycle-unit = <100>; 172 173 /* EC turns on w/ ap_core_en; always on for AP */ 174 regulator-always-on; 175 regulator-boot-on; 176 regulator-min-microvolt = <786384>; 177 regulator-max-microvolt = <1217747>; 178 }; 179 180 ppvar_gpu: ppvar-gpu { 181 compatible = "vctrl-regulator"; 182 regulator-name = "ppvar_gpu"; 183 184 regulator-min-microvolt = <786384>; 185 regulator-max-microvolt = <1217747>; 186 187 ctrl-supply = <&ppvar_gpu_pwm>; 188 ctrl-voltage-range = <786384 1217747>; 189 190 regulator-settling-time-up-us = <390>; 191 }; 192 193 /* EC turns on w/ pp900_ddrpll_en */ 194 pp900_ddrpll: pp900-ap { 195 }; 196 197 /* EC turns on w/ pp900_pll_en */ 198 pp900_pll: pp900-ap { 199 }; 200 201 /* EC turns on w/ pp900_pmu_en */ 202 pp900_pmu: pp900-ap { 203 }; 204 205 /* EC turns on w/ pp1800_s0_en_l */ 206 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { 207 }; 208 209 /* EC turns on w/ pp1800_avdd_en_l */ 210 pp1800_avdd: pp1800 { 211 }; 212 213 /* EC turns on w/ pp1800_lid_en_l */ 214 pp1800_lid: pp1800_mic: pp1800 { 215 }; 216 217 /* EC turns on w/ lpddr_pwr_en */ 218 pp1800_lpddr: pp1800 { 219 }; 220 221 /* EC turns on w/ pp1800_pmu_en_l */ 222 pp1800_pmu: pp1800 { 223 }; 224 225 /* EC turns on w/ pp1800_usb_en_l */ 226 pp1800_usb: pp1800 { 227 }; 228 229 pp3000_sd_slot: pp3000-sd-slot { 230 compatible = "regulator-fixed"; 231 regulator-name = "pp3000_sd_slot"; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&sd_slot_pwr_en>; 234 235 enable-active-high; 236 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 237 238 vin-supply = <&pp3000>; 239 }; 240 241 /* 242 * Technically, this is a small abuse of 'regulator-gpio'; this 243 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 244 * always on though, so it is sufficient to simply control the mux 245 * here. 246 */ 247 ppvar_sd_card_io: ppvar-sd-card-io { 248 compatible = "regulator-gpio"; 249 regulator-name = "ppvar_sd_card_io"; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 252 253 enable-active-high; 254 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 255 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 256 states = <1800000 0x1 257 3000000 0x0>; 258 259 regulator-min-microvolt = <1800000>; 260 regulator-max-microvolt = <3000000>; 261 }; 262 263 /* EC turns on w/ pp3300_trackpad_en_l */ 264 pp3300_trackpad: pp3300-trackpad { 265 }; 266 267 /* EC turns on w/ usb_a_en */ 268 pp5000_usb_a_vbus: pp5000 { 269 }; 270 271 gpio_keys: gpio-keys { 272 compatible = "gpio-keys"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&bt_host_wake_l>; 275 276 wake_on_bt: wake-on-bt { 277 label = "Wake-on-Bluetooth"; 278 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 279 linux,code = <KEY_WAKEUP>; 280 wakeup-source; 281 }; 282 }; 283 284 max98357a: max98357a { 285 compatible = "maxim,max98357a"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&sdmode_en>; 288 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 289 sdmode-delay = <2>; 290 #sound-dai-cells = <0>; 291 status = "okay"; 292 }; 293 294 sound: sound { 295 compatible = "rockchip,rk3399-gru-sound"; 296 rockchip,cpu = <&i2s0 &i2s2>; 297 }; 298}; 299 300&cdn_dp { 301 status = "okay"; 302}; 303 304/* 305 * Set some suspend operating points to avoid OVP in suspend 306 * 307 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 308 * from wherever they're at back to the "default" operating point (whatever 309 * voltage we get when we set the PWM pins to "input"). 310 * 311 * This quick transition under light load has the possibility to trigger the 312 * regulator "over voltage protection" (OVP). 313 * 314 * To make extra certain that we don't hit this OVP at suspend time, we'll 315 * transition to a voltage that's much closer to the default (~1.0 V) so that 316 * there will not be a big jump. Technically we only need to get within 200 mV 317 * of the default voltage, but the speed here should be fast enough and we need 318 * suspend/resume to be rock solid. 319 */ 320 321&cluster0_opp { 322 opp05 { 323 opp-suspend; 324 }; 325}; 326 327&cluster1_opp { 328 opp06 { 329 opp-suspend; 330 }; 331}; 332 333&cpu_l0 { 334 cpu-supply = <&ppvar_litcpu>; 335}; 336 337&cpu_l1 { 338 cpu-supply = <&ppvar_litcpu>; 339}; 340 341&cpu_l2 { 342 cpu-supply = <&ppvar_litcpu>; 343}; 344 345&cpu_l3 { 346 cpu-supply = <&ppvar_litcpu>; 347}; 348 349&cpu_b0 { 350 cpu-supply = <&ppvar_bigcpu>; 351}; 352 353&cpu_b1 { 354 cpu-supply = <&ppvar_bigcpu>; 355}; 356 357&cru { 358 assigned-clocks = 359 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 360 <&cru PLL_NPLL>, 361 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 362 <&cru PCLK_PERIHP>, 363 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 364 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 365 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 366 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 367 <&cru ACLK_GIC_PRE>, 368 <&cru PCLK_DDR>; 369 assigned-clock-rates = 370 <600000000>, <800000000>, 371 <1000000000>, 372 <150000000>, <75000000>, 373 <37500000>, 374 <100000000>, <100000000>, 375 <50000000>, <800000000>, 376 <100000000>, <50000000>, 377 <400000000>, <400000000>, 378 <200000000>, 379 <200000000>; 380}; 381 382&emmc_phy { 383 status = "okay"; 384}; 385 386&gpu { 387 mali-supply = <&ppvar_gpu>; 388 status = "okay"; 389}; 390 391ap_i2c_ts: &i2c3 { 392 status = "okay"; 393 394 clock-frequency = <400000>; 395 396 /* These are relatively safe rise/fall times */ 397 i2c-scl-falling-time-ns = <50>; 398 i2c-scl-rising-time-ns = <300>; 399}; 400 401ap_i2c_audio: &i2c8 { 402 status = "okay"; 403 404 clock-frequency = <400000>; 405 406 /* These are relatively safe rise/fall times */ 407 i2c-scl-falling-time-ns = <50>; 408 i2c-scl-rising-time-ns = <300>; 409 410 codec: da7219@1a { 411 compatible = "dlg,da7219"; 412 reg = <0x1a>; 413 interrupt-parent = <&gpio1>; 414 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 415 clocks = <&cru SCLK_I2S_8CH_OUT>; 416 clock-names = "mclk"; 417 dlg,micbias-lvl = <2600>; 418 dlg,mic-amp-in-sel = "diff"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&headset_int_l>; 421 VDD-supply = <&pp1800>; 422 VDDMIC-supply = <&pp3300>; 423 VDDIO-supply = <&pp1800>; 424 425 da7219_aad { 426 dlg,adc-1bit-rpt = <1>; 427 dlg,btn-avg = <4>; 428 dlg,btn-cfg = <50>; 429 dlg,mic-det-thr = <500>; 430 dlg,jack-ins-deb = <20>; 431 dlg,jack-det-rate = "32ms_64ms"; 432 dlg,jack-rem-deb = <1>; 433 434 dlg,a-d-btn-thr = <0xa>; 435 dlg,d-b-btn-thr = <0x16>; 436 dlg,b-c-btn-thr = <0x21>; 437 dlg,c-mic-btn-thr = <0x3E>; 438 }; 439 }; 440}; 441 442&i2s0 { 443 status = "okay"; 444}; 445 446&i2s2 { 447 status = "okay"; 448}; 449 450&io_domains { 451 status = "okay"; 452 453 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 454 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 455 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 456 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 457}; 458 459&pcie0 { 460 status = "okay"; 461 462 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 465 vpcie3v3-supply = <&pp3300_wifi_bt>; 466 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 467 vpcie0v9-supply = <&pp900_pcie>; 468 469 pci_rootport: pcie@0,0 { 470 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; 471 #address-cells = <3>; 472 #size-cells = <2>; 473 ranges; 474 }; 475}; 476 477&pcie_phy { 478 status = "okay"; 479}; 480 481&pmu_io_domains { 482 status = "okay"; 483 484 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 485}; 486 487&pwm0 { 488 status = "okay"; 489}; 490 491&pwm1 { 492 status = "okay"; 493}; 494 495&pwm2 { 496 status = "okay"; 497}; 498 499&pwm3 { 500 status = "okay"; 501}; 502 503&sdhci { 504 /* 505 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 506 * same (or nearly the same) performance for all eMMC that are intended 507 * to be used. 508 */ 509 assigned-clock-rates = <150000000>; 510 511 bus-width = <8>; 512 mmc-hs400-1_8v; 513 mmc-hs400-enhanced-strobe; 514 non-removable; 515 status = "okay"; 516}; 517 518&sdmmc { 519 status = "okay"; 520 521 /* 522 * Note: configure "sdmmc_cd" as card detect even though it's actually 523 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 524 * should be ignoring card detect anyway. Specifying the pin as 525 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 526 * turned on that the system will still make sure the port is 527 * configured as SDMMC and not JTAG. 528 */ 529 pinctrl-names = "default"; 530 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio 531 &sdmmc_bus4>; 532 533 bus-width = <4>; 534 cap-mmc-highspeed; 535 cap-sd-highspeed; 536 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 537 disable-wp; 538 sd-uhs-sdr12; 539 sd-uhs-sdr25; 540 sd-uhs-sdr50; 541 sd-uhs-sdr104; 542 vmmc-supply = <&pp3000_sd_slot>; 543 vqmmc-supply = <&ppvar_sd_card_io>; 544}; 545 546&spi1 { 547 status = "okay"; 548 u-boot,dm-pre-reloc; 549 550 pinctrl-names = "default", "sleep"; 551 pinctrl-1 = <&spi1_sleep>; 552 553 spi_flash: spiflash@0 { 554 u-boot,dm-pre-reloc; 555 compatible = "jedec,spi-nor", "spi-flash"; 556 reg = <0>; 557 558 /* May run faster once verified. */ 559 spi-max-frequency = <10000000>; 560 }; 561}; 562 563&spi2 { 564 status = "okay"; 565}; 566 567&spi5 { 568 status = "okay"; 569 spi-activate-delay = <100>; 570 spi-max-frequency = <3000000>; 571 spi-deactivate-delay = <200>; 572 573 cros_ec: ec@0 { 574 compatible = "google,cros-ec-spi"; 575 reg = <0>; 576 interrupt-parent = <&gpio0>; 577 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 578 ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&ec_ap_int_l>; 581 spi-max-frequency = <3000000>; 582 583 i2c_tunnel: i2c-tunnel { 584 compatible = "google,cros-ec-i2c-tunnel"; 585 google,remote-bus = <4>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 590 usbc_extcon0: extcon@0 { 591 compatible = "google,extcon-usbc-cros-ec"; 592 google,usb-port-id = <0>; 593 594 #extcon-cells = <0>; 595 }; 596 }; 597}; 598 599&tsadc { 600 status = "okay"; 601 602 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 603 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 604}; 605 606&tcphy0 { 607 status = "okay"; 608 extcon = <&usbc_extcon0>; 609}; 610 611&u2phy0 { 612 status = "okay"; 613}; 614 615&u2phy0_host { 616 status = "okay"; 617}; 618 619&u2phy1_host { 620 status = "okay"; 621}; 622 623&u2phy0_otg { 624 status = "okay"; 625}; 626 627&u2phy1_otg { 628 status = "okay"; 629}; 630 631&uart2 { 632 status = "okay"; 633 u-boot,dm-pre-reloc; 634}; 635 636&usb_host0_ohci { 637 status = "okay"; 638}; 639 640&usbdrd3_0 { 641 status = "okay"; 642 extcon = <&usbc_extcon0>; 643}; 644 645&usbdrd_dwc3_0 { 646 status = "okay"; 647 dr_mode = "host"; 648}; 649 650&vopb { 651 status = "okay"; 652}; 653 654&vopb_mmu { 655 status = "okay"; 656}; 657 658&vopl { 659 status = "okay"; 660}; 661 662&vopl_mmu { 663 status = "okay"; 664}; 665 666#include <cros-ec-keyboard.dtsi> 667#include <cros-ec-sbs.dtsi> 668 669&pinctrl { 670 /* 671 * pinctrl settings for pins that have no real owners. 672 * 673 * At the moment settings are identical for S0 and S3, but if we later 674 * need to configure things differently for S3 we'll adjust here. 675 */ 676 pinctrl-names = "default"; 677 pinctrl-0 = < 678 &ap_pwroff /* AP will auto-assert this when in S3 */ 679 &clk_32k /* This pin is always 32k on gru boards */ 680 >; 681 682 pcfg_output_low: pcfg-output-low { 683 output-low; 684 }; 685 686 pcfg_output_high: pcfg-output-high { 687 output-high; 688 }; 689 690 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 691 bias-disable; 692 drive-strength = <8>; 693 }; 694 695 backlight-enable { 696 bl_en: bl-en { 697 rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; 698 }; 699 }; 700 701 cros-ec { 702 ec_ap_int_l: ec-ap-int-l { 703 rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>; 704 }; 705 }; 706 707 discrete-regulators { 708 sd_io_pwr_en: sd-io-pwr-en { 709 rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO 710 &pcfg_pull_none>; 711 }; 712 713 sd_pwr_1800_sel: sd-pwr-1800-sel { 714 rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO 715 &pcfg_pull_none>; 716 }; 717 718 sd_slot_pwr_en: sd-slot-pwr-en { 719 rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO 720 &pcfg_pull_none>; 721 }; 722 }; 723 724 codec { 725 /* Has external pullup */ 726 headset_int_l: headset-int-l { 727 rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; 728 }; 729 730 mic_int: mic-int { 731 rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; 732 }; 733 }; 734 735 max98357a { 736 sdmode_en: sdmode-en { 737 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; 738 }; 739 }; 740 741 pcie { 742 pcie_clkreqn_cpm: pci-clkreqn-cpm { 743 /* 744 * Since our pcie doesn't support ClockPM(CPM), we want 745 * to hack this as gpio, so the EP could be able to 746 * de-assert it along and make ClockPM(CPM) work. 747 */ 748 rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; 749 }; 750 }; 751 752 sdmmc { 753 /* 754 * We run sdmmc at max speed; bump up drive strength. 755 * We also have external pulls, so disable the internal ones. 756 */ 757 sdmmc_bus4: sdmmc-bus4 { 758 rockchip,pins = 759 <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, 760 <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, 761 <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, 762 <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; 763 }; 764 765 sdmmc_clk: sdmmc-clk { 766 rockchip,pins = 767 <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 768 }; 769 770 sdmmc_cmd: sdmmc-cmd { 771 rockchip,pins = 772 <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; 773 }; 774 775 /* 776 * In our case the official card detect is hooked to ground 777 * to avoid getting access to JTAG just by sticking something 778 * in the SD card slot (see the force_jtag bit in the TRM). 779 * 780 * We still configure it as card detect because it doesn't 781 * hurt and dw_mmc will ignore it. We make sure to disable 782 * the pull though so we don't burn needless power. 783 */ 784 sdmmc_cd: sdmmc-cd { 785 rockchip,pins = 786 <0 7 RK_FUNC_1 &pcfg_pull_none>; 787 }; 788 789 /* This is where we actually hook up CD; has external pull */ 790 sdmmc_cd_gpio: sdmmc-cd-gpio { 791 rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; 792 }; 793 }; 794 795 spi1 { 796 spi1_sleep: spi1-sleep { 797 /* 798 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 799 * prevent leakage. 800 */ 801 rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, 802 <1 10 RK_FUNC_GPIO &pcfg_pull_down>, 803 <1 7 RK_FUNC_GPIO &pcfg_pull_down>, 804 <1 8 RK_FUNC_GPIO &pcfg_pull_down>; 805 }; 806 }; 807 808 touchscreen { 809 touch_int_l: touch-int-l { 810 rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; 811 }; 812 813 touch_reset_l: touch-reset-l { 814 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; 815 }; 816 }; 817 818 trackpad { 819 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 820 rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; 821 }; 822 823 trackpad_int_l: trackpad-int-l { 824 rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; 825 }; 826 }; 827 828 wifi: wifi { 829 wlan_module_reset_l: wlan-module-reset-l { 830 rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; 831 }; 832 833 bt_host_wake_l: bt-host-wake-l { 834 /* Kevin has an external pull up, but Gru does not */ 835 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 836 }; 837 }; 838 839 write-protect { 840 ap_fw_wp: ap-fw-wp { 841 rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; 842 }; 843 }; 844}; 845