1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Collabora Ltd. 4 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 5 * 6 * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw 7 */ 8 9/dts-v1/; 10#include "rk3399-rock960.dtsi" 11#include "rk3399-sdram-ddr3-1600.dtsi" 12 13/ { 14 model = "96boards RK3399 Ficus"; 15 compatible = "vamrs,ficus", "rockchip,rk3399"; 16 17 chosen { 18 stdout-path = "serial2:1500000n8"; 19 }; 20 21 clkin_gmac: external-gmac-clock { 22 compatible = "fixed-clock"; 23 clock-frequency = <125000000>; 24 clock-output-names = "clkin_gmac"; 25 #clock-cells = <0>; 26 }; 27}; 28 29&gmac { 30 assigned-clocks = <&cru SCLK_RMII_SRC>; 31 assigned-clock-parents = <&clkin_gmac>; 32 clock_in_out = "input"; 33 phy-supply = <&vcc3v3_sys>; 34 phy-mode = "rgmii"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&rgmii_pins>; 37 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 38 snps,reset-active-low; 39 snps,reset-delays-us = <0 10000 50000>; 40 tx_delay = <0x28>; 41 rx_delay = <0x11>; 42 status = "okay"; 43}; 44 45&pcie0 { 46 ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; 47}; 48 49&pinctrl { 50 gmac { 51 rgmii_sleep_pins: rgmii-sleep-pins { 52 rockchip,pins = 53 <3 15 RK_FUNC_GPIO &pcfg_output_low>; 54 }; 55 }; 56 57 pcie { 58 pcie_drv: pcie-drv { 59 rockchip,pins = 60 <1 24 RK_FUNC_GPIO &pcfg_pull_none>; 61 }; 62 }; 63 64 usb2 { 65 host_vbus_drv: host-vbus-drv { 66 rockchip,pins = 67 <4 27 RK_FUNC_GPIO &pcfg_pull_none>; 68 }; 69 }; 70}; 71 72&vcc3v3_pcie { 73 gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; 74}; 75 76&vcc5v0_host { 77 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 78}; 79