1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3368-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/thermal/thermal.h> 49 50/ { 51 compatible = "rockchip,rk3368"; 52 interrupt-parent = <&gic>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 56 aliases { 57 ethernet0 = &gmac; 58 i2c0 = &i2c0; 59 i2c1 = &i2c1; 60 i2c2 = &i2c2; 61 i2c3 = &i2c3; 62 i2c4 = &i2c4; 63 i2c5 = &i2c5; 64 serial0 = &uart0; 65 serial1 = &uart1; 66 serial2 = &uart2; 67 serial3 = &uart3; 68 serial4 = &uart4; 69 spi0 = &spi0; 70 spi1 = &spi1; 71 spi2 = &spi2; 72 }; 73 74 cpus { 75 #address-cells = <0x2>; 76 #size-cells = <0x0>; 77 78 cpu-map { 79 cluster0 { 80 core0 { 81 cpu = <&cpu_b0>; 82 }; 83 core1 { 84 cpu = <&cpu_b1>; 85 }; 86 core2 { 87 cpu = <&cpu_b2>; 88 }; 89 core3 { 90 cpu = <&cpu_b3>; 91 }; 92 }; 93 94 cluster1 { 95 core0 { 96 cpu = <&cpu_l0>; 97 }; 98 core1 { 99 cpu = <&cpu_l1>; 100 }; 101 core2 { 102 cpu = <&cpu_l2>; 103 }; 104 core3 { 105 cpu = <&cpu_l3>; 106 }; 107 }; 108 }; 109 110 idle-states { 111 entry-method = "psci"; 112 113 cpu_sleep: cpu-sleep-0 { 114 compatible = "arm,idle-state"; 115 arm,psci-suspend-param = <0x1010000>; 116 entry-latency-us = <0x3fffffff>; 117 exit-latency-us = <0x40000000>; 118 min-residency-us = <0xffffffff>; 119 }; 120 }; 121 122 cpu_l0: cpu@0 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53", "arm,armv8"; 125 reg = <0x0 0x0>; 126 cpu-idle-states = <&cpu_sleep>; 127 enable-method = "psci"; 128 129 #cooling-cells = <2>; /* min followed by max */ 130 }; 131 132 cpu_l1: cpu@1 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53", "arm,armv8"; 135 reg = <0x0 0x1>; 136 cpu-idle-states = <&cpu_sleep>; 137 enable-method = "psci"; 138 }; 139 140 cpu_l2: cpu@2 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a53", "arm,armv8"; 143 reg = <0x0 0x2>; 144 cpu-idle-states = <&cpu_sleep>; 145 enable-method = "psci"; 146 }; 147 148 cpu_l3: cpu@3 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53", "arm,armv8"; 151 reg = <0x0 0x3>; 152 cpu-idle-states = <&cpu_sleep>; 153 enable-method = "psci"; 154 }; 155 156 cpu_b0: cpu@100 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a53", "arm,armv8"; 159 reg = <0x0 0x100>; 160 cpu-idle-states = <&cpu_sleep>; 161 enable-method = "psci"; 162 163 #cooling-cells = <2>; /* min followed by max */ 164 }; 165 166 cpu_b1: cpu@101 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53", "arm,armv8"; 169 reg = <0x0 0x101>; 170 cpu-idle-states = <&cpu_sleep>; 171 enable-method = "psci"; 172 }; 173 174 cpu_b2: cpu@102 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a53", "arm,armv8"; 177 reg = <0x0 0x102>; 178 cpu-idle-states = <&cpu_sleep>; 179 enable-method = "psci"; 180 }; 181 182 cpu_b3: cpu@103 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a53", "arm,armv8"; 185 reg = <0x0 0x103>; 186 cpu-idle-states = <&cpu_sleep>; 187 enable-method = "psci"; 188 }; 189 }; 190 191 arm-pmu { 192 compatible = "arm,armv8-pmuv3"; 193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 201 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 202 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 203 <&cpu_b2>, <&cpu_b3>; 204 }; 205 206 psci { 207 compatible = "arm,psci-0.2"; 208 method = "smc"; 209 }; 210 211 timer { 212 compatible = "arm,armv8-timer"; 213 interrupts = <GIC_PPI 13 214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 215 <GIC_PPI 14 216 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 217 <GIC_PPI 11 218 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 219 <GIC_PPI 10 220 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 221 }; 222 223 xin24m: oscillator { 224 compatible = "fixed-clock"; 225 clock-frequency = <24000000>; 226 clock-output-names = "xin24m"; 227 #clock-cells = <0>; 228 }; 229 230 sdmmc: dwmmc@ff0c0000 { 231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 232 reg = <0x0 0xff0c0000 0x0 0x4000>; 233 clock-freq-min-max = <400000 150000000>; 234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 237 fifo-depth = <0x100>; 238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 239 status = "disabled"; 240 }; 241 242 sdio0: dwmmc@ff0d0000 { 243 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 244 reg = <0x0 0xff0d0000 0x0 0x4000>; 245 clock-freq-min-max = <400000 150000000>; 246 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 247 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 248 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 249 fifo-depth = <0x100>; 250 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 251 status = "disabled"; 252 }; 253 254 emmc: dwmmc@ff0f0000 { 255 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 256 reg = <0x0 0xff0f0000 0x0 0x4000>; 257 clock-freq-min-max = <400000 150000000>; 258 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 259 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 261 fifo-depth = <0x100>; 262 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 263 status = "disabled"; 264 }; 265 266 saradc: saradc@ff100000 { 267 compatible = "rockchip,saradc"; 268 reg = <0x0 0xff100000 0x0 0x100>; 269 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 270 #io-channel-cells = <1>; 271 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 272 clock-names = "saradc", "apb_pclk"; 273 status = "disabled"; 274 }; 275 276 spi0: spi@ff110000 { 277 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 278 reg = <0x0 0xff110000 0x0 0x1000>; 279 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 280 clock-names = "spiclk", "apb_pclk"; 281 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 status = "disabled"; 287 }; 288 289 spi1: spi@ff120000 { 290 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 291 reg = <0x0 0xff120000 0x0 0x1000>; 292 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 293 clock-names = "spiclk", "apb_pclk"; 294 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 spi2: spi@ff130000 { 303 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 304 reg = <0x0 0xff130000 0x0 0x1000>; 305 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 306 clock-names = "spiclk", "apb_pclk"; 307 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 i2c1: i2c@ff140000 { 316 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 317 reg = <0x0 0xff140000 0x0 0x1000>; 318 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 clock-names = "i2c"; 322 clocks = <&cru PCLK_I2C1>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&i2c1_xfer>; 325 status = "disabled"; 326 }; 327 328 i2c3: i2c@ff150000 { 329 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 330 reg = <0x0 0xff150000 0x0 0x1000>; 331 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 clock-names = "i2c"; 335 clocks = <&cru PCLK_I2C3>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&i2c3_xfer>; 338 status = "disabled"; 339 }; 340 341 i2c4: i2c@ff160000 { 342 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 343 reg = <0x0 0xff160000 0x0 0x1000>; 344 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 clock-names = "i2c"; 348 clocks = <&cru PCLK_I2C4>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&i2c4_xfer>; 351 status = "disabled"; 352 }; 353 354 i2c5: i2c@ff170000 { 355 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 356 reg = <0x0 0xff170000 0x0 0x1000>; 357 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 clock-names = "i2c"; 361 clocks = <&cru PCLK_I2C5>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&i2c5_xfer>; 364 status = "disabled"; 365 }; 366 367 uart0: serial@ff180000 { 368 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 369 reg = <0x0 0xff180000 0x0 0x100>; 370 clock-frequency = <24000000>; 371 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 372 clock-names = "baudclk", "apb_pclk"; 373 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 374 reg-shift = <2>; 375 reg-io-width = <4>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&uart0_xfer>; 378 status = "disabled"; 379 }; 380 381 uart1: serial@ff190000 { 382 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 383 reg = <0x0 0xff190000 0x0 0x100>; 384 clock-frequency = <24000000>; 385 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 386 clock-names = "baudclk", "apb_pclk"; 387 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 388 reg-shift = <2>; 389 reg-io-width = <4>; 390 pinctrl-names = "default"; 391 pinctrl-1 = <&uart0_xfer>; 392 status = "disabled"; 393 }; 394 395 uart3: serial@ff1b0000 { 396 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 397 reg = <0x0 0xff1b0000 0x0 0x100>; 398 clock-frequency = <24000000>; 399 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 400 clock-names = "baudclk", "apb_pclk"; 401 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 402 reg-shift = <2>; 403 reg-io-width = <4>; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&uart3_xfer>; 406 status = "disabled"; 407 }; 408 409 uart4: serial@ff1c0000 { 410 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 411 reg = <0x0 0xff1c0000 0x0 0x100>; 412 clock-frequency = <24000000>; 413 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 414 clock-names = "baudclk", "apb_pclk"; 415 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 416 reg-shift = <2>; 417 reg-io-width = <4>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&uart4_xfer>; 420 status = "disabled"; 421 }; 422 423 thermal-zones { 424 cpu { 425 polling-delay-passive = <100>; /* milliseconds */ 426 polling-delay = <5000>; /* milliseconds */ 427 428 thermal-sensors = <&tsadc 0>; 429 430 trips { 431 cpu_alert0: cpu_alert0 { 432 temperature = <75000>; /* millicelsius */ 433 hysteresis = <2000>; /* millicelsius */ 434 type = "passive"; 435 }; 436 cpu_alert1: cpu_alert1 { 437 temperature = <80000>; /* millicelsius */ 438 hysteresis = <2000>; /* millicelsius */ 439 type = "passive"; 440 }; 441 cpu_crit: cpu_crit { 442 temperature = <95000>; /* millicelsius */ 443 hysteresis = <2000>; /* millicelsius */ 444 type = "critical"; 445 }; 446 }; 447 448 cooling-maps { 449 map0 { 450 trip = <&cpu_alert0>; 451 cooling-device = 452 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 453 }; 454 map1 { 455 trip = <&cpu_alert1>; 456 cooling-device = 457 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 458 }; 459 }; 460 }; 461 462 gpu { 463 polling-delay-passive = <100>; /* milliseconds */ 464 polling-delay = <5000>; /* milliseconds */ 465 466 thermal-sensors = <&tsadc 1>; 467 468 trips { 469 gpu_alert0: gpu_alert0 { 470 temperature = <80000>; /* millicelsius */ 471 hysteresis = <2000>; /* millicelsius */ 472 type = "passive"; 473 }; 474 gpu_crit: gpu_crit { 475 temperature = <115000>; /* millicelsius */ 476 hysteresis = <2000>; /* millicelsius */ 477 type = "critical"; 478 }; 479 }; 480 481 cooling-maps { 482 map0 { 483 trip = <&gpu_alert0>; 484 cooling-device = 485 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 486 }; 487 }; 488 }; 489 }; 490 491 tsadc: tsadc@ff280000 { 492 compatible = "rockchip,rk3368-tsadc"; 493 reg = <0x0 0xff280000 0x0 0x100>; 494 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 496 clock-names = "tsadc", "apb_pclk"; 497 resets = <&cru SRST_TSADC>; 498 reset-names = "tsadc-apb"; 499 pinctrl-names = "init", "default", "sleep"; 500 pinctrl-0 = <&otp_gpio>; 501 pinctrl-1 = <&otp_out>; 502 pinctrl-2 = <&otp_gpio>; 503 #thermal-sensor-cells = <1>; 504 rockchip,hw-tshut-temp = <95000>; 505 status = "disabled"; 506 }; 507 508 gmac: ethernet@ff290000 { 509 compatible = "rockchip,rk3368-gmac"; 510 reg = <0x0 0xff290000 0x0 0x10000>; 511 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 512 interrupt-names = "macirq"; 513 rockchip,grf = <&grf>; 514 clocks = <&cru SCLK_MAC>, 515 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 516 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 517 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 518 clock-names = "stmmaceth", 519 "mac_clk_rx", "mac_clk_tx", 520 "clk_mac_ref", "clk_mac_refout", 521 "aclk_mac", "pclk_mac"; 522 status = "disabled"; 523 }; 524 525 usb_host0_ehci: usb@ff500000 { 526 compatible = "generic-ehci"; 527 reg = <0x0 0xff500000 0x0 0x100>; 528 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cru HCLK_HOST0>; 530 clock-names = "usbhost"; 531 status = "disabled"; 532 }; 533 534 usb_otg: usb@ff580000 { 535 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 536 "snps,dwc2"; 537 reg = <0x0 0xff580000 0x0 0x40000>; 538 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cru HCLK_OTG0>; 540 clock-names = "otg"; 541 dr_mode = "otg"; 542 g-np-tx-fifo-size = <16>; 543 g-rx-fifo-size = <275>; 544 g-tx-fifo-size = <256 128 128 64 64 32>; 545 g-use-dma; 546 status = "disabled"; 547 }; 548 549 dmc: dmc@ff610000 { 550 u-boot,dm-pre-reloc; 551 compatible = "rockchip,rk3368-dmc", "syscon"; 552 reg = <0x0 0xff610000 0x0 0x1000>; 553 }; 554 555 i2c0: i2c@ff650000 { 556 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 557 reg = <0x0 0xff650000 0x0 0x1000>; 558 clocks = <&cru PCLK_I2C0>; 559 clock-names = "i2c"; 560 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&i2c0_xfer>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 i2c2: i2c@ff660000 { 569 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 570 reg = <0x0 0xff660000 0x0 0x1000>; 571 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 clock-names = "i2c"; 575 clocks = <&cru PCLK_I2C2>; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&i2c2_xfer>; 578 status = "disabled"; 579 }; 580 581 pwm0: pwm@ff680000 { 582 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 583 reg = <0x0 0xff680000 0x0 0x10>; 584 #pwm-cells = <3>; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&pwm0_pin>; 587 clocks = <&cru PCLK_PWM1>; 588 clock-names = "pwm"; 589 status = "disabled"; 590 }; 591 592 pwm1: pwm@ff680010 { 593 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 594 reg = <0x0 0xff680010 0x0 0x10>; 595 #pwm-cells = <3>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&pwm1_pin>; 598 clocks = <&cru PCLK_PWM1>; 599 clock-names = "pwm"; 600 status = "disabled"; 601 }; 602 603 pwm2: pwm@ff680020 { 604 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 605 reg = <0x0 0xff680020 0x0 0x10>; 606 #pwm-cells = <3>; 607 clocks = <&cru PCLK_PWM1>; 608 clock-names = "pwm"; 609 status = "disabled"; 610 }; 611 612 pwm3: pwm@ff680030 { 613 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 614 reg = <0x0 0xff680030 0x0 0x10>; 615 #pwm-cells = <3>; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&pwm3_pin>; 618 clocks = <&cru PCLK_PWM1>; 619 clock-names = "pwm"; 620 status = "disabled"; 621 }; 622 623 uart2: serial@ff690000 { 624 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 625 reg = <0x0 0xff690000 0x0 0x100>; 626 clock-frequency = <24000000>; 627 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 628 clock-names = "baudclk", "apb_pclk"; 629 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&uart2_xfer>; 632 reg-shift = <2>; 633 reg-io-width = <4>; 634 status = "disabled"; 635 }; 636 637 mbox: mbox@ff6b0000 { 638 compatible = "rockchip,rk3368-mailbox"; 639 reg = <0x0 0xff6b0000 0x0 0x1000>; 640 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cru PCLK_MAILBOX>; 645 clock-names = "pclk_mailbox"; 646 #mbox-cells = <1>; 647 }; 648 649 pmugrf: syscon@ff738000 { 650 u-boot,dm-pre-reloc; 651 compatible = "rockchip,rk3368-pmugrf", "syscon"; 652 reg = <0x0 0xff738000 0x0 0x1000>; 653 }; 654 655 cru: clock-controller@ff760000 { 656 compatible = "rockchip,rk3368-cru"; 657 reg = <0x0 0xff760000 0x0 0x1000>; 658 rockchip,grf = <&grf>; 659 #clock-cells = <1>; 660 #reset-cells = <1>; 661 }; 662 663 grf: syscon@ff770000 { 664 compatible = "rockchip,rk3368-grf", "syscon"; 665 reg = <0x0 0xff770000 0x0 0x1000>; 666 }; 667 668 wdt: watchdog@ff800000 { 669 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 670 reg = <0x0 0xff800000 0x0 0x100>; 671 clocks = <&cru PCLK_WDT>; 672 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 673 status = "disabled"; 674 }; 675 676 timer@ff810000 { 677 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 678 reg = <0x0 0xff810000 0x0 0x20>; 679 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 680 }; 681 682 gic: interrupt-controller@ffb71000 { 683 compatible = "arm,gic-400"; 684 interrupt-controller; 685 #interrupt-cells = <3>; 686 #address-cells = <0>; 687 688 reg = <0x0 0xffb71000 0x0 0x1000>, 689 <0x0 0xffb72000 0x0 0x1000>, 690 <0x0 0xffb74000 0x0 0x2000>, 691 <0x0 0xffb76000 0x0 0x2000>; 692 interrupts = <GIC_PPI 9 693 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 694 }; 695 696 pinctrl: pinctrl { 697 compatible = "rockchip,rk3368-pinctrl"; 698 rockchip,grf = <&grf>; 699 rockchip,pmu = <&pmugrf>; 700 #address-cells = <0x2>; 701 #size-cells = <0x2>; 702 ranges; 703 704 gpio0: gpio0@ff750000 { 705 compatible = "rockchip,gpio-bank"; 706 reg = <0x0 0xff750000 0x0 0x100>; 707 clocks = <&cru PCLK_GPIO0>; 708 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 709 710 gpio-controller; 711 #gpio-cells = <0x2>; 712 713 interrupt-controller; 714 #interrupt-cells = <0x2>; 715 }; 716 717 gpio1: gpio1@ff780000 { 718 compatible = "rockchip,gpio-bank"; 719 reg = <0x0 0xff780000 0x0 0x100>; 720 clocks = <&cru PCLK_GPIO1>; 721 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 722 723 gpio-controller; 724 #gpio-cells = <0x2>; 725 726 interrupt-controller; 727 #interrupt-cells = <0x2>; 728 }; 729 730 gpio2: gpio2@ff790000 { 731 compatible = "rockchip,gpio-bank"; 732 reg = <0x0 0xff790000 0x0 0x100>; 733 clocks = <&cru PCLK_GPIO2>; 734 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 735 736 gpio-controller; 737 #gpio-cells = <0x2>; 738 739 interrupt-controller; 740 #interrupt-cells = <0x2>; 741 }; 742 743 gpio3: gpio3@ff7a0000 { 744 compatible = "rockchip,gpio-bank"; 745 reg = <0x0 0xff7a0000 0x0 0x100>; 746 clocks = <&cru PCLK_GPIO3>; 747 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 748 749 gpio-controller; 750 #gpio-cells = <0x2>; 751 752 interrupt-controller; 753 #interrupt-cells = <0x2>; 754 }; 755 756 pcfg_pull_up: pcfg-pull-up { 757 bias-pull-up; 758 }; 759 760 pcfg_pull_down: pcfg-pull-down { 761 bias-pull-down; 762 }; 763 764 pcfg_pull_none: pcfg-pull-none { 765 bias-disable; 766 }; 767 768 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 769 bias-disable; 770 drive-strength = <12>; 771 }; 772 773 emmc { 774 emmc_clk: emmc-clk { 775 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 776 }; 777 778 emmc_cmd: emmc-cmd { 779 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; 780 }; 781 782 emmc_pwr: emmc-pwr { 783 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; 784 }; 785 786 emmc_bus1: emmc-bus1 { 787 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; 788 }; 789 790 emmc_bus4: emmc-bus4 { 791 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 792 <1 19 RK_FUNC_2 &pcfg_pull_up>, 793 <1 20 RK_FUNC_2 &pcfg_pull_up>, 794 <1 21 RK_FUNC_2 &pcfg_pull_up>; 795 }; 796 797 emmc_bus8: emmc-bus8 { 798 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 799 <1 19 RK_FUNC_2 &pcfg_pull_up>, 800 <1 20 RK_FUNC_2 &pcfg_pull_up>, 801 <1 21 RK_FUNC_2 &pcfg_pull_up>, 802 <1 22 RK_FUNC_2 &pcfg_pull_up>, 803 <1 23 RK_FUNC_2 &pcfg_pull_up>, 804 <1 24 RK_FUNC_2 &pcfg_pull_up>, 805 <1 25 RK_FUNC_2 &pcfg_pull_up>; 806 }; 807 }; 808 809 gmac { 810 rgmii_pins: rgmii-pins { 811 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 812 <3 24 RK_FUNC_1 &pcfg_pull_none>, 813 <3 19 RK_FUNC_1 &pcfg_pull_none>, 814 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 815 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 816 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, 817 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, 818 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, 819 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 820 <3 15 RK_FUNC_1 &pcfg_pull_none>, 821 <3 16 RK_FUNC_1 &pcfg_pull_none>, 822 <3 17 RK_FUNC_1 &pcfg_pull_none>, 823 <3 18 RK_FUNC_1 &pcfg_pull_none>, 824 <3 25 RK_FUNC_1 &pcfg_pull_none>, 825 <3 20 RK_FUNC_1 &pcfg_pull_none>; 826 }; 827 828 rmii_pins: rmii-pins { 829 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 830 <3 24 RK_FUNC_1 &pcfg_pull_none>, 831 <3 19 RK_FUNC_1 &pcfg_pull_none>, 832 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 833 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 834 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 835 <3 15 RK_FUNC_1 &pcfg_pull_none>, 836 <3 16 RK_FUNC_1 &pcfg_pull_none>, 837 <3 20 RK_FUNC_1 &pcfg_pull_none>, 838 <3 21 RK_FUNC_1 &pcfg_pull_none>; 839 }; 840 }; 841 842 i2c0 { 843 i2c0_xfer: i2c0-xfer { 844 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 845 <0 7 RK_FUNC_1 &pcfg_pull_none>; 846 }; 847 }; 848 849 i2c1 { 850 i2c1_xfer: i2c1-xfer { 851 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, 852 <2 22 RK_FUNC_1 &pcfg_pull_none>; 853 }; 854 }; 855 856 i2c2 { 857 i2c2_xfer: i2c2-xfer { 858 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, 859 <3 31 RK_FUNC_2 &pcfg_pull_none>; 860 }; 861 }; 862 863 i2c3 { 864 i2c3_xfer: i2c3-xfer { 865 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, 866 <1 17 RK_FUNC_1 &pcfg_pull_none>; 867 }; 868 }; 869 870 i2c4 { 871 i2c4_xfer: i2c4-xfer { 872 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, 873 <3 25 RK_FUNC_2 &pcfg_pull_none>; 874 }; 875 }; 876 877 i2c5 { 878 i2c5_xfer: i2c5-xfer { 879 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, 880 <3 27 RK_FUNC_2 &pcfg_pull_none>; 881 }; 882 }; 883 884 pwm0 { 885 pwm0_pin: pwm0-pin { 886 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; 887 }; 888 }; 889 890 pwm1 { 891 pwm1_pin: pwm1-pin { 892 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; 893 }; 894 }; 895 896 pwm3 { 897 pwm3_pin: pwm3-pin { 898 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; 899 }; 900 }; 901 902 sdio0 { 903 sdio0_bus1: sdio0-bus1 { 904 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; 905 }; 906 907 sdio0_bus4: sdio0-bus4 { 908 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, 909 <2 29 RK_FUNC_1 &pcfg_pull_up>, 910 <2 30 RK_FUNC_1 &pcfg_pull_up>, 911 <2 31 RK_FUNC_1 &pcfg_pull_up>; 912 }; 913 914 sdio0_cmd: sdio0-cmd { 915 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; 916 }; 917 918 sdio0_clk: sdio0-clk { 919 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; 920 }; 921 922 sdio0_cd: sdio0-cd { 923 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; 924 }; 925 926 sdio0_wp: sdio0-wp { 927 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; 928 }; 929 930 sdio0_pwr: sdio0-pwr { 931 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; 932 }; 933 934 sdio0_bkpwr: sdio0-bkpwr { 935 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; 936 }; 937 938 sdio0_int: sdio0-int { 939 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; 940 }; 941 }; 942 943 sdmmc { 944 sdmmc_clk: sdmmc-clk { 945 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; 946 }; 947 948 sdmmc_cmd: sdmmc-cmd { 949 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; 950 }; 951 952 sdmmc_cd: sdmmc-cd { 953 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; 954 }; 955 956 sdmmc_bus1: sdmmc-bus1 { 957 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; 958 }; 959 960 sdmmc_bus4: sdmmc-bus4 { 961 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, 962 <2 6 RK_FUNC_1 &pcfg_pull_up>, 963 <2 7 RK_FUNC_1 &pcfg_pull_up>, 964 <2 8 RK_FUNC_1 &pcfg_pull_up>; 965 }; 966 }; 967 968 spi0 { 969 spi0_clk: spi0-clk { 970 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; 971 }; 972 spi0_cs0: spi0-cs0 { 973 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; 974 }; 975 spi0_cs1: spi0-cs1 { 976 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; 977 }; 978 spi0_tx: spi0-tx { 979 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; 980 }; 981 spi0_rx: spi0-rx { 982 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; 983 }; 984 }; 985 986 spi1 { 987 spi1_clk: spi1-clk { 988 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; 989 }; 990 spi1_cs0: spi1-cs0 { 991 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; 992 }; 993 spi1_cs1: spi1-cs1 { 994 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; 995 }; 996 spi1_rx: spi1-rx { 997 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; 998 }; 999 spi1_tx: spi1-tx { 1000 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; 1001 }; 1002 }; 1003 1004 spi2 { 1005 spi2_clk: spi2-clk { 1006 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; 1007 }; 1008 spi2_cs0: spi2-cs0 { 1009 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 1010 }; 1011 spi2_rx: spi2-rx { 1012 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; 1013 }; 1014 spi2_tx: spi2-tx { 1015 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 1016 }; 1017 }; 1018 1019 tsadc { 1020 otp_gpio: otp-gpio { 1021 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; 1022 }; 1023 1024 otp_out: otp-out { 1025 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>; 1026 }; 1027 }; 1028 1029 uart0 { 1030 uart0_xfer: uart0-xfer { 1031 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, 1032 <2 25 RK_FUNC_1 &pcfg_pull_none>; 1033 }; 1034 1035 uart0_cts: uart0-cts { 1036 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; 1037 }; 1038 1039 uart0_rts: uart0-rts { 1040 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; 1041 }; 1042 }; 1043 1044 uart1 { 1045 uart1_xfer: uart1-xfer { 1046 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, 1047 <0 21 RK_FUNC_3 &pcfg_pull_none>; 1048 }; 1049 1050 uart1_cts: uart1-cts { 1051 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; 1052 }; 1053 1054 uart1_rts: uart1-rts { 1055 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; 1056 }; 1057 }; 1058 1059 uart2 { 1060 uart2_xfer: uart2-xfer { 1061 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, 1062 <2 5 RK_FUNC_2 &pcfg_pull_none>; 1063 }; 1064 /* no rts / cts for uart2 */ 1065 }; 1066 1067 uart3 { 1068 uart3_xfer: uart3-xfer { 1069 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, 1070 <3 30 RK_FUNC_3 &pcfg_pull_none>; 1071 }; 1072 1073 uart3_cts: uart3-cts { 1074 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; 1075 }; 1076 1077 uart3_rts: uart3-rts { 1078 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; 1079 }; 1080 }; 1081 1082 uart4 { 1083 uart4_xfer: uart4-xfer { 1084 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, 1085 <0 26 RK_FUNC_3 &pcfg_pull_none>; 1086 }; 1087 1088 uart4_cts: uart4-cts { 1089 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; 1090 }; 1091 1092 uart4_rts: uart4-rts { 1093 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; 1094 }; 1095 }; 1096 }; 1097}; 1098