1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 */
5
6/ {
7	config {
8		u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
9		u-boot,mmc-env-offset = <0x4000>;      /* @  16KB */
10	};
11
12	chosen {
13		stdout-path = "serial0:115200n8";
14		u-boot,spl-boot-order = &emmc, &sdmmc;
15		tick-timer = "/timer@ff810000";
16	};
17
18};
19
20&pinctrl {
21	u-boot,dm-pre-reloc;
22};
23
24&service_msch {
25	u-boot,dm-pre-reloc;
26};
27
28&dmc {
29	u-boot,dm-pre-reloc;
30
31	/*
32	 * Validation of throughput using SPEC2000 shows the following
33	 * relative performance for the different memory schedules:
34	 *  - CBDR: 30.1
35	 *  - CBRD: 29.8
36	 *  - CRBD: 29.9
37	 * Note that the best performance for any given application workload
38	 * may vary from the default configured here (e.g. 164.gzip is fastest
39	 * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
40	 *
41	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
42	 * details on the 'rockchip,memory-schedule' property and how it
43	 * affects the physical-address to device-address mapping.
44	 */
45	rockchip,memory-schedule = <DMC_MSCH_CBDR>;
46	rockchip,ddr-frequency = <800000000>;
47	rockchip,ddr-speed-bin = <DDR3_1600K>;
48
49	status = "okay";
50};
51
52&pmugrf {
53	u-boot,dm-pre-reloc;
54};
55
56&sgrf {
57        u-boot,dm-pre-reloc;
58};
59
60&cru {
61	u-boot,dm-pre-reloc;
62};
63
64&grf {
65	u-boot,dm-pre-reloc;
66};
67
68&uart0 {
69	u-boot,dm-pre-reloc;
70};
71
72&emmc {
73	u-boot,dm-spl;
74};
75
76&sdmmc {
77	u-boot,dm-spl;
78};
79
80&spi1 {
81	u-boot,dm-spl;
82
83	spiflash: w25q32dw@0 {
84		u-boot,dm-spl;
85	};
86};
87
88&timer0 {
89	u-boot,dm-pre-reloc;
90	clock-frequency = <24000000>;
91	status = "okay";
92};
93
94
95