1/*
2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
3 *
4 * SPDX-License-Identifier:     GPL-2.0+	X11
5 */
6
7/ {
8	config {
9		u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
10		u-boot,mmc-env-offset = <0x4000>;      /* @  16KB */
11	};
12
13	chosen {
14		stdout-path = "serial0:115200n8";
15		u-boot,spl-boot-order = &emmc, &sdmmc;
16		tick-timer = "/timer@ff810000";
17	};
18
19};
20
21&pinctrl {
22	u-boot,dm-pre-reloc;
23};
24
25&service_msch {
26	u-boot,dm-pre-reloc;
27};
28
29&dmc {
30	u-boot,dm-pre-reloc;
31
32	/*
33	 * Validation of throughput using SPEC2000 shows the following
34	 * relative performance for the different memory schedules:
35	 *  - CBDR: 30.1
36	 *  - CBRD: 29.8
37	 *  - CRBD: 29.9
38	 * Note that the best performance for any given application workload
39	 * may vary from the default configured here (e.g. 164.gzip is fastest
40	 * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
41	 *
42	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
43	 * details on the 'rockchip,memory-schedule' property and how it
44	 * affects the physical-address to device-address mapping.
45	 */
46	rockchip,memory-schedule = <DMC_MSCH_CBDR>;
47	rockchip,ddr-frequency = <800000000>;
48	rockchip,ddr-speed-bin = <DDR3_1600K>;
49
50	status = "okay";
51};
52
53&pmugrf {
54	u-boot,dm-pre-reloc;
55};
56
57&sgrf {
58        u-boot,dm-pre-reloc;
59};
60
61&cru {
62	u-boot,dm-pre-reloc;
63};
64
65&grf {
66	u-boot,dm-pre-reloc;
67};
68
69&uart0 {
70	u-boot,dm-pre-reloc;
71};
72
73&emmc {
74	u-boot,dm-spl;
75};
76
77&sdmmc {
78	u-boot,dm-spl;
79};
80
81&spi1 {
82	u-boot,dm-spl;
83
84	spiflash: w25q32dw@0 {
85		u-boot,dm-spl;
86	};
87};
88
89&timer0 {
90	u-boot,dm-pre-reloc;
91	clock-frequency = <24000000>;
92	status = "okay";
93};
94
95
96