1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &emmc; 29 mmc1 = &sdmmc; 30 mmc2 = &sdmmc_ext; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42// clocks = <&cru ARMCLK>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 }; 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 }; 51 cpu2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 reg = <0x0 0x2>; 55 enable-method = "psci"; 56 }; 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 }; 63 }; 64 65 cpu0_opp_table: opp_table0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp@408000000 { 70 opp-hz = /bits/ 64 <408000000>; 71 opp-microvolt = <950000>; 72 clock-latency-ns = <40000>; 73 opp-suspend; 74 }; 75 opp@600000000 { 76 opp-hz = /bits/ 64 <600000000>; 77 opp-microvolt = <950000>; 78 clock-latency-ns = <40000>; 79 }; 80 opp@816000000 { 81 opp-hz = /bits/ 64 <816000000>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <40000>; 84 }; 85 opp@1008000000 { 86 opp-hz = /bits/ 64 <1008000000>; 87 opp-microvolt = <1100000>; 88 clock-latency-ns = <40000>; 89 }; 90 opp@1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1225000>; 93 clock-latency-ns = <40000>; 94 }; 95 opp@1296000000 { 96 opp-hz = /bits/ 64 <1296000000>; 97 opp-microvolt = <1300000>; 98 clock-latency-ns = <40000>; 99 }; 100 }; 101 102 arm-pmu { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xin24m: xin24m { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <24000000>; 128 clock-output-names = "xin24m"; 129 }; 130 131 i2s0: i2s@ff000000 { 132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 133 reg = <0x0 0xff000000 0x0 0x1000>; 134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 136 clock-names = "i2s_clk", "i2s_hclk"; 137 dmas = <&dmac 11>, <&dmac 12>; 138 #dma-cells = <2>; 139 dma-names = "tx", "rx"; 140 status = "disabled"; 141 }; 142 143 i2s1: i2s@ff010000 { 144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 145 reg = <0x0 0xff010000 0x0 0x1000>; 146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 148 clock-names = "i2s_clk", "i2s_hclk"; 149 dmas = <&dmac 14>, <&dmac 15>; 150 #dma-cells = <2>; 151 dma-names = "tx", "rx"; 152 status = "disabled"; 153 }; 154 155 i2s2: i2s@ff020000 { 156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 157 reg = <0x0 0xff020000 0x0 0x1000>; 158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 160 clock-names = "i2s_clk", "i2s_hclk"; 161 dmas = <&dmac 0>, <&dmac 1>; 162 #dma-cells = <2>; 163 dma-names = "tx", "rx"; 164 pinctrl-names = "default", "sleep"; 165 pinctrl-0 = <&i2s2m0_mclk 166 &i2s2m0_sclk 167 &i2s2m0_lrcktx 168 &i2s2m0_lrckrx 169 &i2s2m0_sdo 170 &i2s2m0_sdi>; 171 pinctrl-1 = <&i2s2m0_sleep>; 172 status = "disabled"; 173 }; 174 175 spdif: spdif@ff030000 { 176 compatible = "rockchip,rk3328-spdif"; 177 reg = <0x0 0xff030000 0x0 0x1000>; 178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 180 clock-names = "mclk", "hclk"; 181 dmas = <&dmac 10>; 182 #dma-cells = <1>; 183 dma-names = "tx"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spdifm2_tx>; 186 status = "disabled"; 187 }; 188 189 grf: syscon@ff100000 { 190 u-boot,dm-pre-reloc; 191 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 192 reg = <0x0 0xff100000 0x0 0x1000>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 196 io_domains: io-domains { 197 compatible = "rockchip,rk3328-io-voltage-domain"; 198 status = "disabled"; 199 }; 200 }; 201 202 uart0: serial@ff110000 { 203 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 204 reg = <0x0 0xff110000 0x0 0x100>; 205 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 207 clock-names = "baudclk", "apb_pclk"; 208 reg-shift = <2>; 209 reg-io-width = <4>; 210 dmas = <&dmac 2>, <&dmac 3>; 211 #dma-cells = <2>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 214 status = "disabled"; 215 }; 216 217 uart1: serial@ff120000 { 218 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 219 reg = <0x0 0xff120000 0x0 0x100>; 220 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 222 clock-names = "sclk_uart", "pclk_uart"; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 dmas = <&dmac 4>, <&dmac 5>; 226 #dma-cells = <2>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 229 status = "disabled"; 230 }; 231 232 uart2: serial@ff130000 { 233 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 234 reg = <0x0 0xff130000 0x0 0x100>; 235 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 237 clock-names = "baudclk", "apb_pclk"; 238 clock-frequency = <24000000>; 239 reg-shift = <2>; 240 reg-io-width = <4>; 241 dmas = <&dmac 6>, <&dmac 7>; 242 #dma-cells = <2>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&uart2m1_xfer>; 245 status = "disabled"; 246 }; 247 248 pmu: power-management@ff140000 { 249 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 250 reg = <0x0 0xff140000 0x0 0x1000>; 251 }; 252 253 i2c0: i2c@ff150000 { 254 compatible = "rockchip,rk3328-i2c"; 255 reg = <0x0 0xff150000 0x0 0x1000>; 256 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 260 clock-names = "i2c", "pclk"; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&i2c0_xfer>; 263 status = "disabled"; 264 }; 265 266 i2c1: i2c@ff160000 { 267 compatible = "rockchip,rk3328-i2c"; 268 reg = <0x0 0xff160000 0x0 0x1000>; 269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 273 clock-names = "i2c", "pclk"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&i2c1_xfer>; 276 status = "disabled"; 277 }; 278 279 i2c2: i2c@ff170000 { 280 compatible = "rockchip,rk3328-i2c"; 281 reg = <0x0 0xff170000 0x0 0x1000>; 282 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 286 clock-names = "i2c", "pclk"; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&i2c2_xfer>; 289 status = "disabled"; 290 }; 291 292 i2c3: i2c@ff180000 { 293 compatible = "rockchip,rk3328-i2c"; 294 reg = <0x0 0xff180000 0x0 0x1000>; 295 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 299 clock-names = "i2c", "pclk"; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c3_xfer>; 302 status = "disabled"; 303 }; 304 305 spi0: spi@ff190000 { 306 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 307 reg = <0x0 0xff190000 0x0 0x1000>; 308 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 312 clock-names = "spiclk", "apb_pclk"; 313 dmas = <&dmac 8>, <&dmac 9>; 314 #dma-cells = <2>; 315 dma-names = "tx", "rx"; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 318 status = "disabled"; 319 }; 320 321 wdt: watchdog@ff1a0000 { 322 compatible = "snps,dw-wdt"; 323 reg = <0x0 0xff1a0000 0x0 0x100>; 324 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 325 status = "disabled"; 326 }; 327 328 amba { 329 compatible = "simple-bus"; 330 #address-cells = <2>; 331 #size-cells = <2>; 332 ranges; 333 334 dmac: dmac@ff1f0000 { 335 compatible = "arm,pl330", "arm,primecell"; 336 reg = <0x0 0xff1f0000 0x0 0x4000>; 337 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&cru ACLK_DMAC>; 340 clock-names = "apb_pclk"; 341 #dma-cells = <1>; 342 }; 343 }; 344 345 saradc: saradc@ff280000 { 346 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 347 reg = <0x0 0xff280000 0x0 0x100>; 348 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 349 #io-channel-cells = <1>; 350 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 351 clock-names = "saradc", "apb_pclk"; 352 resets = <&cru SRST_SARADC_P>; 353 reset-names = "saradc-apb"; 354 status = "disabled"; 355 }; 356 357 dmc: dmc@ff400000 { 358 u-boot,dm-pre-reloc; 359 compatible = "rockchip,rk3328-dmc", "syscon"; 360 reg = <0x0 0xff400000 0x0 0x1000>; 361 }; 362 363 cru: clock-controller@ff440000 { 364 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 365 reg = <0x0 0xff440000 0x0 0x1000>; 366 rockchip,grf = <&grf>; 367 #clock-cells = <1>; 368 #reset-cells = <1>; 369 assigned-clocks = 370 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 371 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 372 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 373 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 374 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 375 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 376 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 377 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 378 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 379 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 380 <&cru SCLK_WIFI>, <&cru ARMCLK>, 381 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 382 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 383 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 384 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 385 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 386 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 387 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 388 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 389 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 390 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 391 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 392 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 393 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 394 assigned-clock-parents = 395 <&cru HDMIPHY>, <&cru PLL_APLL>, 396 <&cru PLL_GPLL>, <&xin24m>, 397 <&xin24m>, <&xin24m>; 398 assigned-clock-rates = 399 <0>, <61440000>, 400 <0>, <24000000>, 401 <24000000>, <24000000>, 402 <15000000>, <15000000>, 403 <100000000>, <100000000>, 404 <100000000>, <100000000>, 405 <50000000>, <100000000>, 406 <100000000>, <100000000>, 407 <50000000>, <50000000>, 408 <50000000>, <50000000>, 409 <24000000>, <600000000>, 410 <491520000>, <1200000000>, 411 <150000000>, <75000000>, 412 <75000000>, <150000000>, 413 <75000000>, <75000000>, 414 <300000000>, <100000000>, 415 <300000000>, <200000000>, 416 <400000000>, <500000000>, 417 <200000000>, <300000000>, 418 <300000000>, <250000000>, 419 <200000000>, <100000000>, 420 <24000000>, <100000000>, 421 <150000000>, <50000000>, 422 <32768>, <32768>; 423 }; 424 425 sdmmc: rksdmmc@ff500000 { 426 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 427 reg = <0x0 0xff500000 0x0 0x4000>; 428 max-frequency = <150000000>; 429 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 430 clock-names = "biu", "ciu"; 431 fifo-depth = <0x100>; 432 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 433 status = "disabled"; 434 }; 435 436 sdio: dwmmc@ff510000 { 437 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 438 reg = <0x0 0xff510000 0x0 0x4000>; 439 max-frequency = <150000000>; 440 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 441 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 442 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 443 fifo-depth = <0x100>; 444 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 445 status = "disabled"; 446 }; 447 448 emmc: rksdmmc@ff520000 { 449 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 450 reg = <0x0 0xff520000 0x0 0x4000>; 451 max-frequency = <150000000>; 452 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 453 clock-names = "biu", "ciu"; 454 fifo-depth = <0x100>; 455 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 456 status = "disabled"; 457 }; 458 459 usb_host0_ehci: usb@ff5c0000 { 460 compatible = "generic-ehci"; 461 reg = <0x0 0xff5c0000 0x0 0x10000>; 462 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 463 status = "disabled"; 464 }; 465 466 usb_host0_ohci: usb@ff5d0000 { 467 compatible = "generic-ohci"; 468 reg = <0x0 0xff5d0000 0x0 0x10000>; 469 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 470 status = "disabled"; 471 }; 472 473 usb20_otg: usb@ff580000 { 474 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 475 "snps,dwc2"; 476 reg = <0x0 0xff580000 0x0 0x40000>; 477 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 478 hnp-srp-disable; 479 dr_mode = "otg"; 480 status = "disabled"; 481 }; 482 483 sdmmc_ext: rksdmmc@ff5f0000 { 484 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 485 reg = <0x0 0xff5f0000 0x0 0x4000>; 486 max-frequency = <150000000>; 487 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 488 clock-names = "biu", "ciu"; 489 fifo-depth = <0x100>; 490 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 491 status = "disabled"; 492 }; 493 494 usb_host0_xhci: usb@ff600000 { 495 compatible = "rockchip,rk3328-xhci"; 496 reg = <0x0 0xff600000 0x0 0x100000>; 497 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 498 snps,dis-enblslpm-quirk; 499 snps,phyif-utmi-bits = <16>; 500 snps,dis-u2-freeclk-exists-quirk; 501 snps,dis-u2-susphy-quirk; 502 status = "disabled"; 503 }; 504 505 gic: interrupt-controller@ffb70000 { 506 compatible = "arm,gic-400"; 507 #interrupt-cells = <3>; 508 #address-cells = <0>; 509 interrupt-controller; 510 reg = <0x0 0xff811000 0 0x1000>, 511 <0x0 0xff812000 0 0x2000>, 512 <0x0 0xff814000 0 0x2000>, 513 <0x0 0xff816000 0 0x2000>; 514 interrupts = <GIC_PPI 9 515 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 516 }; 517 518 pinctrl: pinctrl { 519 compatible = "rockchip,rk3328-pinctrl"; 520 rockchip,grf = <&grf>; 521 #address-cells = <2>; 522 #size-cells = <2>; 523 ranges; 524 525 gpio0: gpio0@ff210000 { 526 compatible = "rockchip,gpio-bank"; 527 reg = <0x0 0xff210000 0x0 0x100>; 528 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cru PCLK_GPIO0>; 530 531 gpio-controller; 532 #gpio-cells = <2>; 533 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 538 gpio1: gpio1@ff220000 { 539 compatible = "rockchip,gpio-bank"; 540 reg = <0x0 0xff220000 0x0 0x100>; 541 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cru PCLK_GPIO1>; 543 544 gpio-controller; 545 #gpio-cells = <2>; 546 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 }; 550 551 gpio2: gpio2@ff230000 { 552 compatible = "rockchip,gpio-bank"; 553 reg = <0x0 0xff230000 0x0 0x100>; 554 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cru PCLK_GPIO2>; 556 557 gpio-controller; 558 #gpio-cells = <2>; 559 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 }; 563 564 gpio3: gpio3@ff240000 { 565 compatible = "rockchip,gpio-bank"; 566 reg = <0x0 0xff240000 0x0 0x100>; 567 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&cru PCLK_GPIO3>; 569 570 gpio-controller; 571 #gpio-cells = <2>; 572 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 }; 576 577 pcfg_pull_up: pcfg-pull-up { 578 bias-pull-up; 579 }; 580 581 pcfg_pull_down: pcfg-pull-down { 582 bias-pull-down; 583 }; 584 585 pcfg_pull_none: pcfg-pull-none { 586 bias-disable; 587 }; 588 589 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 590 bias-disable; 591 drive-strength = <2>; 592 }; 593 594 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 595 bias-pull-up; 596 drive-strength = <2>; 597 }; 598 599 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 600 bias-pull-up; 601 drive-strength = <4>; 602 }; 603 604 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 605 bias-disable; 606 drive-strength = <4>; 607 }; 608 609 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 610 bias-pull-down; 611 drive-strength = <4>; 612 }; 613 614 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 615 bias-disable; 616 drive-strength = <8>; 617 }; 618 619 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 620 bias-pull-up; 621 drive-strength = <8>; 622 }; 623 624 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 625 bias-disable; 626 drive-strength = <12>; 627 }; 628 629 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 630 bias-pull-up; 631 drive-strength = <12>; 632 }; 633 634 pcfg_output_high: pcfg-output-high { 635 output-high; 636 }; 637 638 pcfg_output_low: pcfg-output-low { 639 output-low; 640 }; 641 642 pcfg_input_high: pcfg-input-high { 643 bias-pull-up; 644 input-enable; 645 }; 646 647 pcfg_input: pcfg-input { 648 input-enable; 649 }; 650 651 i2c0 { 652 i2c0_xfer: i2c0-xfer { 653 rockchip,pins = 654 <2 24 RK_FUNC_1 &pcfg_pull_none>, 655 <2 25 RK_FUNC_1 &pcfg_pull_none>; 656 }; 657 }; 658 659 i2c1 { 660 i2c1_xfer: i2c1-xfer { 661 rockchip,pins = 662 <2 4 RK_FUNC_2 &pcfg_pull_none>, 663 <2 5 RK_FUNC_2 &pcfg_pull_none>; 664 }; 665 }; 666 667 i2c2 { 668 i2c2_xfer: i2c2-xfer { 669 rockchip,pins = 670 <2 13 RK_FUNC_1 &pcfg_pull_none>, 671 <2 14 RK_FUNC_1 &pcfg_pull_none>; 672 }; 673 }; 674 675 i2c3 { 676 i2c3_xfer: i2c3-xfer { 677 rockchip,pins = 678 <0 5 RK_FUNC_2 &pcfg_pull_none>, 679 <0 6 RK_FUNC_2 &pcfg_pull_none>; 680 }; 681 i2c3_gpio: i2c3-gpio { 682 rockchip,pins = 683 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 684 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 685 }; 686 }; 687 688 hdmi_i2c { 689 hdmii2c_xfer: hdmii2c-xfer { 690 rockchip,pins = 691 <0 5 RK_FUNC_1 &pcfg_pull_none>, 692 <0 6 RK_FUNC_1 &pcfg_pull_none>; 693 }; 694 }; 695 696 uart0 { 697 uart0_xfer: uart0-xfer { 698 rockchip,pins = 699 <1 9 RK_FUNC_1 &pcfg_pull_up>, 700 <1 8 RK_FUNC_1 &pcfg_pull_none>; 701 }; 702 703 uart0_cts: uart0-cts { 704 rockchip,pins = 705 <1 11 RK_FUNC_1 &pcfg_pull_none>; 706 }; 707 708 uart0_rts: uart0-rts { 709 rockchip,pins = 710 <1 10 RK_FUNC_1 &pcfg_pull_none>; 711 }; 712 713 uart0_rts_gpio: uart0-rts-gpio { 714 rockchip,pins = 715 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 716 }; 717 }; 718 719 uart1 { 720 uart1_xfer: uart1-xfer { 721 rockchip,pins = 722 <3 4 RK_FUNC_4 &pcfg_pull_up>, 723 <3 6 RK_FUNC_4 &pcfg_pull_none>; 724 }; 725 726 uart1_cts: uart1-cts { 727 rockchip,pins = 728 <3 7 RK_FUNC_4 &pcfg_pull_none>; 729 }; 730 731 uart1_rts: uart1-rts { 732 rockchip,pins = 733 <3 5 RK_FUNC_4 &pcfg_pull_none>; 734 }; 735 736 uart1_rts_gpio: uart1-rts-gpio { 737 rockchip,pins = 738 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 739 }; 740 }; 741 742 uart2-0 { 743 uart2m0_xfer: uart2m0-xfer { 744 rockchip,pins = 745 <1 0 RK_FUNC_2 &pcfg_pull_up>, 746 <1 1 RK_FUNC_2 &pcfg_pull_none>; 747 }; 748 }; 749 750 uart2-1 { 751 uart2m1_xfer: uart2m1-xfer { 752 rockchip,pins = 753 <2 0 RK_FUNC_1 &pcfg_pull_up>, 754 <2 1 RK_FUNC_1 &pcfg_pull_none>; 755 }; 756 }; 757 758 spi0-0 { 759 spi0m0_clk: spi0m0-clk { 760 rockchip,pins = 761 <2 8 RK_FUNC_1 &pcfg_pull_up>; 762 }; 763 764 spi0m0_cs0: spi0m0-cs0 { 765 rockchip,pins = 766 <2 11 RK_FUNC_1 &pcfg_pull_up>; 767 }; 768 769 spi0m0_tx: spi0m0-tx { 770 rockchip,pins = 771 <2 9 RK_FUNC_1 &pcfg_pull_up>; 772 }; 773 774 spi0m0_rx: spi0m0-rx { 775 rockchip,pins = 776 <2 10 RK_FUNC_1 &pcfg_pull_up>; 777 }; 778 779 spi0m0_cs1: spi0m0-cs1 { 780 rockchip,pins = 781 <2 12 RK_FUNC_1 &pcfg_pull_up>; 782 }; 783 }; 784 785 spi0-1 { 786 spi0m1_clk: spi0m1-clk { 787 rockchip,pins = 788 <3 23 RK_FUNC_2 &pcfg_pull_up>; 789 }; 790 791 spi0m1_cs0: spi0m1-cs0 { 792 rockchip,pins = 793 <3 26 RK_FUNC_2 &pcfg_pull_up>; 794 }; 795 796 spi0m1_tx: spi0m1-tx { 797 rockchip,pins = 798 <3 25 RK_FUNC_2 &pcfg_pull_up>; 799 }; 800 801 spi0m1_rx: spi0m1-rx { 802 rockchip,pins = 803 <3 24 RK_FUNC_2 &pcfg_pull_up>; 804 }; 805 806 spi0m1_cs1: spi0m1-cs1 { 807 rockchip,pins = 808 <3 27 RK_FUNC_2 &pcfg_pull_up>; 809 }; 810 }; 811 812 spi0-2 { 813 spi0m2_clk: spi0m2-clk { 814 rockchip,pins = 815 <3 0 RK_FUNC_4 &pcfg_pull_up>; 816 }; 817 818 spi0m2_cs0: spi0m2-cs0 { 819 rockchip,pins = 820 <3 8 RK_FUNC_3 &pcfg_pull_up>; 821 }; 822 823 spi0m2_tx: spi0m2-tx { 824 rockchip,pins = 825 <3 1 RK_FUNC_4 &pcfg_pull_up>; 826 }; 827 828 spi0m2_rx: spi0m2-rx { 829 rockchip,pins = 830 <3 2 RK_FUNC_4 &pcfg_pull_up>; 831 }; 832 }; 833 834 i2s1 { 835 i2s1_mclk: i2s1-mclk { 836 rockchip,pins = 837 <2 15 RK_FUNC_1 &pcfg_pull_none>; 838 }; 839 840 i2s1_sclk: i2s1-sclk { 841 rockchip,pins = 842 <2 18 RK_FUNC_1 &pcfg_pull_none>; 843 }; 844 845 i2s1_lrckrx: i2s1-lrckrx { 846 rockchip,pins = 847 <2 16 RK_FUNC_1 &pcfg_pull_none>; 848 }; 849 850 i2s1_lrcktx: i2s1-lrcktx { 851 rockchip,pins = 852 <2 17 RK_FUNC_1 &pcfg_pull_none>; 853 }; 854 855 i2s1_sdi: i2s1-sdi { 856 rockchip,pins = 857 <2 19 RK_FUNC_1 &pcfg_pull_none>; 858 }; 859 860 i2s1_sdo: i2s1-sdo { 861 rockchip,pins = 862 <2 23 RK_FUNC_1 &pcfg_pull_none>; 863 }; 864 865 i2s1_sdio1: i2s1-sdio1 { 866 rockchip,pins = 867 <2 20 RK_FUNC_1 &pcfg_pull_none>; 868 }; 869 870 i2s1_sdio2: i2s1-sdio2 { 871 rockchip,pins = 872 <2 21 RK_FUNC_1 &pcfg_pull_none>; 873 }; 874 875 i2s1_sdio3: i2s1-sdio3 { 876 rockchip,pins = 877 <2 22 RK_FUNC_1 &pcfg_pull_none>; 878 }; 879 880 i2s1_sleep: i2s1-sleep { 881 rockchip,pins = 882 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 883 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 884 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 885 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 886 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 887 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 888 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 889 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 890 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 891 }; 892 }; 893 894 i2s2-0 { 895 i2s2m0_mclk: i2s2m0-mclk { 896 rockchip,pins = 897 <1 21 RK_FUNC_1 &pcfg_pull_none>; 898 }; 899 900 i2s2m0_sclk: i2s2m0-sclk { 901 rockchip,pins = 902 <1 22 RK_FUNC_1 &pcfg_pull_none>; 903 }; 904 905 i2s2m0_lrckrx: i2s2m0-lrckrx { 906 rockchip,pins = 907 <1 26 RK_FUNC_1 &pcfg_pull_none>; 908 }; 909 910 i2s2m0_lrcktx: i2s2m0-lrcktx { 911 rockchip,pins = 912 <1 23 RK_FUNC_1 &pcfg_pull_none>; 913 }; 914 915 i2s2m0_sdi: i2s2m0-sdi { 916 rockchip,pins = 917 <1 24 RK_FUNC_1 &pcfg_pull_none>; 918 }; 919 920 i2s2m0_sdo: i2s2m0-sdo { 921 rockchip,pins = 922 <1 25 RK_FUNC_1 &pcfg_pull_none>; 923 }; 924 925 i2s2m0_sleep: i2s2m0-sleep { 926 rockchip,pins = 927 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 928 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 929 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 930 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 931 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 932 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 933 }; 934 }; 935 936 i2s2-1 { 937 i2s2m1_mclk: i2s2m1-mclk { 938 rockchip,pins = 939 <1 21 RK_FUNC_1 &pcfg_pull_none>; 940 }; 941 942 i2s2m1_sclk: i2s2m1-sclk { 943 rockchip,pins = 944 <3 0 RK_FUNC_6 &pcfg_pull_none>; 945 }; 946 947 i2s2m1_lrckrx: i2sm1-lrckrx { 948 rockchip,pins = 949 <3 8 RK_FUNC_6 &pcfg_pull_none>; 950 }; 951 952 i2s2m1_lrcktx: i2s2m1-lrcktx { 953 rockchip,pins = 954 <3 8 RK_FUNC_4 &pcfg_pull_none>; 955 }; 956 957 i2s2m1_sdi: i2s2m1-sdi { 958 rockchip,pins = 959 <3 2 RK_FUNC_6 &pcfg_pull_none>; 960 }; 961 962 i2s2m1_sdo: i2s2m1-sdo { 963 rockchip,pins = 964 <3 1 RK_FUNC_6 &pcfg_pull_none>; 965 }; 966 967 i2s2m1_sleep: i2s2m1-sleep { 968 rockchip,pins = 969 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 970 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 971 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 972 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 973 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 974 }; 975 }; 976 977 spdif-0 { 978 spdifm0_tx: spdifm0-tx { 979 rockchip,pins = 980 <0 27 RK_FUNC_1 &pcfg_pull_none>; 981 }; 982 }; 983 984 spdif-1 { 985 spdifm1_tx: spdifm1-tx { 986 rockchip,pins = 987 <2 17 RK_FUNC_2 &pcfg_pull_none>; 988 }; 989 }; 990 991 spdif-2 { 992 spdifm2_tx: spdifm2-tx { 993 rockchip,pins = 994 <0 2 RK_FUNC_2 &pcfg_pull_none>; 995 }; 996 }; 997 998 sdmmc0-0 { 999 sdmmc0m0_pwren: sdmmc0m0-pwren { 1000 rockchip,pins = 1001 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1002 }; 1003 1004 sdmmc0m0_gpio: sdmmc0m0-gpio { 1005 rockchip,pins = 1006 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1007 }; 1008 }; 1009 1010 sdmmc0-1 { 1011 sdmmc0m1_pwren: sdmmc0m1-pwren { 1012 rockchip,pins = 1013 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1014 }; 1015 1016 sdmmc0m1_gpio: sdmmc0m1-gpio { 1017 rockchip,pins = 1018 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1019 }; 1020 }; 1021 1022 sdmmc0 { 1023 sdmmc0_clk: sdmmc0-clk { 1024 rockchip,pins = 1025 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1026 }; 1027 1028 sdmmc0_cmd: sdmmc0-cmd { 1029 rockchip,pins = 1030 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1031 }; 1032 1033 sdmmc0_dectn: sdmmc0-dectn { 1034 rockchip,pins = 1035 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1036 }; 1037 1038 sdmmc0_wrprt: sdmmc0-wrprt { 1039 rockchip,pins = 1040 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1041 }; 1042 1043 sdmmc0_bus1: sdmmc0-bus1 { 1044 rockchip,pins = 1045 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1046 }; 1047 1048 sdmmc0_bus4: sdmmc0-bus4 { 1049 rockchip,pins = 1050 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1051 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1052 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1053 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1054 }; 1055 1056 sdmmc0_gpio: sdmmc0-gpio { 1057 rockchip,pins = 1058 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1059 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1060 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1061 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1062 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1063 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1064 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1065 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1066 }; 1067 }; 1068 1069 sdmmc0ext { 1070 sdmmc0ext_clk: sdmmc0ext-clk { 1071 rockchip,pins = 1072 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1073 }; 1074 1075 sdmmc0ext_cmd: sdmmc0ext-cmd { 1076 rockchip,pins = 1077 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1078 }; 1079 1080 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1081 rockchip,pins = 1082 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1083 }; 1084 1085 sdmmc0ext_dectn: sdmmc0ext-dectn { 1086 rockchip,pins = 1087 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1088 }; 1089 1090 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1091 rockchip,pins = 1092 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1093 }; 1094 1095 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1096 rockchip,pins = 1097 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1098 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1099 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1100 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1101 }; 1102 1103 sdmmc0ext_gpio: sdmmc0ext-gpio { 1104 rockchip,pins = 1105 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1106 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1107 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1108 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1109 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1110 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1111 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1112 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1113 }; 1114 }; 1115 1116 sdmmc1 { 1117 sdmmc1_clk: sdmmc1-clk { 1118 rockchip,pins = 1119 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1120 }; 1121 1122 sdmmc1_cmd: sdmmc1-cmd { 1123 rockchip,pins = 1124 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1125 }; 1126 1127 sdmmc1_pwren: sdmmc1-pwren { 1128 rockchip,pins = 1129 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1130 }; 1131 1132 sdmmc1_wrprt: sdmmc1-wrprt { 1133 rockchip,pins = 1134 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1135 }; 1136 1137 sdmmc1_dectn: sdmmc1-dectn { 1138 rockchip,pins = 1139 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1140 }; 1141 1142 sdmmc1_bus1: sdmmc1-bus1 { 1143 rockchip,pins = 1144 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1145 }; 1146 1147 sdmmc1_bus4: sdmmc1-bus4 { 1148 rockchip,pins = 1149 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1150 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1151 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1152 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1153 }; 1154 1155 sdmmc1_gpio: sdmmc1-gpio { 1156 rockchip,pins = 1157 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1158 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1159 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1160 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1161 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1162 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1163 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1164 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1165 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1166 }; 1167 }; 1168 1169 emmc { 1170 emmc_clk: emmc-clk { 1171 rockchip,pins = 1172 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1173 }; 1174 1175 emmc_cmd: emmc-cmd { 1176 rockchip,pins = 1177 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1178 }; 1179 1180 emmc_pwren: emmc-pwren { 1181 rockchip,pins = 1182 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1183 }; 1184 1185 emmc_rstnout: emmc-rstnout { 1186 rockchip,pins = 1187 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1188 }; 1189 1190 emmc_bus1: emmc-bus1 { 1191 rockchip,pins = 1192 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1193 }; 1194 1195 emmc_bus4: emmc-bus4 { 1196 rockchip,pins = 1197 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1198 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1199 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1200 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1201 }; 1202 1203 emmc_bus8: emmc-bus8 { 1204 rockchip,pins = 1205 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1206 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1207 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1208 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1209 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1210 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1211 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1212 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1213 }; 1214 }; 1215 1216 pwm0 { 1217 pwm0_pin: pwm0-pin { 1218 rockchip,pins = 1219 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1220 }; 1221 }; 1222 1223 pwm1 { 1224 pwm1_pin: pwm1-pin { 1225 rockchip,pins = 1226 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1227 }; 1228 }; 1229 1230 pwm2 { 1231 pwm2_pin: pwm2-pin { 1232 rockchip,pins = 1233 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1234 }; 1235 }; 1236 1237 pwmir { 1238 pwmir_pin: pwmir-pin { 1239 rockchip,pins = 1240 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1241 }; 1242 }; 1243 1244 gmac-0 { 1245 rgmiim0_pins: rgmiim0-pins { 1246 rockchip,pins = 1247 /* mac_txclk */ 1248 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1249 /* mac_rxclk */ 1250 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1251 /* mac_mdio */ 1252 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1253 /* mac_txen */ 1254 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1255 /* mac_clk */ 1256 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1257 /* mac_rxdv */ 1258 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1259 /* mac_mdc */ 1260 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1261 /* mac_rxd1 */ 1262 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1263 /* mac_rxd0 */ 1264 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1265 /* mac_txd1 */ 1266 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1267 /* mac_txd0 */ 1268 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1269 /* mac_rxd3 */ 1270 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1271 /* mac_rxd2 */ 1272 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1273 /* mac_txd3 */ 1274 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1275 /* mac_txd2 */ 1276 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1277 }; 1278 1279 rmiim0_pins: rmiim0-pins { 1280 rockchip,pins = 1281 /* mac_mdio */ 1282 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1283 /* mac_txen */ 1284 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1285 /* mac_clk */ 1286 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1287 /* mac_rxer */ 1288 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1289 /* mac_rxdv */ 1290 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1291 /* mac_mdc */ 1292 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1293 /* mac_rxd1 */ 1294 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1295 /* mac_rxd0 */ 1296 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1297 /* mac_txd1 */ 1298 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1299 /* mac_txd0 */ 1300 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1301 }; 1302 }; 1303 1304 gmac-1 { 1305 rgmiim1_pins: rgmiim1-pins { 1306 rockchip,pins = 1307 /* mac_txclk */ 1308 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1309 /* mac_rxclk */ 1310 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1311 /* mac_mdio */ 1312 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1313 /* mac_txen */ 1314 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1315 /* mac_clk */ 1316 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1317 /* mac_rxdv */ 1318 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1319 /* mac_mdc */ 1320 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1321 /* mac_rxd1 */ 1322 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1323 /* mac_rxd0 */ 1324 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1325 /* mac_txd1 */ 1326 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1327 /* mac_txd0 */ 1328 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1329 /* mac_rxd3 */ 1330 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1331 /* mac_rxd2 */ 1332 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1333 /* mac_txd3 */ 1334 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1335 /* mac_txd2 */ 1336 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1337 1338 /* mac_txclk */ 1339 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1340 /* mac_txen */ 1341 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1342 /* mac_clk */ 1343 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1344 /* mac_txd1 */ 1345 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1346 /* mac_txd0 */ 1347 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1348 /* mac_txd3 */ 1349 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1350 /* mac_txd2 */ 1351 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1352 }; 1353 1354 rmiim1_pins: rmiim1-pins { 1355 rockchip,pins = 1356 /* mac_mdio */ 1357 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1358 /* mac_txen */ 1359 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1360 /* mac_clk */ 1361 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1362 /* mac_rxer */ 1363 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1364 /* mac_rxdv */ 1365 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1366 /* mac_mdc */ 1367 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1368 /* mac_rxd1 */ 1369 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1370 /* mac_rxd0 */ 1371 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1372 /* mac_txd1 */ 1373 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1374 /* mac_txd0 */ 1375 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1376 1377 /* mac_mdio */ 1378 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1379 /* mac_txen */ 1380 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1381 /* mac_clk */ 1382 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1383 /* mac_mdc */ 1384 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1385 /* mac_txd1 */ 1386 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1387 /* mac_txd0 */ 1388 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1389 }; 1390 }; 1391 1392 gmac2phy { 1393 fephyled_speed100: fephyled-speed100 { 1394 rockchip,pins = 1395 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1396 }; 1397 1398 fephyled_speed10: fephyled-speed10 { 1399 rockchip,pins = 1400 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1401 }; 1402 1403 fephyled_duplex: fephyled-duplex { 1404 rockchip,pins = 1405 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1406 }; 1407 1408 fephyled_rxm0: fephyled-rxm0 { 1409 rockchip,pins = 1410 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1411 }; 1412 1413 fephyled_txm0: fephyled-txm0 { 1414 rockchip,pins = 1415 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1416 }; 1417 1418 fephyled_linkm0: fephyled-linkm0 { 1419 rockchip,pins = 1420 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1421 }; 1422 1423 fephyled_rxm1: fephyled-rxm1 { 1424 rockchip,pins = 1425 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1426 }; 1427 1428 fephyled_txm1: fephyled-txm1 { 1429 rockchip,pins = 1430 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1431 }; 1432 1433 fephyled_linkm1: fephyled-linkm1 { 1434 rockchip,pins = 1435 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1436 }; 1437 }; 1438 1439 tsadc_pin { 1440 tsadc_int: tsadc-int { 1441 rockchip,pins = 1442 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1443 }; 1444 tsadc_gpio: tsadc-gpio { 1445 rockchip,pins = 1446 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1447 }; 1448 }; 1449 1450 hdmi_pin { 1451 hdmi_cec: hdmi-cec { 1452 rockchip,pins = 1453 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1454 }; 1455 1456 hdmi_hpd: hdmi-hpd { 1457 rockchip,pins = 1458 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1459 }; 1460 }; 1461 1462 cif-0 { 1463 dvp_d2d9_m0:dvp-d2d9-m0 { 1464 rockchip,pins = 1465 /* cif_d0 */ 1466 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1467 /* cif_d1 */ 1468 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1469 /* cif_d2 */ 1470 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1471 /* cif_d3 */ 1472 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1473 /* cif_d4 */ 1474 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1475 /* cif_d5m0 */ 1476 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1477 /* cif_d6m0 */ 1478 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1479 /* cif_d7m0 */ 1480 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1481 /* cif_href */ 1482 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1483 /* cif_vsync */ 1484 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1485 /* cif_clkoutm0 */ 1486 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1487 /* cif_clkin */ 1488 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1489 }; 1490 }; 1491 1492 cif-1 { 1493 dvp_d2d9_m1:dvp-d2d9-m1 { 1494 rockchip,pins = 1495 /* cif_d0 */ 1496 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1497 /* cif_d1 */ 1498 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1499 /* cif_d2 */ 1500 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1501 /* cif_d3 */ 1502 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1503 /* cif_d4 */ 1504 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1505 /* cif_d5m1 */ 1506 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1507 /* cif_d6m1 */ 1508 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1509 /* cif_d7m1 */ 1510 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1511 /* cif_href */ 1512 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1513 /* cif_vsync */ 1514 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1515 /* cif_clkoutm1 */ 1516 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1517 /* cif_clkin */ 1518 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1519 }; 1520 }; 1521 }; 1522}; 1523