1/* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/clock/rk3328-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13/ { 14 compatible = "rockchip,rk3328"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53", "arm,armv8"; 37 reg = <0x0 0x0>; 38 enable-method = "psci"; 39// clocks = <&cru ARMCLK>; 40 operating-points-v2 = <&cpu0_opp_table>; 41 }; 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <0x0 0x1>; 46 enable-method = "psci"; 47 }; 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53", "arm,armv8"; 51 reg = <0x0 0x2>; 52 enable-method = "psci"; 53 }; 54 cpu3: cpu@3 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53", "arm,armv8"; 57 reg = <0x0 0x3>; 58 enable-method = "psci"; 59 }; 60 }; 61 62 cpu0_opp_table: opp_table0 { 63 compatible = "operating-points-v2"; 64 opp-shared; 65 66 opp@408000000 { 67 opp-hz = /bits/ 64 <408000000>; 68 opp-microvolt = <950000>; 69 clock-latency-ns = <40000>; 70 opp-suspend; 71 }; 72 opp@600000000 { 73 opp-hz = /bits/ 64 <600000000>; 74 opp-microvolt = <950000>; 75 clock-latency-ns = <40000>; 76 }; 77 opp@816000000 { 78 opp-hz = /bits/ 64 <816000000>; 79 opp-microvolt = <1000000>; 80 clock-latency-ns = <40000>; 81 }; 82 opp@1008000000 { 83 opp-hz = /bits/ 64 <1008000000>; 84 opp-microvolt = <1100000>; 85 clock-latency-ns = <40000>; 86 }; 87 opp@1200000000 { 88 opp-hz = /bits/ 64 <1200000000>; 89 opp-microvolt = <1225000>; 90 clock-latency-ns = <40000>; 91 }; 92 opp@1296000000 { 93 opp-hz = /bits/ 64 <1296000000>; 94 opp-microvolt = <1300000>; 95 clock-latency-ns = <40000>; 96 }; 97 }; 98 99 arm-pmu { 100 compatible = "arm,cortex-a53-pmu"; 101 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 106 }; 107 108 psci { 109 compatible = "arm,psci-1.0"; 110 method = "smc"; 111 }; 112 113 timer { 114 compatible = "arm,armv8-timer"; 115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 119 }; 120 121 xin24m: xin24m { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <24000000>; 125 clock-output-names = "xin24m"; 126 }; 127 128 i2s0: i2s@ff000000 { 129 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 130 reg = <0x0 0xff000000 0x0 0x1000>; 131 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 133 clock-names = "i2s_clk", "i2s_hclk"; 134 dmas = <&dmac 11>, <&dmac 12>; 135 #dma-cells = <2>; 136 dma-names = "tx", "rx"; 137 status = "disabled"; 138 }; 139 140 i2s1: i2s@ff010000 { 141 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 142 reg = <0x0 0xff010000 0x0 0x1000>; 143 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 145 clock-names = "i2s_clk", "i2s_hclk"; 146 dmas = <&dmac 14>, <&dmac 15>; 147 #dma-cells = <2>; 148 dma-names = "tx", "rx"; 149 status = "disabled"; 150 }; 151 152 i2s2: i2s@ff020000 { 153 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 154 reg = <0x0 0xff020000 0x0 0x1000>; 155 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 157 clock-names = "i2s_clk", "i2s_hclk"; 158 dmas = <&dmac 0>, <&dmac 1>; 159 #dma-cells = <2>; 160 dma-names = "tx", "rx"; 161 pinctrl-names = "default", "sleep"; 162 pinctrl-0 = <&i2s2m0_mclk 163 &i2s2m0_sclk 164 &i2s2m0_lrcktx 165 &i2s2m0_lrckrx 166 &i2s2m0_sdo 167 &i2s2m0_sdi>; 168 pinctrl-1 = <&i2s2m0_sleep>; 169 status = "disabled"; 170 }; 171 172 spdif: spdif@ff030000 { 173 compatible = "rockchip,rk3328-spdif"; 174 reg = <0x0 0xff030000 0x0 0x1000>; 175 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 177 clock-names = "mclk", "hclk"; 178 dmas = <&dmac 10>; 179 #dma-cells = <1>; 180 dma-names = "tx"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&spdifm2_tx>; 183 status = "disabled"; 184 }; 185 186 grf: syscon@ff100000 { 187 u-boot,dm-pre-reloc; 188 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 189 reg = <0x0 0xff100000 0x0 0x1000>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 193 io_domains: io-domains { 194 compatible = "rockchip,rk3328-io-voltage-domain"; 195 status = "disabled"; 196 }; 197 }; 198 199 uart0: serial@ff110000 { 200 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 201 reg = <0x0 0xff110000 0x0 0x100>; 202 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 204 clock-names = "baudclk", "apb_pclk"; 205 reg-shift = <2>; 206 reg-io-width = <4>; 207 dmas = <&dmac 2>, <&dmac 3>; 208 #dma-cells = <2>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 211 status = "disabled"; 212 }; 213 214 uart1: serial@ff120000 { 215 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 216 reg = <0x0 0xff120000 0x0 0x100>; 217 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 219 clock-names = "sclk_uart", "pclk_uart"; 220 reg-shift = <2>; 221 reg-io-width = <4>; 222 dmas = <&dmac 4>, <&dmac 5>; 223 #dma-cells = <2>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 226 status = "disabled"; 227 }; 228 229 uart2: serial@ff130000 { 230 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 231 reg = <0x0 0xff130000 0x0 0x100>; 232 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 234 clock-names = "baudclk", "apb_pclk"; 235 clock-frequency = <24000000>; 236 reg-shift = <2>; 237 reg-io-width = <4>; 238 dmas = <&dmac 6>, <&dmac 7>; 239 #dma-cells = <2>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&uart2m1_xfer>; 242 status = "disabled"; 243 }; 244 245 pmu: power-management@ff140000 { 246 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; 247 reg = <0x0 0xff140000 0x0 0x1000>; 248 }; 249 250 i2c0: i2c@ff150000 { 251 compatible = "rockchip,rk3328-i2c"; 252 reg = <0x0 0xff150000 0x0 0x1000>; 253 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 257 clock-names = "i2c", "pclk"; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&i2c0_xfer>; 260 status = "disabled"; 261 }; 262 263 i2c1: i2c@ff160000 { 264 compatible = "rockchip,rk3328-i2c"; 265 reg = <0x0 0xff160000 0x0 0x1000>; 266 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 270 clock-names = "i2c", "pclk"; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&i2c1_xfer>; 273 status = "disabled"; 274 }; 275 276 i2c2: i2c@ff170000 { 277 compatible = "rockchip,rk3328-i2c"; 278 reg = <0x0 0xff170000 0x0 0x1000>; 279 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 283 clock-names = "i2c", "pclk"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&i2c2_xfer>; 286 status = "disabled"; 287 }; 288 289 i2c3: i2c@ff180000 { 290 compatible = "rockchip,rk3328-i2c"; 291 reg = <0x0 0xff180000 0x0 0x1000>; 292 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 296 clock-names = "i2c", "pclk"; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&i2c3_xfer>; 299 status = "disabled"; 300 }; 301 302 spi0: spi@ff190000 { 303 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 304 reg = <0x0 0xff190000 0x0 0x1000>; 305 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 309 clock-names = "spiclk", "apb_pclk"; 310 dmas = <&dmac 8>, <&dmac 9>; 311 #dma-cells = <2>; 312 dma-names = "tx", "rx"; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 315 status = "disabled"; 316 }; 317 318 wdt: watchdog@ff1a0000 { 319 compatible = "snps,dw-wdt"; 320 reg = <0x0 0xff1a0000 0x0 0x100>; 321 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 322 status = "disabled"; 323 }; 324 325 amba { 326 compatible = "simple-bus"; 327 #address-cells = <2>; 328 #size-cells = <2>; 329 ranges; 330 331 dmac: dmac@ff1f0000 { 332 compatible = "arm,pl330", "arm,primecell"; 333 reg = <0x0 0xff1f0000 0x0 0x4000>; 334 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&cru ACLK_DMAC>; 337 clock-names = "apb_pclk"; 338 #dma-cells = <1>; 339 }; 340 }; 341 342 saradc: saradc@ff280000 { 343 compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; 344 reg = <0x0 0xff280000 0x0 0x100>; 345 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 346 #io-channel-cells = <1>; 347 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 348 clock-names = "saradc", "apb_pclk"; 349 resets = <&cru SRST_SARADC_P>; 350 reset-names = "saradc-apb"; 351 status = "disabled"; 352 }; 353 354 dmc: dmc@ff400000 { 355 u-boot,dm-pre-reloc; 356 compatible = "rockchip,rk3328-dmc", "syscon"; 357 reg = <0x0 0xff400000 0x0 0x1000>; 358 }; 359 360 cru: clock-controller@ff440000 { 361 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 362 reg = <0x0 0xff440000 0x0 0x1000>; 363 rockchip,grf = <&grf>; 364 #clock-cells = <1>; 365 #reset-cells = <1>; 366 assigned-clocks = 367 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 368 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 369 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 370 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 371 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 372 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 373 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 374 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 375 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 376 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 377 <&cru SCLK_WIFI>, <&cru ARMCLK>, 378 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 379 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 380 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 381 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 382 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, 383 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, 384 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 385 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 386 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 387 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 388 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, 389 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 390 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; 391 assigned-clock-parents = 392 <&cru HDMIPHY>, <&cru PLL_APLL>, 393 <&cru PLL_GPLL>, <&xin24m>, 394 <&xin24m>, <&xin24m>; 395 assigned-clock-rates = 396 <0>, <61440000>, 397 <0>, <24000000>, 398 <24000000>, <24000000>, 399 <15000000>, <15000000>, 400 <100000000>, <100000000>, 401 <100000000>, <100000000>, 402 <50000000>, <100000000>, 403 <100000000>, <100000000>, 404 <50000000>, <50000000>, 405 <50000000>, <50000000>, 406 <24000000>, <600000000>, 407 <491520000>, <1200000000>, 408 <150000000>, <75000000>, 409 <75000000>, <150000000>, 410 <75000000>, <75000000>, 411 <300000000>, <100000000>, 412 <300000000>, <200000000>, 413 <400000000>, <500000000>, 414 <200000000>, <300000000>, 415 <300000000>, <250000000>, 416 <200000000>, <100000000>, 417 <24000000>, <100000000>, 418 <150000000>, <50000000>, 419 <32768>, <32768>; 420 }; 421 422 sdmmc: rksdmmc@ff500000 { 423 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 424 reg = <0x0 0xff500000 0x0 0x4000>; 425 clock-freq-min-max = <400000 150000000>; 426 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 427 clock-names = "biu", "ciu"; 428 fifo-depth = <0x100>; 429 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 430 status = "disabled"; 431 }; 432 433 sdio: dwmmc@ff510000 { 434 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 435 reg = <0x0 0xff510000 0x0 0x4000>; 436 clock-freq-min-max = <400000 150000000>; 437 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 438 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 439 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 440 fifo-depth = <0x100>; 441 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 442 status = "disabled"; 443 }; 444 445 emmc: rksdmmc@ff520000 { 446 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 447 reg = <0x0 0xff520000 0x0 0x4000>; 448 clock-freq-min-max = <400000 150000000>; 449 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 450 clock-names = "biu", "ciu"; 451 fifo-depth = <0x100>; 452 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 453 status = "disabled"; 454 }; 455 456 usb_host0_ehci: usb@ff5c0000 { 457 compatible = "generic-ehci"; 458 reg = <0x0 0xff5c0000 0x0 0x10000>; 459 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 460 status = "disabled"; 461 }; 462 463 usb_host0_ohci: usb@ff5d0000 { 464 compatible = "generic-ohci"; 465 reg = <0x0 0xff5d0000 0x0 0x10000>; 466 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 467 status = "disabled"; 468 }; 469 470 sdmmc_ext: rksdmmc@ff5f0000 { 471 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 472 reg = <0x0 0xff5f0000 0x0 0x4000>; 473 clock-freq-min-max = <400000 150000000>; 474 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 475 clock-names = "biu", "ciu"; 476 fifo-depth = <0x100>; 477 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 478 status = "disabled"; 479 }; 480 481 usb_host0_xhci: usb@ff600000 { 482 compatible = "rockchip,rk3328-xhci"; 483 reg = <0x0 0xff600000 0x0 0x100000>; 484 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 485 snps,dis-enblslpm-quirk; 486 snps,phyif-utmi-bits = <16>; 487 snps,dis-u2-freeclk-exists-quirk; 488 snps,dis-u2-susphy-quirk; 489 status = "disabled"; 490 }; 491 492 gic: interrupt-controller@ffb70000 { 493 compatible = "arm,gic-400"; 494 #interrupt-cells = <3>; 495 #address-cells = <0>; 496 interrupt-controller; 497 reg = <0x0 0xff811000 0 0x1000>, 498 <0x0 0xff812000 0 0x2000>, 499 <0x0 0xff814000 0 0x2000>, 500 <0x0 0xff816000 0 0x2000>; 501 interrupts = <GIC_PPI 9 502 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 503 }; 504 505 pinctrl: pinctrl { 506 compatible = "rockchip,rk3328-pinctrl"; 507 rockchip,grf = <&grf>; 508 #address-cells = <2>; 509 #size-cells = <2>; 510 ranges; 511 512 gpio0: gpio0@ff210000 { 513 compatible = "rockchip,gpio-bank"; 514 reg = <0x0 0xff210000 0x0 0x100>; 515 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cru PCLK_GPIO0>; 517 518 gpio-controller; 519 #gpio-cells = <2>; 520 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 }; 524 525 gpio1: gpio1@ff220000 { 526 compatible = "rockchip,gpio-bank"; 527 reg = <0x0 0xff220000 0x0 0x100>; 528 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cru PCLK_GPIO1>; 530 531 gpio-controller; 532 #gpio-cells = <2>; 533 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 538 gpio2: gpio2@ff230000 { 539 compatible = "rockchip,gpio-bank"; 540 reg = <0x0 0xff230000 0x0 0x100>; 541 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cru PCLK_GPIO2>; 543 544 gpio-controller; 545 #gpio-cells = <2>; 546 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 }; 550 551 gpio3: gpio3@ff240000 { 552 compatible = "rockchip,gpio-bank"; 553 reg = <0x0 0xff240000 0x0 0x100>; 554 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cru PCLK_GPIO3>; 556 557 gpio-controller; 558 #gpio-cells = <2>; 559 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 }; 563 564 pcfg_pull_up: pcfg-pull-up { 565 bias-pull-up; 566 }; 567 568 pcfg_pull_down: pcfg-pull-down { 569 bias-pull-down; 570 }; 571 572 pcfg_pull_none: pcfg-pull-none { 573 bias-disable; 574 }; 575 576 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 577 bias-disable; 578 drive-strength = <2>; 579 }; 580 581 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 582 bias-pull-up; 583 drive-strength = <2>; 584 }; 585 586 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 587 bias-pull-up; 588 drive-strength = <4>; 589 }; 590 591 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 592 bias-disable; 593 drive-strength = <4>; 594 }; 595 596 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 597 bias-pull-down; 598 drive-strength = <4>; 599 }; 600 601 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 602 bias-disable; 603 drive-strength = <8>; 604 }; 605 606 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 607 bias-pull-up; 608 drive-strength = <8>; 609 }; 610 611 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 612 bias-disable; 613 drive-strength = <12>; 614 }; 615 616 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 617 bias-pull-up; 618 drive-strength = <12>; 619 }; 620 621 pcfg_output_high: pcfg-output-high { 622 output-high; 623 }; 624 625 pcfg_output_low: pcfg-output-low { 626 output-low; 627 }; 628 629 pcfg_input_high: pcfg-input-high { 630 bias-pull-up; 631 input-enable; 632 }; 633 634 pcfg_input: pcfg-input { 635 input-enable; 636 }; 637 638 i2c0 { 639 i2c0_xfer: i2c0-xfer { 640 rockchip,pins = 641 <2 24 RK_FUNC_1 &pcfg_pull_none>, 642 <2 25 RK_FUNC_1 &pcfg_pull_none>; 643 }; 644 }; 645 646 i2c1 { 647 i2c1_xfer: i2c1-xfer { 648 rockchip,pins = 649 <2 4 RK_FUNC_2 &pcfg_pull_none>, 650 <2 5 RK_FUNC_2 &pcfg_pull_none>; 651 }; 652 }; 653 654 i2c2 { 655 i2c2_xfer: i2c2-xfer { 656 rockchip,pins = 657 <2 13 RK_FUNC_1 &pcfg_pull_none>, 658 <2 14 RK_FUNC_1 &pcfg_pull_none>; 659 }; 660 }; 661 662 i2c3 { 663 i2c3_xfer: i2c3-xfer { 664 rockchip,pins = 665 <0 5 RK_FUNC_2 &pcfg_pull_none>, 666 <0 6 RK_FUNC_2 &pcfg_pull_none>; 667 }; 668 i2c3_gpio: i2c3-gpio { 669 rockchip,pins = 670 <0 5 RK_FUNC_GPIO &pcfg_pull_none>, 671 <0 6 RK_FUNC_GPIO &pcfg_pull_none>; 672 }; 673 }; 674 675 hdmi_i2c { 676 hdmii2c_xfer: hdmii2c-xfer { 677 rockchip,pins = 678 <0 5 RK_FUNC_1 &pcfg_pull_none>, 679 <0 6 RK_FUNC_1 &pcfg_pull_none>; 680 }; 681 }; 682 683 uart0 { 684 uart0_xfer: uart0-xfer { 685 rockchip,pins = 686 <1 9 RK_FUNC_1 &pcfg_pull_up>, 687 <1 8 RK_FUNC_1 &pcfg_pull_none>; 688 }; 689 690 uart0_cts: uart0-cts { 691 rockchip,pins = 692 <1 11 RK_FUNC_1 &pcfg_pull_none>; 693 }; 694 695 uart0_rts: uart0-rts { 696 rockchip,pins = 697 <1 10 RK_FUNC_1 &pcfg_pull_none>; 698 }; 699 700 uart0_rts_gpio: uart0-rts-gpio { 701 rockchip,pins = 702 <1 10 RK_FUNC_GPIO &pcfg_pull_none>; 703 }; 704 }; 705 706 uart1 { 707 uart1_xfer: uart1-xfer { 708 rockchip,pins = 709 <3 4 RK_FUNC_4 &pcfg_pull_up>, 710 <3 6 RK_FUNC_4 &pcfg_pull_none>; 711 }; 712 713 uart1_cts: uart1-cts { 714 rockchip,pins = 715 <3 7 RK_FUNC_4 &pcfg_pull_none>; 716 }; 717 718 uart1_rts: uart1-rts { 719 rockchip,pins = 720 <3 5 RK_FUNC_4 &pcfg_pull_none>; 721 }; 722 723 uart1_rts_gpio: uart1-rts-gpio { 724 rockchip,pins = 725 <3 5 RK_FUNC_GPIO &pcfg_pull_none>; 726 }; 727 }; 728 729 uart2-0 { 730 uart2m0_xfer: uart2m0-xfer { 731 rockchip,pins = 732 <1 0 RK_FUNC_2 &pcfg_pull_up>, 733 <1 1 RK_FUNC_2 &pcfg_pull_none>; 734 }; 735 }; 736 737 uart2-1 { 738 uart2m1_xfer: uart2m1-xfer { 739 rockchip,pins = 740 <2 0 RK_FUNC_1 &pcfg_pull_up>, 741 <2 1 RK_FUNC_1 &pcfg_pull_none>; 742 }; 743 }; 744 745 spi0-0 { 746 spi0m0_clk: spi0m0-clk { 747 rockchip,pins = 748 <2 8 RK_FUNC_1 &pcfg_pull_up>; 749 }; 750 751 spi0m0_cs0: spi0m0-cs0 { 752 rockchip,pins = 753 <2 11 RK_FUNC_1 &pcfg_pull_up>; 754 }; 755 756 spi0m0_tx: spi0m0-tx { 757 rockchip,pins = 758 <2 9 RK_FUNC_1 &pcfg_pull_up>; 759 }; 760 761 spi0m0_rx: spi0m0-rx { 762 rockchip,pins = 763 <2 10 RK_FUNC_1 &pcfg_pull_up>; 764 }; 765 766 spi0m0_cs1: spi0m0-cs1 { 767 rockchip,pins = 768 <2 12 RK_FUNC_1 &pcfg_pull_up>; 769 }; 770 }; 771 772 spi0-1 { 773 spi0m1_clk: spi0m1-clk { 774 rockchip,pins = 775 <3 23 RK_FUNC_2 &pcfg_pull_up>; 776 }; 777 778 spi0m1_cs0: spi0m1-cs0 { 779 rockchip,pins = 780 <3 26 RK_FUNC_2 &pcfg_pull_up>; 781 }; 782 783 spi0m1_tx: spi0m1-tx { 784 rockchip,pins = 785 <3 25 RK_FUNC_2 &pcfg_pull_up>; 786 }; 787 788 spi0m1_rx: spi0m1-rx { 789 rockchip,pins = 790 <3 24 RK_FUNC_2 &pcfg_pull_up>; 791 }; 792 793 spi0m1_cs1: spi0m1-cs1 { 794 rockchip,pins = 795 <3 27 RK_FUNC_2 &pcfg_pull_up>; 796 }; 797 }; 798 799 spi0-2 { 800 spi0m2_clk: spi0m2-clk { 801 rockchip,pins = 802 <3 0 RK_FUNC_4 &pcfg_pull_up>; 803 }; 804 805 spi0m2_cs0: spi0m2-cs0 { 806 rockchip,pins = 807 <3 8 RK_FUNC_3 &pcfg_pull_up>; 808 }; 809 810 spi0m2_tx: spi0m2-tx { 811 rockchip,pins = 812 <3 1 RK_FUNC_4 &pcfg_pull_up>; 813 }; 814 815 spi0m2_rx: spi0m2-rx { 816 rockchip,pins = 817 <3 2 RK_FUNC_4 &pcfg_pull_up>; 818 }; 819 }; 820 821 i2s1 { 822 i2s1_mclk: i2s1-mclk { 823 rockchip,pins = 824 <2 15 RK_FUNC_1 &pcfg_pull_none>; 825 }; 826 827 i2s1_sclk: i2s1-sclk { 828 rockchip,pins = 829 <2 18 RK_FUNC_1 &pcfg_pull_none>; 830 }; 831 832 i2s1_lrckrx: i2s1-lrckrx { 833 rockchip,pins = 834 <2 16 RK_FUNC_1 &pcfg_pull_none>; 835 }; 836 837 i2s1_lrcktx: i2s1-lrcktx { 838 rockchip,pins = 839 <2 17 RK_FUNC_1 &pcfg_pull_none>; 840 }; 841 842 i2s1_sdi: i2s1-sdi { 843 rockchip,pins = 844 <2 19 RK_FUNC_1 &pcfg_pull_none>; 845 }; 846 847 i2s1_sdo: i2s1-sdo { 848 rockchip,pins = 849 <2 23 RK_FUNC_1 &pcfg_pull_none>; 850 }; 851 852 i2s1_sdio1: i2s1-sdio1 { 853 rockchip,pins = 854 <2 20 RK_FUNC_1 &pcfg_pull_none>; 855 }; 856 857 i2s1_sdio2: i2s1-sdio2 { 858 rockchip,pins = 859 <2 21 RK_FUNC_1 &pcfg_pull_none>; 860 }; 861 862 i2s1_sdio3: i2s1-sdio3 { 863 rockchip,pins = 864 <2 22 RK_FUNC_1 &pcfg_pull_none>; 865 }; 866 867 i2s1_sleep: i2s1-sleep { 868 rockchip,pins = 869 <2 15 RK_FUNC_GPIO &pcfg_input_high>, 870 <2 16 RK_FUNC_GPIO &pcfg_input_high>, 871 <2 17 RK_FUNC_GPIO &pcfg_input_high>, 872 <2 18 RK_FUNC_GPIO &pcfg_input_high>, 873 <2 19 RK_FUNC_GPIO &pcfg_input_high>, 874 <2 20 RK_FUNC_GPIO &pcfg_input_high>, 875 <2 21 RK_FUNC_GPIO &pcfg_input_high>, 876 <2 22 RK_FUNC_GPIO &pcfg_input_high>, 877 <2 23 RK_FUNC_GPIO &pcfg_input_high>; 878 }; 879 }; 880 881 i2s2-0 { 882 i2s2m0_mclk: i2s2m0-mclk { 883 rockchip,pins = 884 <1 21 RK_FUNC_1 &pcfg_pull_none>; 885 }; 886 887 i2s2m0_sclk: i2s2m0-sclk { 888 rockchip,pins = 889 <1 22 RK_FUNC_1 &pcfg_pull_none>; 890 }; 891 892 i2s2m0_lrckrx: i2s2m0-lrckrx { 893 rockchip,pins = 894 <1 26 RK_FUNC_1 &pcfg_pull_none>; 895 }; 896 897 i2s2m0_lrcktx: i2s2m0-lrcktx { 898 rockchip,pins = 899 <1 23 RK_FUNC_1 &pcfg_pull_none>; 900 }; 901 902 i2s2m0_sdi: i2s2m0-sdi { 903 rockchip,pins = 904 <1 24 RK_FUNC_1 &pcfg_pull_none>; 905 }; 906 907 i2s2m0_sdo: i2s2m0-sdo { 908 rockchip,pins = 909 <1 25 RK_FUNC_1 &pcfg_pull_none>; 910 }; 911 912 i2s2m0_sleep: i2s2m0-sleep { 913 rockchip,pins = 914 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 915 <1 22 RK_FUNC_GPIO &pcfg_input_high>, 916 <1 26 RK_FUNC_GPIO &pcfg_input_high>, 917 <1 23 RK_FUNC_GPIO &pcfg_input_high>, 918 <1 24 RK_FUNC_GPIO &pcfg_input_high>, 919 <1 25 RK_FUNC_GPIO &pcfg_input_high>; 920 }; 921 }; 922 923 i2s2-1 { 924 i2s2m1_mclk: i2s2m1-mclk { 925 rockchip,pins = 926 <1 21 RK_FUNC_1 &pcfg_pull_none>; 927 }; 928 929 i2s2m1_sclk: i2s2m1-sclk { 930 rockchip,pins = 931 <3 0 RK_FUNC_6 &pcfg_pull_none>; 932 }; 933 934 i2s2m1_lrckrx: i2sm1-lrckrx { 935 rockchip,pins = 936 <3 8 RK_FUNC_6 &pcfg_pull_none>; 937 }; 938 939 i2s2m1_lrcktx: i2s2m1-lrcktx { 940 rockchip,pins = 941 <3 8 RK_FUNC_4 &pcfg_pull_none>; 942 }; 943 944 i2s2m1_sdi: i2s2m1-sdi { 945 rockchip,pins = 946 <3 2 RK_FUNC_6 &pcfg_pull_none>; 947 }; 948 949 i2s2m1_sdo: i2s2m1-sdo { 950 rockchip,pins = 951 <3 1 RK_FUNC_6 &pcfg_pull_none>; 952 }; 953 954 i2s2m1_sleep: i2s2m1-sleep { 955 rockchip,pins = 956 <1 21 RK_FUNC_GPIO &pcfg_input_high>, 957 <3 0 RK_FUNC_GPIO &pcfg_input_high>, 958 <3 8 RK_FUNC_GPIO &pcfg_input_high>, 959 <3 2 RK_FUNC_GPIO &pcfg_input_high>, 960 <3 1 RK_FUNC_GPIO &pcfg_input_high>; 961 }; 962 }; 963 964 spdif-0 { 965 spdifm0_tx: spdifm0-tx { 966 rockchip,pins = 967 <0 27 RK_FUNC_1 &pcfg_pull_none>; 968 }; 969 }; 970 971 spdif-1 { 972 spdifm1_tx: spdifm1-tx { 973 rockchip,pins = 974 <2 17 RK_FUNC_2 &pcfg_pull_none>; 975 }; 976 }; 977 978 spdif-2 { 979 spdifm2_tx: spdifm2-tx { 980 rockchip,pins = 981 <0 2 RK_FUNC_2 &pcfg_pull_none>; 982 }; 983 }; 984 985 sdmmc0-0 { 986 sdmmc0m0_pwren: sdmmc0m0-pwren { 987 rockchip,pins = 988 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 989 }; 990 991 sdmmc0m0_gpio: sdmmc0m0-gpio { 992 rockchip,pins = 993 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 994 }; 995 }; 996 997 sdmmc0-1 { 998 sdmmc0m1_pwren: sdmmc0m1-pwren { 999 rockchip,pins = 1000 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; 1001 }; 1002 1003 sdmmc0m1_gpio: sdmmc0m1-gpio { 1004 rockchip,pins = 1005 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1006 }; 1007 }; 1008 1009 sdmmc0 { 1010 sdmmc0_clk: sdmmc0-clk { 1011 rockchip,pins = 1012 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; 1013 }; 1014 1015 sdmmc0_cmd: sdmmc0-cmd { 1016 rockchip,pins = 1017 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; 1018 }; 1019 1020 sdmmc0_dectn: sdmmc0-dectn { 1021 rockchip,pins = 1022 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; 1023 }; 1024 1025 sdmmc0_wrprt: sdmmc0-wrprt { 1026 rockchip,pins = 1027 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; 1028 }; 1029 1030 sdmmc0_bus1: sdmmc0-bus1 { 1031 rockchip,pins = 1032 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; 1033 }; 1034 1035 sdmmc0_bus4: sdmmc0-bus4 { 1036 rockchip,pins = 1037 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, 1038 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, 1039 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, 1040 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; 1041 }; 1042 1043 sdmmc0_gpio: sdmmc0-gpio { 1044 rockchip,pins = 1045 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1046 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1047 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1048 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1049 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1050 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1051 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1052 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1053 }; 1054 }; 1055 1056 sdmmc0ext { 1057 sdmmc0ext_clk: sdmmc0ext-clk { 1058 rockchip,pins = 1059 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; 1060 }; 1061 1062 sdmmc0ext_cmd: sdmmc0ext-cmd { 1063 rockchip,pins = 1064 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; 1065 }; 1066 1067 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1068 rockchip,pins = 1069 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; 1070 }; 1071 1072 sdmmc0ext_dectn: sdmmc0ext-dectn { 1073 rockchip,pins = 1074 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; 1075 }; 1076 1077 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1078 rockchip,pins = 1079 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; 1080 }; 1081 1082 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1083 rockchip,pins = 1084 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, 1085 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, 1086 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, 1087 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; 1088 }; 1089 1090 sdmmc0ext_gpio: sdmmc0ext-gpio { 1091 rockchip,pins = 1092 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1093 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1094 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1095 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1096 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1097 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1098 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1099 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1100 }; 1101 }; 1102 1103 sdmmc1 { 1104 sdmmc1_clk: sdmmc1-clk { 1105 rockchip,pins = 1106 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1107 }; 1108 1109 sdmmc1_cmd: sdmmc1-cmd { 1110 rockchip,pins = 1111 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; 1112 }; 1113 1114 sdmmc1_pwren: sdmmc1-pwren { 1115 rockchip,pins = 1116 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; 1117 }; 1118 1119 sdmmc1_wrprt: sdmmc1-wrprt { 1120 rockchip,pins = 1121 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; 1122 }; 1123 1124 sdmmc1_dectn: sdmmc1-dectn { 1125 rockchip,pins = 1126 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; 1127 }; 1128 1129 sdmmc1_bus1: sdmmc1-bus1 { 1130 rockchip,pins = 1131 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; 1132 }; 1133 1134 sdmmc1_bus4: sdmmc1-bus4 { 1135 rockchip,pins = 1136 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, 1137 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, 1138 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, 1139 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; 1140 }; 1141 1142 sdmmc1_gpio: sdmmc1-gpio { 1143 rockchip,pins = 1144 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1145 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1146 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1147 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1148 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1149 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1150 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1151 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1152 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1153 }; 1154 }; 1155 1156 emmc { 1157 emmc_clk: emmc-clk { 1158 rockchip,pins = 1159 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; 1160 }; 1161 1162 emmc_cmd: emmc-cmd { 1163 rockchip,pins = 1164 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; 1165 }; 1166 1167 emmc_pwren: emmc-pwren { 1168 rockchip,pins = 1169 <3 22 RK_FUNC_2 &pcfg_pull_none>; 1170 }; 1171 1172 emmc_rstnout: emmc-rstnout { 1173 rockchip,pins = 1174 <3 20 RK_FUNC_2 &pcfg_pull_none>; 1175 }; 1176 1177 emmc_bus1: emmc-bus1 { 1178 rockchip,pins = 1179 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; 1180 }; 1181 1182 emmc_bus4: emmc-bus4 { 1183 rockchip,pins = 1184 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1185 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1186 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1187 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; 1188 }; 1189 1190 emmc_bus8: emmc-bus8 { 1191 rockchip,pins = 1192 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, 1193 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, 1194 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, 1195 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, 1196 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, 1197 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, 1198 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, 1199 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; 1200 }; 1201 }; 1202 1203 pwm0 { 1204 pwm0_pin: pwm0-pin { 1205 rockchip,pins = 1206 <2 4 RK_FUNC_1 &pcfg_pull_none>; 1207 }; 1208 }; 1209 1210 pwm1 { 1211 pwm1_pin: pwm1-pin { 1212 rockchip,pins = 1213 <2 5 RK_FUNC_1 &pcfg_pull_none>; 1214 }; 1215 }; 1216 1217 pwm2 { 1218 pwm2_pin: pwm2-pin { 1219 rockchip,pins = 1220 <2 6 RK_FUNC_1 &pcfg_pull_none>; 1221 }; 1222 }; 1223 1224 pwmir { 1225 pwmir_pin: pwmir-pin { 1226 rockchip,pins = 1227 <2 2 RK_FUNC_1 &pcfg_pull_none>; 1228 }; 1229 }; 1230 1231 gmac-0 { 1232 rgmiim0_pins: rgmiim0-pins { 1233 rockchip,pins = 1234 /* mac_txclk */ 1235 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1236 /* mac_rxclk */ 1237 <0 10 RK_FUNC_1 &pcfg_pull_none>, 1238 /* mac_mdio */ 1239 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1240 /* mac_txen */ 1241 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1242 /* mac_clk */ 1243 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1244 /* mac_rxdv */ 1245 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1246 /* mac_mdc */ 1247 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1248 /* mac_rxd1 */ 1249 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1250 /* mac_rxd0 */ 1251 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1252 /* mac_txd1 */ 1253 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1254 /* mac_txd0 */ 1255 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, 1256 /* mac_rxd3 */ 1257 <0 20 RK_FUNC_1 &pcfg_pull_none>, 1258 /* mac_rxd2 */ 1259 <0 21 RK_FUNC_1 &pcfg_pull_none>, 1260 /* mac_txd3 */ 1261 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, 1262 /* mac_txd2 */ 1263 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; 1264 }; 1265 1266 rmiim0_pins: rmiim0-pins { 1267 rockchip,pins = 1268 /* mac_mdio */ 1269 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1270 /* mac_txen */ 1271 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, 1272 /* mac_clk */ 1273 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1274 /* mac_rxer */ 1275 <0 13 RK_FUNC_1 &pcfg_pull_none>, 1276 /* mac_rxdv */ 1277 <0 25 RK_FUNC_1 &pcfg_pull_none>, 1278 /* mac_mdc */ 1279 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1280 /* mac_rxd1 */ 1281 <0 14 RK_FUNC_1 &pcfg_pull_none>, 1282 /* mac_rxd0 */ 1283 <0 15 RK_FUNC_1 &pcfg_pull_none>, 1284 /* mac_txd1 */ 1285 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, 1286 /* mac_txd0 */ 1287 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; 1288 }; 1289 }; 1290 1291 gmac-1 { 1292 rgmiim1_pins: rgmiim1-pins { 1293 rockchip,pins = 1294 /* mac_txclk */ 1295 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, 1296 /* mac_rxclk */ 1297 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, 1298 /* mac_mdio */ 1299 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1300 /* mac_txen */ 1301 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1302 /* mac_clk */ 1303 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1304 /* mac_rxdv */ 1305 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1306 /* mac_mdc */ 1307 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1308 /* mac_rxd1 */ 1309 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1310 /* mac_rxd0 */ 1311 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1312 /* mac_txd1 */ 1313 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1314 /* mac_txd0 */ 1315 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1316 /* mac_rxd3 */ 1317 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, 1318 /* mac_rxd2 */ 1319 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, 1320 /* mac_txd3 */ 1321 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, 1322 /* mac_txd2 */ 1323 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, 1324 1325 /* mac_txclk */ 1326 <0 8 RK_FUNC_1 &pcfg_pull_none>, 1327 /* mac_txen */ 1328 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1329 /* mac_clk */ 1330 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1331 /* mac_txd1 */ 1332 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1333 /* mac_txd0 */ 1334 <0 17 RK_FUNC_1 &pcfg_pull_none>, 1335 /* mac_txd3 */ 1336 <0 23 RK_FUNC_1 &pcfg_pull_none>, 1337 /* mac_txd2 */ 1338 <0 22 RK_FUNC_1 &pcfg_pull_none>; 1339 }; 1340 1341 rmiim1_pins: rmiim1-pins { 1342 rockchip,pins = 1343 /* mac_mdio */ 1344 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, 1345 /* mac_txen */ 1346 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, 1347 /* mac_clk */ 1348 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, 1349 /* mac_rxer */ 1350 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, 1351 /* mac_rxdv */ 1352 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, 1353 /* mac_mdc */ 1354 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, 1355 /* mac_rxd1 */ 1356 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, 1357 /* mac_rxd0 */ 1358 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, 1359 /* mac_txd1 */ 1360 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, 1361 /* mac_txd0 */ 1362 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, 1363 1364 /* mac_mdio */ 1365 <0 11 RK_FUNC_1 &pcfg_pull_none>, 1366 /* mac_txen */ 1367 <0 12 RK_FUNC_1 &pcfg_pull_none>, 1368 /* mac_clk */ 1369 <0 24 RK_FUNC_1 &pcfg_pull_none>, 1370 /* mac_mdc */ 1371 <0 19 RK_FUNC_1 &pcfg_pull_none>, 1372 /* mac_txd1 */ 1373 <0 16 RK_FUNC_1 &pcfg_pull_none>, 1374 /* mac_txd0 */ 1375 <0 17 RK_FUNC_1 &pcfg_pull_none>; 1376 }; 1377 }; 1378 1379 gmac2phy { 1380 fephyled_speed100: fephyled-speed100 { 1381 rockchip,pins = 1382 <0 31 RK_FUNC_1 &pcfg_pull_none>; 1383 }; 1384 1385 fephyled_speed10: fephyled-speed10 { 1386 rockchip,pins = 1387 <0 30 RK_FUNC_1 &pcfg_pull_none>; 1388 }; 1389 1390 fephyled_duplex: fephyled-duplex { 1391 rockchip,pins = 1392 <0 30 RK_FUNC_2 &pcfg_pull_none>; 1393 }; 1394 1395 fephyled_rxm0: fephyled-rxm0 { 1396 rockchip,pins = 1397 <0 29 RK_FUNC_1 &pcfg_pull_none>; 1398 }; 1399 1400 fephyled_txm0: fephyled-txm0 { 1401 rockchip,pins = 1402 <0 29 RK_FUNC_2 &pcfg_pull_none>; 1403 }; 1404 1405 fephyled_linkm0: fephyled-linkm0 { 1406 rockchip,pins = 1407 <0 28 RK_FUNC_1 &pcfg_pull_none>; 1408 }; 1409 1410 fephyled_rxm1: fephyled-rxm1 { 1411 rockchip,pins = 1412 <2 25 RK_FUNC_2 &pcfg_pull_none>; 1413 }; 1414 1415 fephyled_txm1: fephyled-txm1 { 1416 rockchip,pins = 1417 <2 25 RK_FUNC_3 &pcfg_pull_none>; 1418 }; 1419 1420 fephyled_linkm1: fephyled-linkm1 { 1421 rockchip,pins = 1422 <2 24 RK_FUNC_2 &pcfg_pull_none>; 1423 }; 1424 }; 1425 1426 tsadc_pin { 1427 tsadc_int: tsadc-int { 1428 rockchip,pins = 1429 <2 13 RK_FUNC_2 &pcfg_pull_none>; 1430 }; 1431 tsadc_gpio: tsadc-gpio { 1432 rockchip,pins = 1433 <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 1434 }; 1435 }; 1436 1437 hdmi_pin { 1438 hdmi_cec: hdmi-cec { 1439 rockchip,pins = 1440 <0 3 RK_FUNC_1 &pcfg_pull_none>; 1441 }; 1442 1443 hdmi_hpd: hdmi-hpd { 1444 rockchip,pins = 1445 <0 4 RK_FUNC_1 &pcfg_pull_down>; 1446 }; 1447 }; 1448 1449 cif-0 { 1450 dvp_d2d9_m0:dvp-d2d9-m0 { 1451 rockchip,pins = 1452 /* cif_d0 */ 1453 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1454 /* cif_d1 */ 1455 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1456 /* cif_d2 */ 1457 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1458 /* cif_d3 */ 1459 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1460 /* cif_d4 */ 1461 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1462 /* cif_d5m0 */ 1463 <3 9 RK_FUNC_2 &pcfg_pull_none>, 1464 /* cif_d6m0 */ 1465 <3 10 RK_FUNC_2 &pcfg_pull_none>, 1466 /* cif_d7m0 */ 1467 <3 11 RK_FUNC_2 &pcfg_pull_none>, 1468 /* cif_href */ 1469 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1470 /* cif_vsync */ 1471 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1472 /* cif_clkoutm0 */ 1473 <3 3 RK_FUNC_2 &pcfg_pull_none>, 1474 /* cif_clkin */ 1475 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1476 }; 1477 }; 1478 1479 cif-1 { 1480 dvp_d2d9_m1:dvp-d2d9-m1 { 1481 rockchip,pins = 1482 /* cif_d0 */ 1483 <3 4 RK_FUNC_2 &pcfg_pull_none>, 1484 /* cif_d1 */ 1485 <3 5 RK_FUNC_2 &pcfg_pull_none>, 1486 /* cif_d2 */ 1487 <3 6 RK_FUNC_2 &pcfg_pull_none>, 1488 /* cif_d3 */ 1489 <3 7 RK_FUNC_2 &pcfg_pull_none>, 1490 /* cif_d4 */ 1491 <3 8 RK_FUNC_2 &pcfg_pull_none>, 1492 /* cif_d5m1 */ 1493 <2 16 RK_FUNC_4 &pcfg_pull_none>, 1494 /* cif_d6m1 */ 1495 <2 17 RK_FUNC_4 &pcfg_pull_none>, 1496 /* cif_d7m1 */ 1497 <2 18 RK_FUNC_4 &pcfg_pull_none>, 1498 /* cif_href */ 1499 <3 1 RK_FUNC_2 &pcfg_pull_none>, 1500 /* cif_vsync */ 1501 <3 0 RK_FUNC_2 &pcfg_pull_none>, 1502 /* cif_clkoutm1 */ 1503 <2 15 RK_FUNC_4 &pcfg_pull_none>, 1504 /* cif_clkin */ 1505 <3 2 RK_FUNC_2 &pcfg_pull_none>; 1506 }; 1507 }; 1508 }; 1509}; 1510