1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3288-cru.h> 10#include <dt-bindings/power-domain/rk3288.h> 11#include <dt-bindings/thermal/thermal.h> 12#include <dt-bindings/video/rk3288.h> 13#include "skeleton.dtsi" 14 15/ { 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 gpio3 = &gpio3; 24 gpio4 = &gpio4; 25 gpio5 = &gpio5; 26 gpio6 = &gpio6; 27 gpio7 = &gpio7; 28 gpio8 = &gpio8; 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 mmc0 = &emmc; 36 mmc1 = &sdmmc; 37 mmc2 = &sdio0; 38 mmc3 = &sdio1; 39 mshc0 = &emmc; 40 mshc1 = &sdmmc; 41 mshc2 = &sdio0; 42 mshc3 = &sdio1; 43 serial0 = &uart0; 44 serial1 = &uart1; 45 serial2 = &uart2; 46 serial3 = &uart3; 47 serial4 = &uart4; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi2 = &spi2; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 enable-method = "rockchip,rk3066-smp"; 57 rockchip,pmu = <&pmu>; 58 59 cpu0: cpu@500 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a12"; 62 reg = <0x500>; 63 operating-points = < 64 /* KHz uV */ 65 1800000 1400000 66 1704000 1350000 67 1608000 1300000 68 1512000 1250000 69 1416000 1200000 70 1200000 1100000 71 1008000 1050000 72 816000 1000000 73 696000 950000 74 600000 900000 75 408000 900000 76 216000 900000 77 126000 900000 78 >; 79 #cooling-cells = <2>; /* min followed by max */ 80 clock-latency = <40000>; 81 clocks = <&cru ARMCLK>; 82 resets = <&cru SRST_CORE0>; 83 }; 84 cpu@501 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a12"; 87 reg = <0x501>; 88 resets = <&cru SRST_CORE1>; 89 }; 90 cpu@502 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a12"; 93 reg = <0x502>; 94 resets = <&cru SRST_CORE2>; 95 }; 96 cpu@503 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a12"; 99 reg = <0x503>; 100 resets = <&cru SRST_CORE3>; 101 }; 102 }; 103 104 amba { 105 compatible = "arm,amba-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 dmac_peri: dma-controller@ff250000 { 111 compatible = "arm,pl330", "arm,primecell"; 112 broken-no-flushp; 113 reg = <0xff250000 0x4000>; 114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 116 #dma-cells = <1>; 117 clocks = <&cru ACLK_DMAC2>; 118 clock-names = "apb_pclk"; 119 }; 120 121 dmac_bus_ns: dma-controller@ff600000 { 122 compatible = "arm,pl330", "arm,primecell"; 123 broken-no-flushp; 124 reg = <0xff600000 0x4000>; 125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 127 #dma-cells = <1>; 128 clocks = <&cru ACLK_DMAC1>; 129 clock-names = "apb_pclk"; 130 status = "disabled"; 131 }; 132 133 dmac_bus_s: dma-controller@ffb20000 { 134 compatible = "arm,pl330", "arm,primecell"; 135 broken-no-flushp; 136 reg = <0xffb20000 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 #dma-cells = <1>; 140 clocks = <&cru ACLK_DMAC1>; 141 clock-names = "apb_pclk"; 142 }; 143 }; 144 145 xin24m: oscillator { 146 compatible = "fixed-clock"; 147 clock-frequency = <24000000>; 148 clock-output-names = "xin24m"; 149 #clock-cells = <0>; 150 }; 151 152 timer { 153 arm,use-physical-timer; 154 compatible = "arm,armv7-timer"; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 159 clock-frequency = <24000000>; 160 always-on; 161 }; 162 163 display-subsystem { 164 compatible = "rockchip,display-subsystem"; 165 ports = <&vopl_out>, <&vopb_out>; 166 }; 167 168 sdmmc: dwmmc@ff0c0000 { 169 compatible = "rockchip,rk3288-dw-mshc"; 170 clock-freq-min-max = <400000 150000000>; 171 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 172 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 173 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 174 fifo-depth = <0x100>; 175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 176 reg = <0xff0c0000 0x4000>; 177 status = "disabled"; 178 }; 179 180 sdio0: dwmmc@ff0d0000 { 181 compatible = "rockchip,rk3288-dw-mshc"; 182 clock-freq-min-max = <400000 150000000>; 183 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 184 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 185 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 186 fifo-depth = <0x100>; 187 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 188 reg = <0xff0d0000 0x4000>; 189 status = "disabled"; 190 }; 191 192 sdio1: dwmmc@ff0e0000 { 193 compatible = "rockchip,rk3288-dw-mshc"; 194 clock-freq-min-max = <400000 150000000>; 195 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 196 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 197 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 198 fifo-depth = <0x100>; 199 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 200 reg = <0xff0e0000 0x4000>; 201 status = "disabled"; 202 }; 203 204 emmc: dwmmc@ff0f0000 { 205 compatible = "rockchip,rk3288-dw-mshc"; 206 clock-freq-min-max = <400000 150000000>; 207 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 208 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 209 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 210 fifo-depth = <0x100>; 211 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 212 reg = <0xff0f0000 0x4000>; 213 status = "disabled"; 214 }; 215 216 saradc: saradc@ff100000 { 217 compatible = "rockchip,saradc"; 218 reg = <0xff100000 0x100>; 219 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 220 #io-channel-cells = <1>; 221 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 222 clock-names = "saradc", "apb_pclk"; 223 status = "disabled"; 224 }; 225 226 spi0: spi@ff110000 { 227 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 228 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 229 clock-names = "spiclk", "apb_pclk"; 230 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 231 dma-names = "tx", "rx"; 232 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 235 reg = <0xff110000 0x1000>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 status = "disabled"; 239 }; 240 241 spi1: spi@ff120000 { 242 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 243 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 244 clock-names = "spiclk", "apb_pclk"; 245 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 246 dma-names = "tx", "rx"; 247 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 250 reg = <0xff120000 0x1000>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 status = "disabled"; 254 }; 255 256 spi2: spi@ff130000 { 257 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 258 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 259 clock-names = "spiclk", "apb_pclk"; 260 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 261 dma-names = "tx", "rx"; 262 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 265 reg = <0xff130000 0x1000>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 i2c1: i2c@ff140000 { 272 compatible = "rockchip,rk3288-i2c"; 273 reg = <0xff140000 0x1000>; 274 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 clock-names = "i2c"; 278 clocks = <&cru PCLK_I2C1>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&i2c1_xfer>; 281 status = "disabled"; 282 }; 283 284 i2c3: i2c@ff150000 { 285 compatible = "rockchip,rk3288-i2c"; 286 reg = <0xff150000 0x1000>; 287 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 clock-names = "i2c"; 291 clocks = <&cru PCLK_I2C3>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&i2c3_xfer>; 294 status = "disabled"; 295 }; 296 297 i2c4: i2c@ff160000 { 298 compatible = "rockchip,rk3288-i2c"; 299 reg = <0xff160000 0x1000>; 300 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 clock-names = "i2c"; 304 clocks = <&cru PCLK_I2C4>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&i2c4_xfer>; 307 status = "disabled"; 308 }; 309 310 i2c5: i2c@ff170000 { 311 compatible = "rockchip,rk3288-i2c"; 312 reg = <0xff170000 0x1000>; 313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 clock-names = "i2c"; 317 clocks = <&cru PCLK_I2C5>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&i2c5_xfer>; 320 status = "disabled"; 321 }; 322 uart0: serial@ff180000 { 323 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 324 reg = <0xff180000 0x100>; 325 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 326 reg-shift = <2>; 327 reg-io-width = <4>; 328 clock-frequency = <24000000>; 329 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 330 clock-names = "baudclk", "apb_pclk"; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&uart0_xfer>; 333 status = "disabled"; 334 }; 335 336 uart1: serial@ff190000 { 337 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 338 reg = <0xff190000 0x100>; 339 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 340 reg-shift = <2>; 341 reg-io-width = <4>; 342 clock-frequency = <24000000>; 343 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 344 clock-names = "baudclk", "apb_pclk"; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&uart1_xfer>; 347 status = "disabled"; 348 }; 349 350 uart2: serial@ff690000 { 351 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 352 reg = <0xff690000 0x100>; 353 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 354 reg-shift = <2>; 355 reg-io-width = <4>; 356 clock-frequency = <24000000>; 357 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 358 clock-names = "baudclk", "apb_pclk"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&uart2_xfer>; 361 status = "disabled"; 362 }; 363 uart3: serial@ff1b0000 { 364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 365 reg = <0xff1b0000 0x100>; 366 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 367 reg-shift = <2>; 368 reg-io-width = <4>; 369 clock-frequency = <24000000>; 370 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 371 clock-names = "baudclk", "apb_pclk"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&uart3_xfer>; 374 status = "disabled"; 375 }; 376 377 uart4: serial@ff1c0000 { 378 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 379 reg = <0xff1c0000 0x100>; 380 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 381 reg-shift = <2>; 382 reg-io-width = <4>; 383 clock-frequency = <24000000>; 384 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 385 clock-names = "baudclk", "apb_pclk"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&uart4_xfer>; 388 status = "disabled"; 389 }; 390 thermal: thermal-zones { 391 #include "rk3288-thermal.dtsi" 392 }; 393 394 tsadc: tsadc@ff280000 { 395 compatible = "rockchip,rk3288-tsadc"; 396 reg = <0xff280000 0x100>; 397 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 399 clock-names = "tsadc", "apb_pclk"; 400 resets = <&cru SRST_TSADC>; 401 reset-names = "tsadc-apb"; 402 pinctrl-names = "otp_out"; 403 pinctrl-0 = <&otp_out>; 404 #thermal-sensor-cells = <1>; 405 hw-shut-temp = <125000>; 406 status = "disabled"; 407 }; 408 409 gmac: ethernet@ff290000 { 410 compatible = "rockchip,rk3288-gmac"; 411 reg = <0xff290000 0x10000>; 412 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "macirq"; 414 rockchip,grf = <&grf>; 415 clocks = <&cru SCLK_MAC>, 416 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 417 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 418 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 419 clock-names = "stmmaceth", 420 "mac_clk_rx", "mac_clk_tx", 421 "clk_mac_ref", "clk_mac_refout", 422 "aclk_mac", "pclk_mac"; 423 }; 424 425 usb_host0_ehci: usb@ff500000 { 426 compatible = "generic-ehci"; 427 reg = <0xff500000 0x100>; 428 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cru HCLK_USBHOST0>; 430 clock-names = "usbhost"; 431 phys = <&usbphy1>; 432 phy-names = "usb"; 433 status = "disabled"; 434 }; 435 436 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 437 438 usb_host1: usb@ff540000 { 439 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 440 "snps,dwc2"; 441 reg = <0xff540000 0x40000>; 442 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&cru HCLK_USBHOST1>; 444 clock-names = "otg"; 445 phys = <&usbphy2>; 446 phy-names = "usb2-phy"; 447 status = "disabled"; 448 }; 449 450 usb_otg: usb@ff580000 { 451 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 452 "snps,dwc2"; 453 reg = <0xff580000 0x40000>; 454 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&cru HCLK_OTG0>; 456 clock-names = "otg"; 457 phys = <&usbphy0>; 458 phy-names = "usb2-phy"; 459 status = "disabled"; 460 }; 461 462 usb_hsic: usb@ff5c0000 { 463 compatible = "generic-ehci"; 464 reg = <0xff5c0000 0x100>; 465 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cru HCLK_HSIC>; 467 clock-names = "usbhost"; 468 status = "disabled"; 469 }; 470 471 dmc: dmc@ff610000 { 472 u-boot,dm-pre-reloc; 473 compatible = "rockchip,rk3288-dmc", "syscon"; 474 rockchip,cru = <&cru>; 475 rockchip,grf = <&grf>; 476 rockchip,pmu = <&pmu>; 477 rockchip,sgrf = <&sgrf>; 478 rockchip,noc = <&noc>; 479 reg = <0xff610000 0x3fc 480 0xff620000 0x294 481 0xff630000 0x3fc 482 0xff640000 0x294>; 483 rockchip,sram = <&ddr_sram>; 484 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, 485 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, 486 <&cru ARMCLK>; 487 clock-names = "pclk_ddrupctl0", "pclk_publ0", 488 "pclk_ddrupctl1", "pclk_publ1", 489 "arm_clk"; 490 }; 491 492 i2c0: i2c@ff650000 { 493 compatible = "rockchip,rk3288-i2c"; 494 reg = <0xff650000 0x1000>; 495 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 clock-names = "i2c"; 499 clocks = <&cru PCLK_I2C0>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&i2c0_xfer>; 502 status = "disabled"; 503 }; 504 505 i2c2: i2c@ff660000 { 506 compatible = "rockchip,rk3288-i2c"; 507 reg = <0xff660000 0x1000>; 508 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 clock-names = "i2c"; 512 clocks = <&cru PCLK_I2C2>; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&i2c2_xfer>; 515 status = "disabled"; 516 }; 517 518 pwm0: pwm@ff680000 { 519 compatible = "rockchip,rk3288-pwm"; 520 reg = <0xff680000 0x10>; 521 #pwm-cells = <3>; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&pwm0_pin>; 524 clocks = <&cru PCLK_PWM>; 525 clock-names = "pwm"; 526 rockchip,grf = <&grf>; 527 status = "disabled"; 528 }; 529 530 pwm1: pwm@ff680010 { 531 compatible = "rockchip,rk3288-pwm"; 532 reg = <0xff680010 0x10>; 533 #pwm-cells = <3>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&pwm1_pin>; 536 clocks = <&cru PCLK_PWM>; 537 clock-names = "pwm"; 538 rockchip,grf = <&grf>; 539 status = "disabled"; 540 }; 541 542 pwm2: pwm@ff680020 { 543 compatible = "rockchip,rk3288-pwm"; 544 reg = <0xff680020 0x10>; 545 #pwm-cells = <3>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pwm2_pin>; 548 clocks = <&cru PCLK_PWM>; 549 clock-names = "pwm"; 550 rockchip,grf = <&grf>; 551 status = "disabled"; 552 }; 553 554 pwm3: pwm@ff680030 { 555 compatible = "rockchip,rk3288-pwm"; 556 reg = <0xff680030 0x10>; 557 #pwm-cells = <2>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&pwm3_pin>; 560 clocks = <&cru PCLK_PWM>; 561 clock-names = "pwm"; 562 rockchip,grf = <&grf>; 563 status = "disabled"; 564 }; 565 566 bus_intmem@ff700000 { 567 compatible = "mmio-sram"; 568 reg = <0xff700000 0x18000>; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 ranges = <0 0xff700000 0x18000>; 572 smp-sram@0 { 573 compatible = "rockchip,rk3066-smp-sram"; 574 reg = <0x00 0x10>; 575 }; 576 ddr_sram: ddr-sram@1000 { 577 compatible = "rockchip,rk3288-ddr-sram"; 578 reg = <0x1000 0x4000>; 579 }; 580 }; 581 582 sram@ff720000 { 583 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 584 reg = <0xff720000 0x1000>; 585 }; 586 587 pmu: power-management@ff730000 { 588 u-boot,dm-pre-reloc; 589 compatible = "rockchip,rk3288-pmu", "syscon"; 590 reg = <0xff730000 0x100>; 591 }; 592 593 sgrf: syscon@ff740000 { 594 u-boot,dm-pre-reloc; 595 compatible = "rockchip,rk3288-sgrf", "syscon"; 596 reg = <0xff740000 0x1000>; 597 }; 598 599 cru: clock-controller@ff760000 { 600 compatible = "rockchip,rk3288-cru"; 601 reg = <0xff760000 0x1000>; 602 rockchip,grf = <&grf>; 603 u-boot,dm-pre-reloc; 604 #clock-cells = <1>; 605 #reset-cells = <1>; 606 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, 607 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 608 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 609 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 610 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 611 <&cru PCLK_PERI>; 612 assigned-clock-rates = <0>, <0>, 613 <594000000>, <400000000>, 614 <500000000>, <300000000>, 615 <150000000>, <75000000>, 616 <300000000>, <150000000>, 617 <75000000>; 618 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>; 619 }; 620 621 grf: syscon@ff770000 { 622 u-boot,dm-pre-reloc; 623 compatible = "rockchip,rk3288-grf", "syscon"; 624 reg = <0xff770000 0x1000>; 625 }; 626 627 wdt: watchdog@ff800000 { 628 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 629 reg = <0xff800000 0x100>; 630 clocks = <&cru PCLK_WDT>; 631 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 632 status = "disabled"; 633 }; 634 635 spdif: sound@ff88b0000 { 636 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 637 reg = <0xff8b0000 0x10000>; 638 #sound-dai-cells = <0>; 639 clock-names = "hclk", "mclk"; 640 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; 641 dmas = <&dmac_bus_s 3>; 642 dma-names = "tx"; 643 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&spdif_tx>; 646 rockchip,grf = <&grf>; 647 status = "disabled"; 648 }; 649 650 i2s: i2s@ff890000 { 651 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 652 reg = <0xff890000 0x10000>; 653 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 657 dma-names = "tx", "rx"; 658 clock-names = "i2s_hclk", "i2s_clk"; 659 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&i2s0_bus>; 662 status = "disabled"; 663 }; 664 665 vopb: vop@ff930000 { 666 compatible = "rockchip,rk3288-vop"; 667 reg = <0xff930000 0x19c>; 668 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 670 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 671 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 672 reset-names = "axi", "ahb", "dclk"; 673 iommus = <&vopb_mmu>; 674 power-domains = <&power RK3288_PD_VIO>; 675 status = "disabled"; 676 vopb_out: port { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 vopb_out_edp: endpoint@0 { 680 reg = <0>; 681 remote-endpoint = <&edp_in_vopb>; 682 }; 683 vopb_out_hdmi: endpoint@1 { 684 reg = <1>; 685 remote-endpoint = <&hdmi_in_vopb>; 686 }; 687 vopb_out_lvds: endpoint@2 { 688 reg = <2>; 689 remote-endpoint = <&lvds_in_vopb>; 690 }; 691 }; 692 }; 693 694 vopb_mmu: iommu@ff930300 { 695 compatible = "rockchip,iommu"; 696 reg = <0xff930300 0x100>; 697 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 698 interrupt-names = "vopb_mmu"; 699 power-domains = <&power RK3288_PD_VIO>; 700 #iommu-cells = <0>; 701 status = "disabled"; 702 }; 703 704 vopl: vop@ff940000 { 705 compatible = "rockchip,rk3288-vop"; 706 reg = <0xff940000 0x19c>; 707 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 709 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 710 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 711 reset-names = "axi", "ahb", "dclk"; 712 iommus = <&vopl_mmu>; 713 power-domains = <&power RK3288_PD_VIO>; 714 status = "disabled"; 715 u-boot,dm-pre-reloc; 716 vopl_out: port { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 vopl_out_edp: endpoint@0 { 720 reg = <0>; 721 remote-endpoint = <&edp_in_vopl>; 722 }; 723 vopl_out_hdmi: endpoint@1 { 724 reg = <1>; 725 remote-endpoint = <&hdmi_in_vopl>; 726 }; 727 vopl_out_lvds: endpoint@2 { 728 reg = <2>; 729 remote-endpoint = <&lvds_in_vopl>; 730 }; 731 }; 732 }; 733 734 vopl_mmu: iommu@ff940300 { 735 compatible = "rockchip,iommu"; 736 reg = <0xff940300 0x100>; 737 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "vopl_mmu"; 739 power-domains = <&power RK3288_PD_VIO>; 740 #iommu-cells = <0>; 741 status = "disabled"; 742 }; 743 744 edp: edp@ff970000 { 745 compatible = "rockchip,rk3288-edp"; 746 reg = <0xff970000 0x4000>; 747 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; 749 rockchip,grf = <&grf>; 750 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; 751 resets = <&cru 111>; 752 reset-names = "edp"; 753 power-domains = <&power RK3288_PD_VIO>; 754 status = "disabled"; 755 ports { 756 edp_in: port { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 edp_in_vopb: endpoint@0 { 760 reg = <0>; 761 remote-endpoint = <&vopb_out_edp>; 762 }; 763 edp_in_vopl: endpoint@1 { 764 reg = <1>; 765 remote-endpoint = <&vopl_out_edp>; 766 }; 767 }; 768 }; 769 }; 770 771 hdmi: hdmi@ff980000 { 772 compatible = "rockchip,rk3288-dw-hdmi"; 773 reg = <0xff980000 0x20000>; 774 reg-io-width = <4>; 775 ddc-i2c-bus = <&i2c5>; 776 rockchip,grf = <&grf>; 777 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 779 clock-names = "iahb", "isfr"; 780 status = "disabled"; 781 ports { 782 hdmi_in: port { 783 #address-cells = <1>; 784 #size-cells = <0>; 785 hdmi_in_vopb: endpoint@0 { 786 reg = <0>; 787 remote-endpoint = <&vopb_out_hdmi>; 788 }; 789 hdmi_in_vopl: endpoint@1 { 790 reg = <1>; 791 remote-endpoint = <&vopl_out_hdmi>; 792 }; 793 }; 794 }; 795 }; 796 797 lvds: lvds@ff96c000 { 798 compatible = "rockchip,rk3288-lvds"; 799 reg = <0xff96c000 0x4000>; 800 clocks = <&cru PCLK_LVDS_PHY>; 801 clock-names = "pclk_lvds"; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&lcdc0_ctl>; 804 rockchip,grf = <&grf>; 805 status = "disabled"; 806 ports { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 lvds_in: port@0 { 810 reg = <0>; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 lvds_in_vopb: endpoint@0 { 814 reg = <0>; 815 remote-endpoint = <&vopb_out_lvds>; 816 }; 817 lvds_in_vopl: endpoint@1 { 818 reg = <1>; 819 remote-endpoint = <&vopl_out_lvds>; 820 }; 821 }; 822 }; 823 }; 824 825 hdmi_audio: hdmi_audio { 826 compatible = "rockchip,rk3288-hdmi-audio"; 827 i2s-controller = <&i2s>; 828 status = "disable"; 829 }; 830 831 vpu: video-codec@ff9a0000 { 832 compatible = "rockchip,rk3288-vpu"; 833 reg = <0xff9a0000 0x800>; 834 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-names = "vepu", "vdpu"; 837 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 838 clock-names = "aclk_vcodec", "hclk_vcodec"; 839 power-domains = <&power RK3288_PD_VIDEO>; 840 iommus = <&vpu_mmu>; 841 }; 842 843 vpu_mmu: iommu@ff9a0800 { 844 compatible = "rockchip,iommu"; 845 reg = <0xff9a0800 0x100>; 846 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 847 interrupt-names = "vpu_mmu"; 848 power-domains = <&power RK3288_PD_VIDEO>; 849 #iommu-cells = <0>; 850 }; 851 852 gpu: gpu@ffa30000 { 853 compatible = "arm,malit764", 854 "arm,malit76x", 855 "arm,malit7xx", 856 "arm,mali-midgard"; 857 reg = <0xffa30000 0x10000>; 858 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "JOB", "MMU", "GPU"; 862 clocks = <&cru ACLK_GPU>; 863 clock-names = "aclk_gpu"; 864 operating-points = < 865 /* KHz uV */ 866 100000 950000 867 200000 950000 868 300000 1000000 869 400000 1100000 870 /* 500000 1200000 - See crosbug.com/p/33857 */ 871 600000 1250000 872 >; 873 power-domains = <&power RK3288_PD_GPU>; 874 status = "disabled"; 875 }; 876 877 noc: syscon@ffac0000 { 878 u-boot,dm-pre-reloc; 879 compatible = "rockchip,rk3288-noc", "syscon"; 880 reg = <0xffac0000 0x2000>; 881 }; 882 883 efuse: efuse@ffb40000 { 884 compatible = "rockchip,rk3288-efuse"; 885 reg = <0xffb40000 0x10000>; 886 status = "disabled"; 887 }; 888 889 gic: interrupt-controller@ffc01000 { 890 compatible = "arm,gic-400"; 891 interrupt-controller; 892 #interrupt-cells = <3>; 893 #address-cells = <0>; 894 895 reg = <0xffc01000 0x1000>, 896 <0xffc02000 0x1000>, 897 <0xffc04000 0x2000>, 898 <0xffc06000 0x2000>; 899 interrupts = <GIC_PPI 9 0xf04>; 900 }; 901 902 cpuidle: cpuidle { 903 compatible = "rockchip,rk3288-cpuidle"; 904 }; 905 906 usbphy: phy { 907 compatible = "rockchip,rk3288-usb-phy"; 908 rockchip,grf = <&grf>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 status = "disabled"; 912 913 usbphy0: usb-phy0 { 914 #phy-cells = <0>; 915 reg = <0x320>; 916 clocks = <&cru SCLK_OTGPHY0>; 917 clock-names = "phyclk"; 918 }; 919 920 usbphy1: usb-phy1 { 921 #phy-cells = <0>; 922 reg = <0x334>; 923 clocks = <&cru SCLK_OTGPHY1>; 924 clock-names = "phyclk"; 925 }; 926 927 usbphy2: usb-phy2 { 928 #phy-cells = <0>; 929 reg = <0x348>; 930 clocks = <&cru SCLK_OTGPHY2>; 931 clock-names = "phyclk"; 932 }; 933 }; 934 935 pinctrl: pinctrl { 936 compatible = "rockchip,rk3288-pinctrl"; 937 rockchip,grf = <&grf>; 938 rockchip,pmu = <&pmu>; 939 #address-cells = <1>; 940 #size-cells = <1>; 941 ranges; 942 943 gpio0: gpio0@ff750000 { 944 compatible = "rockchip,gpio-bank"; 945 reg = <0xff750000 0x100>; 946 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&cru PCLK_GPIO0>; 948 949 gpio-controller; 950 #gpio-cells = <2>; 951 952 interrupt-controller; 953 #interrupt-cells = <2>; 954 }; 955 956 gpio1: gpio1@ff780000 { 957 compatible = "rockchip,gpio-bank"; 958 reg = <0xff780000 0x100>; 959 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&cru PCLK_GPIO1>; 961 962 gpio-controller; 963 #gpio-cells = <2>; 964 965 interrupt-controller; 966 #interrupt-cells = <2>; 967 }; 968 969 gpio2: gpio2@ff790000 { 970 compatible = "rockchip,gpio-bank"; 971 reg = <0xff790000 0x100>; 972 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&cru PCLK_GPIO2>; 974 975 gpio-controller; 976 #gpio-cells = <2>; 977 978 interrupt-controller; 979 #interrupt-cells = <2>; 980 }; 981 982 gpio3: gpio3@ff7a0000 { 983 compatible = "rockchip,gpio-bank"; 984 reg = <0xff7a0000 0x100>; 985 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&cru PCLK_GPIO3>; 987 988 gpio-controller; 989 #gpio-cells = <2>; 990 991 interrupt-controller; 992 #interrupt-cells = <2>; 993 }; 994 995 gpio4: gpio4@ff7b0000 { 996 compatible = "rockchip,gpio-bank"; 997 reg = <0xff7b0000 0x100>; 998 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&cru PCLK_GPIO4>; 1000 1001 gpio-controller; 1002 #gpio-cells = <2>; 1003 1004 interrupt-controller; 1005 #interrupt-cells = <2>; 1006 }; 1007 1008 gpio5: gpio5@ff7c0000 { 1009 compatible = "rockchip,gpio-bank"; 1010 reg = <0xff7c0000 0x100>; 1011 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&cru PCLK_GPIO5>; 1013 1014 gpio-controller; 1015 #gpio-cells = <2>; 1016 1017 interrupt-controller; 1018 #interrupt-cells = <2>; 1019 }; 1020 1021 gpio6: gpio6@ff7d0000 { 1022 compatible = "rockchip,gpio-bank"; 1023 reg = <0xff7d0000 0x100>; 1024 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&cru PCLK_GPIO6>; 1026 1027 gpio-controller; 1028 #gpio-cells = <2>; 1029 1030 interrupt-controller; 1031 #interrupt-cells = <2>; 1032 }; 1033 1034 gpio7: gpio7@ff7e0000 { 1035 compatible = "rockchip,gpio-bank"; 1036 reg = <0xff7e0000 0x100>; 1037 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&cru PCLK_GPIO7>; 1039 1040 gpio-controller; 1041 #gpio-cells = <2>; 1042 1043 interrupt-controller; 1044 #interrupt-cells = <2>; 1045 }; 1046 1047 gpio8: gpio8@ff7f0000 { 1048 compatible = "rockchip,gpio-bank"; 1049 reg = <0xff7f0000 0x100>; 1050 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&cru PCLK_GPIO8>; 1052 1053 gpio-controller; 1054 #gpio-cells = <2>; 1055 1056 interrupt-controller; 1057 #interrupt-cells = <2>; 1058 }; 1059 1060 pcfg_pull_up: pcfg-pull-up { 1061 bias-pull-up; 1062 }; 1063 1064 pcfg_pull_down: pcfg-pull-down { 1065 bias-pull-down; 1066 }; 1067 1068 pcfg_pull_none: pcfg-pull-none { 1069 bias-disable; 1070 }; 1071 1072 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1073 bias-disable; 1074 drive-strength = <12>; 1075 }; 1076 1077 sleep { 1078 global_pwroff: global-pwroff { 1079 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1080 }; 1081 1082 ddrio_pwroff: ddrio-pwroff { 1083 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1084 }; 1085 1086 ddr0_retention: ddr0-retention { 1087 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1088 }; 1089 1090 ddr1_retention: ddr1-retention { 1091 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1092 }; 1093 }; 1094 1095 i2c0 { 1096 i2c0_xfer: i2c0-xfer { 1097 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1098 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1099 }; 1100 }; 1101 1102 i2c1 { 1103 i2c1_xfer: i2c1-xfer { 1104 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1105 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1106 }; 1107 }; 1108 1109 i2c2 { 1110 i2c2_xfer: i2c2-xfer { 1111 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1112 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1113 }; 1114 }; 1115 1116 i2c3 { 1117 i2c3_xfer: i2c3-xfer { 1118 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1119 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1120 }; 1121 }; 1122 1123 i2c4 { 1124 i2c4_xfer: i2c4-xfer { 1125 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1126 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1127 }; 1128 }; 1129 1130 i2c5 { 1131 i2c5_xfer: i2c5-xfer { 1132 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1133 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1134 }; 1135 }; 1136 1137 i2s0 { 1138 i2s0_bus: i2s0-bus { 1139 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1140 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1141 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1142 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1143 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1144 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1145 }; 1146 }; 1147 1148 lcdc0 { 1149 lcdc0_ctl: lcdc0-ctl { 1150 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, 1151 <1 25 RK_FUNC_1 &pcfg_pull_none>, 1152 <1 26 RK_FUNC_1 &pcfg_pull_none>, 1153 <1 27 RK_FUNC_1 &pcfg_pull_none>; 1154 }; 1155 }; 1156 1157 sdmmc { 1158 sdmmc_clk: sdmmc-clk { 1159 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1160 }; 1161 1162 sdmmc_cmd: sdmmc-cmd { 1163 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1164 }; 1165 1166 sdmmc_cd: sdmcc-cd { 1167 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1168 }; 1169 1170 sdmmc_bus1: sdmmc-bus1 { 1171 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1172 }; 1173 1174 sdmmc_bus4: sdmmc-bus4 { 1175 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1176 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1177 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1178 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1179 }; 1180 }; 1181 1182 sdio0 { 1183 sdio0_bus1: sdio0-bus1 { 1184 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1185 }; 1186 1187 sdio0_bus4: sdio0-bus4 { 1188 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1189 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1190 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1191 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1192 }; 1193 1194 sdio0_cmd: sdio0-cmd { 1195 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1196 }; 1197 1198 sdio0_clk: sdio0-clk { 1199 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1200 }; 1201 1202 sdio0_cd: sdio0-cd { 1203 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1204 }; 1205 1206 sdio0_wp: sdio0-wp { 1207 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1208 }; 1209 1210 sdio0_pwr: sdio0-pwr { 1211 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1212 }; 1213 1214 sdio0_bkpwr: sdio0-bkpwr { 1215 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1216 }; 1217 1218 sdio0_int: sdio0-int { 1219 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1220 }; 1221 }; 1222 1223 sdio1 { 1224 sdio1_bus1: sdio1-bus1 { 1225 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; 1226 }; 1227 1228 sdio1_bus4: sdio1-bus4 { 1229 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, 1230 <3 25 RK_FUNC_4 &pcfg_pull_up>, 1231 <3 26 RK_FUNC_4 &pcfg_pull_up>, 1232 <3 27 RK_FUNC_4 &pcfg_pull_up>; 1233 }; 1234 1235 sdio1_cd: sdio1-cd { 1236 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; 1237 }; 1238 1239 sdio1_wp: sdio1-wp { 1240 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; 1241 }; 1242 1243 sdio1_bkpwr: sdio1-bkpwr { 1244 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; 1245 }; 1246 1247 sdio1_int: sdio1-int { 1248 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; 1249 }; 1250 1251 sdio1_cmd: sdio1-cmd { 1252 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; 1253 }; 1254 1255 sdio1_clk: sdio1-clk { 1256 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; 1257 }; 1258 1259 sdio1_pwr: sdio1-pwr { 1260 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; 1261 }; 1262 }; 1263 1264 emmc { 1265 emmc_clk: emmc-clk { 1266 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1267 }; 1268 1269 emmc_cmd: emmc-cmd { 1270 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1271 }; 1272 1273 emmc_pwr: emmc-pwr { 1274 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1275 }; 1276 1277 emmc_bus1: emmc-bus1 { 1278 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1279 }; 1280 1281 emmc_bus4: emmc-bus4 { 1282 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1283 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1284 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1285 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1286 }; 1287 1288 emmc_bus8: emmc-bus8 { 1289 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1290 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1291 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1292 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1293 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1294 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1295 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1296 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1297 }; 1298 }; 1299 1300 spi0 { 1301 spi0_clk: spi0-clk { 1302 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1303 }; 1304 spi0_cs0: spi0-cs0 { 1305 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1306 }; 1307 spi0_tx: spi0-tx { 1308 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1309 }; 1310 spi0_rx: spi0-rx { 1311 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1312 }; 1313 spi0_cs1: spi0-cs1 { 1314 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1315 }; 1316 }; 1317 spi1 { 1318 spi1_clk: spi1-clk { 1319 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1320 }; 1321 spi1_cs0: spi1-cs0 { 1322 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1323 }; 1324 spi1_rx: spi1-rx { 1325 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1326 }; 1327 spi1_tx: spi1-tx { 1328 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1329 }; 1330 }; 1331 1332 spi2 { 1333 spi2_cs1: spi2-cs1 { 1334 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1335 }; 1336 spi2_clk: spi2-clk { 1337 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1338 }; 1339 spi2_cs0: spi2-cs0 { 1340 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1341 }; 1342 spi2_rx: spi2-rx { 1343 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1344 }; 1345 spi2_tx: spi2-tx { 1346 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1347 }; 1348 }; 1349 1350 uart0 { 1351 uart0_xfer: uart0-xfer { 1352 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1353 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1354 }; 1355 1356 uart0_cts: uart0-cts { 1357 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; 1358 }; 1359 1360 uart0_rts: uart0-rts { 1361 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1362 }; 1363 }; 1364 1365 uart1 { 1366 uart1_xfer: uart1-xfer { 1367 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1368 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1369 }; 1370 1371 uart1_cts: uart1-cts { 1372 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; 1373 }; 1374 1375 uart1_rts: uart1-rts { 1376 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1377 }; 1378 }; 1379 1380 uart2 { 1381 uart2_xfer: uart2-xfer { 1382 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1383 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1384 }; 1385 /* no rts / cts for uart2 */ 1386 }; 1387 1388 uart3 { 1389 uart3_xfer: uart3-xfer { 1390 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1391 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1392 }; 1393 1394 uart3_cts: uart3-cts { 1395 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; 1396 }; 1397 1398 uart3_rts: uart3-rts { 1399 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1400 }; 1401 }; 1402 1403 uart4 { 1404 uart4_xfer: uart4-xfer { 1405 rockchip,pins = <5 12 3 &pcfg_pull_up>, 1406 <5 13 3 &pcfg_pull_none>; 1407 }; 1408 1409 uart4_cts: uart4-cts { 1410 rockchip,pins = <5 14 3 &pcfg_pull_none>; 1411 }; 1412 1413 uart4_rts: uart4-rts { 1414 rockchip,pins = <5 15 3 &pcfg_pull_none>; 1415 }; 1416 }; 1417 1418 tsadc { 1419 otp_out: otp-out { 1420 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1421 }; 1422 }; 1423 1424 pwm0 { 1425 pwm0_pin: pwm0-pin { 1426 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1427 }; 1428 }; 1429 1430 pwm1 { 1431 pwm1_pin: pwm1-pin { 1432 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1433 }; 1434 }; 1435 1436 pwm2 { 1437 pwm2_pin: pwm2-pin { 1438 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; 1439 }; 1440 }; 1441 1442 pwm3 { 1443 pwm3_pin: pwm3-pin { 1444 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; 1445 }; 1446 }; 1447 1448 gmac { 1449 rgmii_pins: rgmii-pins { 1450 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1451 <3 31 3 &pcfg_pull_none>, 1452 <3 26 3 &pcfg_pull_none>, 1453 <3 27 3 &pcfg_pull_none>, 1454 <3 28 3 &pcfg_pull_none_12ma>, 1455 <3 29 3 &pcfg_pull_none_12ma>, 1456 <3 24 3 &pcfg_pull_none_12ma>, 1457 <3 25 3 &pcfg_pull_none_12ma>, 1458 <4 0 3 &pcfg_pull_none>, 1459 <4 5 3 &pcfg_pull_none>, 1460 <4 6 3 &pcfg_pull_none>, 1461 <4 9 3 &pcfg_pull_none_12ma>, 1462 <4 4 3 &pcfg_pull_none_12ma>, 1463 <4 1 3 &pcfg_pull_none>, 1464 <4 3 3 &pcfg_pull_none>; 1465 }; 1466 1467 rmii_pins: rmii-pins { 1468 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1469 <3 31 3 &pcfg_pull_none>, 1470 <3 28 3 &pcfg_pull_none>, 1471 <3 29 3 &pcfg_pull_none>, 1472 <4 0 3 &pcfg_pull_none>, 1473 <4 5 3 &pcfg_pull_none>, 1474 <4 4 3 &pcfg_pull_none>, 1475 <4 1 3 &pcfg_pull_none>, 1476 <4 2 3 &pcfg_pull_none>, 1477 <4 3 3 &pcfg_pull_none>; 1478 }; 1479 }; 1480 1481 spdif { 1482 spdif_tx: spdif-tx { 1483 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; 1484 }; 1485 }; 1486 }; 1487 1488 power: power-controller { 1489 compatible = "rockchip,rk3288-power-controller"; 1490 #power-domain-cells = <1>; 1491 rockchip,pmu = <&pmu>; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 1495 pd_gpu { 1496 reg = <RK3288_PD_GPU>; 1497 clocks = <&cru ACLK_GPU>; 1498 }; 1499 1500 pd_hevc { 1501 reg = <RK3288_PD_HEVC>; 1502 clocks = <&cru ACLK_HEVC>, 1503 <&cru SCLK_HEVC_CABAC>, 1504 <&cru SCLK_HEVC_CORE>, 1505 <&cru HCLK_HEVC>; 1506 }; 1507 1508 pd_vio { 1509 reg = <RK3288_PD_VIO>; 1510 clocks = <&cru ACLK_IEP>, 1511 <&cru ACLK_ISP>, 1512 <&cru ACLK_RGA>, 1513 <&cru ACLK_VIP>, 1514 <&cru ACLK_VOP0>, 1515 <&cru ACLK_VOP1>, 1516 <&cru DCLK_VOP0>, 1517 <&cru DCLK_VOP1>, 1518 <&cru HCLK_IEP>, 1519 <&cru HCLK_ISP>, 1520 <&cru HCLK_RGA>, 1521 <&cru HCLK_VIP>, 1522 <&cru HCLK_VOP0>, 1523 <&cru HCLK_VOP1>, 1524 <&cru PCLK_EDP_CTRL>, 1525 <&cru PCLK_HDMI_CTRL>, 1526 <&cru PCLK_LVDS_PHY>, 1527 <&cru PCLK_MIPI_CSI>, 1528 <&cru PCLK_MIPI_DSI0>, 1529 <&cru PCLK_MIPI_DSI1>, 1530 <&cru SCLK_EDP_24M>, 1531 <&cru SCLK_EDP>, 1532 <&cru SCLK_HDMI_CEC>, 1533 <&cru SCLK_HDMI_HDCP>, 1534 <&cru SCLK_ISP_JPE>, 1535 <&cru SCLK_ISP>, 1536 <&cru SCLK_RGA>; 1537 }; 1538 1539 pd_video { 1540 reg = <RK3288_PD_VIDEO>; 1541 clocks = <&cru ACLK_VCODEC>, 1542 <&cru HCLK_VCODEC>; 1543 }; 1544 }; 1545}; 1546