1/* 2 * SPDX-License-Identifier: GPL-2.0+ 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3288-cru.h> 10#include <dt-bindings/power-domain/rk3288.h> 11#include <dt-bindings/thermal/thermal.h> 12#include "skeleton.dtsi" 13 14/ { 15 compatible = "rockchip,rk3288"; 16 17 interrupt-parent = <&gic>; 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 mmc0 = &emmc; 26 mmc1 = &sdmmc; 27 mmc2 = &sdio0; 28 mmc3 = &sdio1; 29 mshc0 = &emmc; 30 mshc1 = &sdmmc; 31 mshc2 = &sdio0; 32 mshc3 = &sdio1; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 spi0 = &spi0; 39 spi1 = &spi1; 40 spi2 = &spi2; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 enable-method = "rockchip,rk3066-smp"; 47 rockchip,pmu = <&pmu>; 48 49 cpu0: cpu@500 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a12"; 52 reg = <0x500>; 53 operating-points = < 54 /* KHz uV */ 55 1800000 1400000 56 1704000 1350000 57 1608000 1300000 58 1512000 1250000 59 1416000 1200000 60 1200000 1100000 61 1008000 1050000 62 816000 1000000 63 696000 950000 64 600000 900000 65 408000 900000 66 216000 900000 67 126000 900000 68 >; 69 #cooling-cells = <2>; /* min followed by max */ 70 clock-latency = <40000>; 71 clocks = <&cru ARMCLK>; 72 resets = <&cru SRST_CORE0>; 73 }; 74 cpu@501 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a12"; 77 reg = <0x501>; 78 resets = <&cru SRST_CORE1>; 79 }; 80 cpu@502 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a12"; 83 reg = <0x502>; 84 resets = <&cru SRST_CORE2>; 85 }; 86 cpu@503 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a12"; 89 reg = <0x503>; 90 resets = <&cru SRST_CORE3>; 91 }; 92 }; 93 94 amba { 95 compatible = "arm,amba-bus"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 100 dmac_peri: dma-controller@ff250000 { 101 compatible = "arm,pl330", "arm,primecell"; 102 broken-no-flushp; 103 reg = <0xff250000 0x4000>; 104 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 106 #dma-cells = <1>; 107 clocks = <&cru ACLK_DMAC2>; 108 clock-names = "apb_pclk"; 109 }; 110 111 dmac_bus_ns: dma-controller@ff600000 { 112 compatible = "arm,pl330", "arm,primecell"; 113 broken-no-flushp; 114 reg = <0xff600000 0x4000>; 115 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 117 #dma-cells = <1>; 118 clocks = <&cru ACLK_DMAC1>; 119 clock-names = "apb_pclk"; 120 status = "disabled"; 121 }; 122 123 dmac_bus_s: dma-controller@ffb20000 { 124 compatible = "arm,pl330", "arm,primecell"; 125 broken-no-flushp; 126 reg = <0xffb20000 0x4000>; 127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 129 #dma-cells = <1>; 130 clocks = <&cru ACLK_DMAC1>; 131 clock-names = "apb_pclk"; 132 }; 133 }; 134 135 xin24m: oscillator { 136 compatible = "fixed-clock"; 137 clock-frequency = <24000000>; 138 clock-output-names = "xin24m"; 139 #clock-cells = <0>; 140 }; 141 142 timer { 143 arm,use-physical-timer; 144 compatible = "arm,armv7-timer"; 145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 149 clock-frequency = <24000000>; 150 always-on; 151 }; 152 153 display-subsystem { 154 compatible = "rockchip,display-subsystem"; 155 ports = <&vopl_out>, <&vopb_out>; 156 }; 157 158 sdmmc: dwmmc@ff0c0000 { 159 compatible = "rockchip,rk3288-dw-mshc"; 160 clock-freq-min-max = <400000 150000000>; 161 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 162 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 163 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 164 fifo-depth = <0x100>; 165 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 166 reg = <0xff0c0000 0x4000>; 167 status = "disabled"; 168 }; 169 170 sdio0: dwmmc@ff0d0000 { 171 compatible = "rockchip,rk3288-dw-mshc"; 172 clock-freq-min-max = <400000 150000000>; 173 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 174 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 175 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 176 fifo-depth = <0x100>; 177 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 178 reg = <0xff0d0000 0x4000>; 179 status = "disabled"; 180 }; 181 182 sdio1: dwmmc@ff0e0000 { 183 compatible = "rockchip,rk3288-dw-mshc"; 184 clock-freq-min-max = <400000 150000000>; 185 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 186 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 187 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 188 fifo-depth = <0x100>; 189 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 190 reg = <0xff0e0000 0x4000>; 191 status = "disabled"; 192 }; 193 194 emmc: dwmmc@ff0f0000 { 195 compatible = "rockchip,rk3288-dw-mshc"; 196 clock-freq-min-max = <400000 150000000>; 197 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 198 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 199 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 200 fifo-depth = <0x100>; 201 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 202 reg = <0xff0f0000 0x4000>; 203 status = "disabled"; 204 }; 205 206 saradc: saradc@ff100000 { 207 compatible = "rockchip,saradc"; 208 reg = <0xff100000 0x100>; 209 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 210 #io-channel-cells = <1>; 211 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 212 clock-names = "saradc", "apb_pclk"; 213 status = "disabled"; 214 }; 215 216 spi0: spi@ff110000 { 217 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 218 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 219 clock-names = "spiclk", "apb_pclk"; 220 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 221 dma-names = "tx", "rx"; 222 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 225 reg = <0xff110000 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 status = "disabled"; 229 }; 230 231 spi1: spi@ff120000 { 232 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 233 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 234 clock-names = "spiclk", "apb_pclk"; 235 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 236 dma-names = "tx", "rx"; 237 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 240 reg = <0xff120000 0x1000>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 status = "disabled"; 244 }; 245 246 spi2: spi@ff130000 { 247 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 248 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 249 clock-names = "spiclk", "apb_pclk"; 250 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 251 dma-names = "tx", "rx"; 252 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 255 reg = <0xff130000 0x1000>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 status = "disabled"; 259 }; 260 261 i2c1: i2c@ff140000 { 262 compatible = "rockchip,rk3288-i2c"; 263 reg = <0xff140000 0x1000>; 264 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 clock-names = "i2c"; 268 clocks = <&cru PCLK_I2C1>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&i2c1_xfer>; 271 status = "disabled"; 272 }; 273 274 i2c3: i2c@ff150000 { 275 compatible = "rockchip,rk3288-i2c"; 276 reg = <0xff150000 0x1000>; 277 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 clock-names = "i2c"; 281 clocks = <&cru PCLK_I2C3>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c3_xfer>; 284 status = "disabled"; 285 }; 286 287 i2c4: i2c@ff160000 { 288 compatible = "rockchip,rk3288-i2c"; 289 reg = <0xff160000 0x1000>; 290 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 clock-names = "i2c"; 294 clocks = <&cru PCLK_I2C4>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&i2c4_xfer>; 297 status = "disabled"; 298 }; 299 300 i2c5: i2c@ff170000 { 301 compatible = "rockchip,rk3288-i2c"; 302 reg = <0xff170000 0x1000>; 303 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 clock-names = "i2c"; 307 clocks = <&cru PCLK_I2C5>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&i2c5_xfer>; 310 status = "disabled"; 311 }; 312 uart0: serial@ff180000 { 313 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 314 reg = <0xff180000 0x100>; 315 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 316 reg-shift = <2>; 317 reg-io-width = <4>; 318 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 319 clock-names = "baudclk", "apb_pclk"; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&uart0_xfer>; 322 status = "disabled"; 323 }; 324 325 uart1: serial@ff190000 { 326 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 327 reg = <0xff190000 0x100>; 328 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 329 reg-shift = <2>; 330 reg-io-width = <4>; 331 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 332 clock-names = "baudclk", "apb_pclk"; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&uart1_xfer>; 335 status = "disabled"; 336 }; 337 338 uart2: serial@ff690000 { 339 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 340 reg = <0xff690000 0x100>; 341 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 342 reg-shift = <2>; 343 reg-io-width = <4>; 344 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 345 clock-names = "baudclk", "apb_pclk"; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&uart2_xfer>; 348 status = "disabled"; 349 }; 350 uart3: serial@ff1b0000 { 351 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 352 reg = <0xff1b0000 0x100>; 353 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 354 reg-shift = <2>; 355 reg-io-width = <4>; 356 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 357 clock-names = "baudclk", "apb_pclk"; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&uart3_xfer>; 360 status = "disabled"; 361 }; 362 363 uart4: serial@ff1c0000 { 364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 365 reg = <0xff1c0000 0x100>; 366 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 367 reg-shift = <2>; 368 reg-io-width = <4>; 369 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 370 clock-names = "baudclk", "apb_pclk"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&uart4_xfer>; 373 status = "disabled"; 374 }; 375 thermal: thermal-zones { 376 #include "rk3288-thermal.dtsi" 377 }; 378 379 tsadc: tsadc@ff280000 { 380 compatible = "rockchip,rk3288-tsadc"; 381 reg = <0xff280000 0x100>; 382 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 384 clock-names = "tsadc", "apb_pclk"; 385 resets = <&cru SRST_TSADC>; 386 reset-names = "tsadc-apb"; 387 pinctrl-names = "otp_out"; 388 pinctrl-0 = <&otp_out>; 389 #thermal-sensor-cells = <1>; 390 hw-shut-temp = <125000>; 391 status = "disabled"; 392 }; 393 394 gmac: ethernet@ff290000 { 395 compatible = "rockchip,rk3288-gmac"; 396 reg = <0xff290000 0x10000>; 397 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 398 interrupt-names = "macirq"; 399 rockchip,grf = <&grf>; 400 clocks = <&cru SCLK_MAC>, 401 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 402 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 403 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 404 clock-names = "stmmaceth", 405 "mac_clk_rx", "mac_clk_tx", 406 "clk_mac_ref", "clk_mac_refout", 407 "aclk_mac", "pclk_mac"; 408 }; 409 410 usb_host0_ehci: usb@ff500000 { 411 compatible = "generic-ehci"; 412 reg = <0xff500000 0x100>; 413 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&cru HCLK_USBHOST0>; 415 clock-names = "usbhost"; 416 phys = <&usbphy1>; 417 phy-names = "usb"; 418 status = "disabled"; 419 }; 420 421 /* NOTE: ohci@ff520000 doesn't actually work on hardware */ 422 423 usb_host1: usb@ff540000 { 424 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 425 "snps,dwc2"; 426 reg = <0xff540000 0x40000>; 427 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&cru HCLK_USBHOST1>; 429 clock-names = "otg"; 430 phys = <&usbphy2>; 431 phy-names = "usb2-phy"; 432 status = "disabled"; 433 }; 434 435 usb_otg: usb@ff580000 { 436 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 437 "snps,dwc2"; 438 reg = <0xff580000 0x40000>; 439 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cru HCLK_OTG0>; 441 clock-names = "otg"; 442 phys = <&usbphy0>; 443 phy-names = "usb2-phy"; 444 status = "disabled"; 445 }; 446 447 usb_hsic: usb@ff5c0000 { 448 compatible = "generic-ehci"; 449 reg = <0xff5c0000 0x100>; 450 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cru HCLK_HSIC>; 452 clock-names = "usbhost"; 453 status = "disabled"; 454 }; 455 456 dmc: dmc@ff610000 { 457 compatible = "rockchip,rk3288-dmc", "syscon"; 458 rockchip,cru = <&cru>; 459 rockchip,grf = <&grf>; 460 rockchip,pmu = <&pmu>; 461 rockchip,sgrf = <&sgrf>; 462 rockchip,noc = <&noc>; 463 reg = <0xff610000 0x3fc 464 0xff620000 0x294 465 0xff630000 0x3fc 466 0xff640000 0x294>; 467 rockchip,sram = <&ddr_sram>; 468 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, 469 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, 470 <&cru ARMCLK>; 471 clock-names = "pclk_ddrupctl0", "pclk_publ0", 472 "pclk_ddrupctl1", "pclk_publ1", 473 "arm_clk"; 474 }; 475 476 i2c0: i2c@ff650000 { 477 compatible = "rockchip,rk3288-i2c"; 478 reg = <0xff650000 0x1000>; 479 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 clock-names = "i2c"; 483 clocks = <&cru PCLK_I2C0>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&i2c0_xfer>; 486 status = "disabled"; 487 }; 488 489 i2c2: i2c@ff660000 { 490 compatible = "rockchip,rk3288-i2c"; 491 reg = <0xff660000 0x1000>; 492 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 clock-names = "i2c"; 496 clocks = <&cru PCLK_I2C2>; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&i2c2_xfer>; 499 status = "disabled"; 500 }; 501 502 pwm0: pwm@ff680000 { 503 compatible = "rockchip,rk3288-pwm"; 504 reg = <0xff680000 0x10>; 505 #pwm-cells = <3>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&pwm0_pin>; 508 clocks = <&cru PCLK_PWM>; 509 clock-names = "pwm"; 510 rockchip,grf = <&grf>; 511 status = "disabled"; 512 }; 513 514 pwm1: pwm@ff680010 { 515 compatible = "rockchip,rk3288-pwm"; 516 reg = <0xff680010 0x10>; 517 #pwm-cells = <3>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pwm1_pin>; 520 clocks = <&cru PCLK_PWM>; 521 clock-names = "pwm"; 522 rockchip,grf = <&grf>; 523 status = "disabled"; 524 }; 525 526 pwm2: pwm@ff680020 { 527 compatible = "rockchip,rk3288-pwm"; 528 reg = <0xff680020 0x10>; 529 #pwm-cells = <3>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pwm2_pin>; 532 clocks = <&cru PCLK_PWM>; 533 clock-names = "pwm"; 534 rockchip,grf = <&grf>; 535 status = "disabled"; 536 }; 537 538 pwm3: pwm@ff680030 { 539 compatible = "rockchip,rk3288-pwm"; 540 reg = <0xff680030 0x10>; 541 #pwm-cells = <2>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pwm3_pin>; 544 clocks = <&cru PCLK_PWM>; 545 clock-names = "pwm"; 546 rockchip,grf = <&grf>; 547 status = "disabled"; 548 }; 549 550 bus_intmem@ff700000 { 551 compatible = "mmio-sram"; 552 reg = <0xff700000 0x18000>; 553 #address-cells = <1>; 554 #size-cells = <1>; 555 ranges = <0 0xff700000 0x18000>; 556 smp-sram@0 { 557 compatible = "rockchip,rk3066-smp-sram"; 558 reg = <0x00 0x10>; 559 }; 560 ddr_sram: ddr-sram@1000 { 561 compatible = "rockchip,rk3288-ddr-sram"; 562 reg = <0x1000 0x4000>; 563 }; 564 }; 565 566 sram@ff720000 { 567 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 568 reg = <0xff720000 0x1000>; 569 }; 570 571 pmu: power-management@ff730000 { 572 compatible = "rockchip,rk3288-pmu", "syscon"; 573 reg = <0xff730000 0x100>; 574 }; 575 576 sgrf: syscon@ff740000 { 577 compatible = "rockchip,rk3288-sgrf", "syscon"; 578 reg = <0xff740000 0x1000>; 579 }; 580 581 cru: clock-controller@ff760000 { 582 compatible = "rockchip,rk3288-cru"; 583 reg = <0xff760000 0x1000>; 584 rockchip,grf = <&grf>; 585 #clock-cells = <1>; 586 #reset-cells = <1>; 587 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, 588 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 589 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 590 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 591 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 592 <&cru PCLK_PERI>; 593 assigned-clock-rates = <0>, <0>, 594 <594000000>, <400000000>, 595 <500000000>, <300000000>, 596 <150000000>, <75000000>, 597 <300000000>, <150000000>, 598 <75000000>; 599 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>; 600 }; 601 602 grf: syscon@ff770000 { 603 compatible = "rockchip,rk3288-grf", "syscon"; 604 reg = <0xff770000 0x1000>; 605 }; 606 607 wdt: watchdog@ff800000 { 608 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 609 reg = <0xff800000 0x100>; 610 clocks = <&cru PCLK_WDT>; 611 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 612 status = "disabled"; 613 }; 614 615 i2s: i2s@ff890000 { 616 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 617 reg = <0xff890000 0x10000>; 618 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 622 dma-names = "tx", "rx"; 623 clock-names = "i2s_hclk", "i2s_clk"; 624 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&i2s0_bus>; 627 status = "disabled"; 628 }; 629 630 vopb: vop@ff930000 { 631 compatible = "rockchip,rk3288-vop"; 632 reg = <0xff930000 0x19c>; 633 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 635 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 636 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 637 reset-names = "axi", "ahb", "dclk"; 638 iommus = <&vopb_mmu>; 639 power-domains = <&power RK3288_PD_VIO>; 640 status = "disabled"; 641 vopb_out: port { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 vopb_out_edp: endpoint@0 { 645 reg = <0>; 646 remote-endpoint = <&edp_in_vopb>; 647 }; 648 vopb_out_hdmi: endpoint@1 { 649 reg = <1>; 650 remote-endpoint = <&hdmi_in_vopb>; 651 }; 652 }; 653 }; 654 655 vopb_mmu: iommu@ff930300 { 656 compatible = "rockchip,iommu"; 657 reg = <0xff930300 0x100>; 658 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 659 interrupt-names = "vopb_mmu"; 660 power-domains = <&power RK3288_PD_VIO>; 661 #iommu-cells = <0>; 662 status = "disabled"; 663 }; 664 665 vopl: vop@ff940000 { 666 compatible = "rockchip,rk3288-vop"; 667 reg = <0xff940000 0x19c>; 668 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 670 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 671 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 672 reset-names = "axi", "ahb", "dclk"; 673 iommus = <&vopl_mmu>; 674 power-domains = <&power RK3288_PD_VIO>; 675 status = "disabled"; 676 vopl_out: port { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 vopl_out_edp: endpoint@0 { 680 reg = <0>; 681 remote-endpoint = <&edp_in_vopl>; 682 }; 683 vopl_out_hdmi: endpoint@1 { 684 reg = <1>; 685 remote-endpoint = <&hdmi_in_vopl>; 686 }; 687 688 }; 689 }; 690 691 vopl_mmu: iommu@ff940300 { 692 compatible = "rockchip,iommu"; 693 reg = <0xff940300 0x100>; 694 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 695 interrupt-names = "vopl_mmu"; 696 power-domains = <&power RK3288_PD_VIO>; 697 #iommu-cells = <0>; 698 status = "disabled"; 699 }; 700 701 edp: edp@ff970000 { 702 compatible = "rockchip,rk3288-edp"; 703 reg = <0xff970000 0x4000>; 704 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; 706 rockchip,grf = <&grf>; 707 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; 708 resets = <&cru 111>; 709 reset-names = "edp"; 710 power-domains = <&power RK3288_PD_VIO>; 711 status = "disabled"; 712 ports { 713 edp_in: port { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 edp_in_vopb: endpoint@0 { 717 reg = <0>; 718 remote-endpoint = <&vopb_out_edp>; 719 }; 720 edp_in_vopl: endpoint@1 { 721 reg = <1>; 722 remote-endpoint = <&vopl_out_edp>; 723 }; 724 }; 725 }; 726 }; 727 728 hdmi: hdmi@ff980000 { 729 compatible = "rockchip,rk3288-dw-hdmi"; 730 reg = <0xff980000 0x20000>; 731 reg-io-width = <4>; 732 ddc-i2c-bus = <&i2c5>; 733 rockchip,grf = <&grf>; 734 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; 736 clock-names = "iahb", "isfr"; 737 status = "disabled"; 738 ports { 739 hdmi_in: port { 740 #address-cells = <1>; 741 #size-cells = <0>; 742 hdmi_in_vopb: endpoint@0 { 743 reg = <0>; 744 remote-endpoint = <&vopb_out_hdmi>; 745 }; 746 hdmi_in_vopl: endpoint@1 { 747 reg = <1>; 748 remote-endpoint = <&vopl_out_hdmi>; 749 }; 750 }; 751 }; 752 }; 753 754 hdmi_audio: hdmi_audio { 755 compatible = "rockchip,rk3288-hdmi-audio"; 756 i2s-controller = <&i2s>; 757 status = "disable"; 758 }; 759 760 vpu: video-codec@ff9a0000 { 761 compatible = "rockchip,rk3288-vpu"; 762 reg = <0xff9a0000 0x800>; 763 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-names = "vepu", "vdpu"; 766 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 767 clock-names = "aclk_vcodec", "hclk_vcodec"; 768 power-domains = <&power RK3288_PD_VIDEO>; 769 iommus = <&vpu_mmu>; 770 }; 771 772 vpu_mmu: iommu@ff9a0800 { 773 compatible = "rockchip,iommu"; 774 reg = <0xff9a0800 0x100>; 775 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 776 interrupt-names = "vpu_mmu"; 777 power-domains = <&power RK3288_PD_VIDEO>; 778 #iommu-cells = <0>; 779 }; 780 781 gpu: gpu@ffa30000 { 782 compatible = "arm,malit764", 783 "arm,malit76x", 784 "arm,malit7xx", 785 "arm,mali-midgard"; 786 reg = <0xffa30000 0x10000>; 787 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 790 interrupt-names = "JOB", "MMU", "GPU"; 791 clocks = <&cru ACLK_GPU>; 792 clock-names = "aclk_gpu"; 793 operating-points = < 794 /* KHz uV */ 795 100000 950000 796 200000 950000 797 300000 1000000 798 400000 1100000 799 /* 500000 1200000 - See crosbug.com/p/33857 */ 800 600000 1250000 801 >; 802 power-domains = <&power RK3288_PD_GPU>; 803 status = "disabled"; 804 }; 805 806 noc: syscon@ffac0000 { 807 compatible = "rockchip,rk3288-noc", "syscon"; 808 reg = <0xffac0000 0x2000>; 809 }; 810 811 efuse: efuse@ffb40000 { 812 compatible = "rockchip,rk3288-efuse"; 813 reg = <0xffb40000 0x10000>; 814 status = "disabled"; 815 }; 816 817 gic: interrupt-controller@ffc01000 { 818 compatible = "arm,gic-400"; 819 interrupt-controller; 820 #interrupt-cells = <3>; 821 #address-cells = <0>; 822 823 reg = <0xffc01000 0x1000>, 824 <0xffc02000 0x1000>, 825 <0xffc04000 0x2000>, 826 <0xffc06000 0x2000>; 827 interrupts = <GIC_PPI 9 0xf04>; 828 }; 829 830 cpuidle: cpuidle { 831 compatible = "rockchip,rk3288-cpuidle"; 832 }; 833 834 usbphy: phy { 835 compatible = "rockchip,rk3288-usb-phy"; 836 rockchip,grf = <&grf>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 841 usbphy0: usb-phy0 { 842 #phy-cells = <0>; 843 reg = <0x320>; 844 clocks = <&cru SCLK_OTGPHY0>; 845 clock-names = "phyclk"; 846 }; 847 848 usbphy1: usb-phy1 { 849 #phy-cells = <0>; 850 reg = <0x334>; 851 clocks = <&cru SCLK_OTGPHY1>; 852 clock-names = "phyclk"; 853 }; 854 855 usbphy2: usb-phy2 { 856 #phy-cells = <0>; 857 reg = <0x348>; 858 clocks = <&cru SCLK_OTGPHY2>; 859 clock-names = "phyclk"; 860 }; 861 }; 862 863 pinctrl: pinctrl { 864 compatible = "rockchip,rk3288-pinctrl"; 865 rockchip,grf = <&grf>; 866 rockchip,pmu = <&pmu>; 867 #address-cells = <1>; 868 #size-cells = <1>; 869 ranges; 870 871 gpio0: gpio0@ff750000 { 872 compatible = "rockchip,gpio-bank"; 873 reg = <0xff750000 0x100>; 874 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&cru PCLK_GPIO0>; 876 877 gpio-controller; 878 #gpio-cells = <2>; 879 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 }; 883 884 gpio1: gpio1@ff780000 { 885 compatible = "rockchip,gpio-bank"; 886 reg = <0xff780000 0x100>; 887 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&cru PCLK_GPIO1>; 889 890 gpio-controller; 891 #gpio-cells = <2>; 892 893 interrupt-controller; 894 #interrupt-cells = <2>; 895 }; 896 897 gpio2: gpio2@ff790000 { 898 compatible = "rockchip,gpio-bank"; 899 reg = <0xff790000 0x100>; 900 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&cru PCLK_GPIO2>; 902 903 gpio-controller; 904 #gpio-cells = <2>; 905 906 interrupt-controller; 907 #interrupt-cells = <2>; 908 }; 909 910 gpio3: gpio3@ff7a0000 { 911 compatible = "rockchip,gpio-bank"; 912 reg = <0xff7a0000 0x100>; 913 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&cru PCLK_GPIO3>; 915 916 gpio-controller; 917 #gpio-cells = <2>; 918 919 interrupt-controller; 920 #interrupt-cells = <2>; 921 }; 922 923 gpio4: gpio4@ff7b0000 { 924 compatible = "rockchip,gpio-bank"; 925 reg = <0xff7b0000 0x100>; 926 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&cru PCLK_GPIO4>; 928 929 gpio-controller; 930 #gpio-cells = <2>; 931 932 interrupt-controller; 933 #interrupt-cells = <2>; 934 }; 935 936 gpio5: gpio5@ff7c0000 { 937 compatible = "rockchip,gpio-bank"; 938 reg = <0xff7c0000 0x100>; 939 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&cru PCLK_GPIO5>; 941 942 gpio-controller; 943 #gpio-cells = <2>; 944 945 interrupt-controller; 946 #interrupt-cells = <2>; 947 }; 948 949 gpio6: gpio6@ff7d0000 { 950 compatible = "rockchip,gpio-bank"; 951 reg = <0xff7d0000 0x100>; 952 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&cru PCLK_GPIO6>; 954 955 gpio-controller; 956 #gpio-cells = <2>; 957 958 interrupt-controller; 959 #interrupt-cells = <2>; 960 }; 961 962 gpio7: gpio7@ff7e0000 { 963 compatible = "rockchip,gpio-bank"; 964 reg = <0xff7e0000 0x100>; 965 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&cru PCLK_GPIO7>; 967 968 gpio-controller; 969 #gpio-cells = <2>; 970 971 interrupt-controller; 972 #interrupt-cells = <2>; 973 }; 974 975 gpio8: gpio8@ff7f0000 { 976 compatible = "rockchip,gpio-bank"; 977 reg = <0xff7f0000 0x100>; 978 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&cru PCLK_GPIO8>; 980 981 gpio-controller; 982 #gpio-cells = <2>; 983 984 interrupt-controller; 985 #interrupt-cells = <2>; 986 }; 987 988 pcfg_pull_up: pcfg-pull-up { 989 bias-pull-up; 990 }; 991 992 pcfg_pull_down: pcfg-pull-down { 993 bias-pull-down; 994 }; 995 996 pcfg_pull_none: pcfg-pull-none { 997 bias-disable; 998 }; 999 1000 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1001 bias-disable; 1002 drive-strength = <12>; 1003 }; 1004 1005 sleep { 1006 global_pwroff: global-pwroff { 1007 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; 1008 }; 1009 1010 ddrio_pwroff: ddrio-pwroff { 1011 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; 1012 }; 1013 1014 ddr0_retention: ddr0-retention { 1015 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; 1016 }; 1017 1018 ddr1_retention: ddr1-retention { 1019 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; 1020 }; 1021 }; 1022 1023 i2c0 { 1024 i2c0_xfer: i2c0-xfer { 1025 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, 1026 <0 16 RK_FUNC_1 &pcfg_pull_none>; 1027 }; 1028 }; 1029 1030 i2c1 { 1031 i2c1_xfer: i2c1-xfer { 1032 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, 1033 <8 5 RK_FUNC_1 &pcfg_pull_none>; 1034 }; 1035 }; 1036 1037 i2c2 { 1038 i2c2_xfer: i2c2-xfer { 1039 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, 1040 <6 10 RK_FUNC_1 &pcfg_pull_none>; 1041 }; 1042 }; 1043 1044 i2c3 { 1045 i2c3_xfer: i2c3-xfer { 1046 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, 1047 <2 17 RK_FUNC_1 &pcfg_pull_none>; 1048 }; 1049 }; 1050 1051 i2c4 { 1052 i2c4_xfer: i2c4-xfer { 1053 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, 1054 <7 18 RK_FUNC_1 &pcfg_pull_none>; 1055 }; 1056 }; 1057 1058 i2c5 { 1059 i2c5_xfer: i2c5-xfer { 1060 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, 1061 <7 20 RK_FUNC_1 &pcfg_pull_none>; 1062 }; 1063 }; 1064 1065 i2s0 { 1066 i2s0_bus: i2s0-bus { 1067 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, 1068 <6 1 RK_FUNC_1 &pcfg_pull_none>, 1069 <6 2 RK_FUNC_1 &pcfg_pull_none>, 1070 <6 3 RK_FUNC_1 &pcfg_pull_none>, 1071 <6 4 RK_FUNC_1 &pcfg_pull_none>, 1072 <6 8 RK_FUNC_1 &pcfg_pull_none>; 1073 }; 1074 }; 1075 1076 sdmmc { 1077 sdmmc_clk: sdmmc-clk { 1078 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; 1079 }; 1080 1081 sdmmc_cmd: sdmmc-cmd { 1082 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; 1083 }; 1084 1085 sdmmc_cd: sdmcc-cd { 1086 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; 1087 }; 1088 1089 sdmmc_bus1: sdmmc-bus1 { 1090 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; 1091 }; 1092 1093 sdmmc_bus4: sdmmc-bus4 { 1094 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, 1095 <6 17 RK_FUNC_1 &pcfg_pull_up>, 1096 <6 18 RK_FUNC_1 &pcfg_pull_up>, 1097 <6 19 RK_FUNC_1 &pcfg_pull_up>; 1098 }; 1099 }; 1100 1101 sdio0 { 1102 sdio0_bus1: sdio0-bus1 { 1103 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; 1104 }; 1105 1106 sdio0_bus4: sdio0-bus4 { 1107 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, 1108 <4 21 RK_FUNC_1 &pcfg_pull_up>, 1109 <4 22 RK_FUNC_1 &pcfg_pull_up>, 1110 <4 23 RK_FUNC_1 &pcfg_pull_up>; 1111 }; 1112 1113 sdio0_cmd: sdio0-cmd { 1114 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; 1115 }; 1116 1117 sdio0_clk: sdio0-clk { 1118 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; 1119 }; 1120 1121 sdio0_cd: sdio0-cd { 1122 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; 1123 }; 1124 1125 sdio0_wp: sdio0-wp { 1126 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; 1127 }; 1128 1129 sdio0_pwr: sdio0-pwr { 1130 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; 1131 }; 1132 1133 sdio0_bkpwr: sdio0-bkpwr { 1134 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; 1135 }; 1136 1137 sdio0_int: sdio0-int { 1138 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; 1139 }; 1140 }; 1141 1142 sdio1 { 1143 sdio1_bus1: sdio1-bus1 { 1144 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; 1145 }; 1146 1147 sdio1_bus4: sdio1-bus4 { 1148 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, 1149 <3 25 RK_FUNC_4 &pcfg_pull_up>, 1150 <3 26 RK_FUNC_4 &pcfg_pull_up>, 1151 <3 27 RK_FUNC_4 &pcfg_pull_up>; 1152 }; 1153 1154 sdio1_cd: sdio1-cd { 1155 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; 1156 }; 1157 1158 sdio1_wp: sdio1-wp { 1159 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; 1160 }; 1161 1162 sdio1_bkpwr: sdio1-bkpwr { 1163 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; 1164 }; 1165 1166 sdio1_int: sdio1-int { 1167 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; 1168 }; 1169 1170 sdio1_cmd: sdio1-cmd { 1171 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; 1172 }; 1173 1174 sdio1_clk: sdio1-clk { 1175 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; 1176 }; 1177 1178 sdio1_pwr: sdio1-pwr { 1179 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; 1180 }; 1181 }; 1182 1183 emmc { 1184 emmc_clk: emmc-clk { 1185 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; 1186 }; 1187 1188 emmc_cmd: emmc-cmd { 1189 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; 1190 }; 1191 1192 emmc_pwr: emmc-pwr { 1193 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; 1194 }; 1195 1196 emmc_bus1: emmc-bus1 { 1197 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; 1198 }; 1199 1200 emmc_bus4: emmc-bus4 { 1201 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1202 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1203 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1204 <3 3 RK_FUNC_2 &pcfg_pull_up>; 1205 }; 1206 1207 emmc_bus8: emmc-bus8 { 1208 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, 1209 <3 1 RK_FUNC_2 &pcfg_pull_up>, 1210 <3 2 RK_FUNC_2 &pcfg_pull_up>, 1211 <3 3 RK_FUNC_2 &pcfg_pull_up>, 1212 <3 4 RK_FUNC_2 &pcfg_pull_up>, 1213 <3 5 RK_FUNC_2 &pcfg_pull_up>, 1214 <3 6 RK_FUNC_2 &pcfg_pull_up>, 1215 <3 7 RK_FUNC_2 &pcfg_pull_up>; 1216 }; 1217 }; 1218 1219 spi0 { 1220 spi0_clk: spi0-clk { 1221 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; 1222 }; 1223 spi0_cs0: spi0-cs0 { 1224 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; 1225 }; 1226 spi0_tx: spi0-tx { 1227 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; 1228 }; 1229 spi0_rx: spi0-rx { 1230 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; 1231 }; 1232 spi0_cs1: spi0-cs1 { 1233 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; 1234 }; 1235 }; 1236 spi1 { 1237 spi1_clk: spi1-clk { 1238 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; 1239 }; 1240 spi1_cs0: spi1-cs0 { 1241 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; 1242 }; 1243 spi1_rx: spi1-rx { 1244 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; 1245 }; 1246 spi1_tx: spi1-tx { 1247 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; 1248 }; 1249 }; 1250 1251 spi2 { 1252 spi2_cs1: spi2-cs1 { 1253 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; 1254 }; 1255 spi2_clk: spi2-clk { 1256 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; 1257 }; 1258 spi2_cs0: spi2-cs0 { 1259 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; 1260 }; 1261 spi2_rx: spi2-rx { 1262 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; 1263 }; 1264 spi2_tx: spi2-tx { 1265 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; 1266 }; 1267 }; 1268 1269 uart0 { 1270 uart0_xfer: uart0-xfer { 1271 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, 1272 <4 17 RK_FUNC_1 &pcfg_pull_none>; 1273 }; 1274 1275 uart0_cts: uart0-cts { 1276 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; 1277 }; 1278 1279 uart0_rts: uart0-rts { 1280 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; 1281 }; 1282 }; 1283 1284 uart1 { 1285 uart1_xfer: uart1-xfer { 1286 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, 1287 <5 9 RK_FUNC_1 &pcfg_pull_none>; 1288 }; 1289 1290 uart1_cts: uart1-cts { 1291 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; 1292 }; 1293 1294 uart1_rts: uart1-rts { 1295 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; 1296 }; 1297 }; 1298 1299 uart2 { 1300 uart2_xfer: uart2-xfer { 1301 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, 1302 <7 23 RK_FUNC_1 &pcfg_pull_none>; 1303 }; 1304 /* no rts / cts for uart2 */ 1305 }; 1306 1307 uart3 { 1308 uart3_xfer: uart3-xfer { 1309 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, 1310 <7 8 RK_FUNC_1 &pcfg_pull_none>; 1311 }; 1312 1313 uart3_cts: uart3-cts { 1314 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; 1315 }; 1316 1317 uart3_rts: uart3-rts { 1318 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; 1319 }; 1320 }; 1321 1322 uart4 { 1323 uart4_xfer: uart4-xfer { 1324 rockchip,pins = <5 12 3 &pcfg_pull_up>, 1325 <5 13 3 &pcfg_pull_none>; 1326 }; 1327 1328 uart4_cts: uart4-cts { 1329 rockchip,pins = <5 14 3 &pcfg_pull_none>; 1330 }; 1331 1332 uart4_rts: uart4-rts { 1333 rockchip,pins = <5 15 3 &pcfg_pull_none>; 1334 }; 1335 }; 1336 1337 tsadc { 1338 otp_out: otp-out { 1339 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 1340 }; 1341 }; 1342 1343 pwm0 { 1344 pwm0_pin: pwm0-pin { 1345 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1346 }; 1347 }; 1348 1349 pwm1 { 1350 pwm1_pin: pwm1-pin { 1351 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; 1352 }; 1353 }; 1354 1355 pwm2 { 1356 pwm2_pin: pwm2-pin { 1357 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; 1358 }; 1359 }; 1360 1361 pwm3 { 1362 pwm3_pin: pwm3-pin { 1363 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; 1364 }; 1365 }; 1366 1367 gmac { 1368 rgmii_pins: rgmii-pins { 1369 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1370 <3 31 3 &pcfg_pull_none>, 1371 <3 26 3 &pcfg_pull_none>, 1372 <3 27 3 &pcfg_pull_none>, 1373 <3 28 3 &pcfg_pull_none_12ma>, 1374 <3 29 3 &pcfg_pull_none_12ma>, 1375 <3 24 3 &pcfg_pull_none_12ma>, 1376 <3 25 3 &pcfg_pull_none_12ma>, 1377 <4 0 3 &pcfg_pull_none>, 1378 <4 5 3 &pcfg_pull_none>, 1379 <4 6 3 &pcfg_pull_none>, 1380 <4 9 3 &pcfg_pull_none_12ma>, 1381 <4 4 3 &pcfg_pull_none_12ma>, 1382 <4 1 3 &pcfg_pull_none>, 1383 <4 3 3 &pcfg_pull_none>; 1384 }; 1385 1386 rmii_pins: rmii-pins { 1387 rockchip,pins = <3 30 3 &pcfg_pull_none>, 1388 <3 31 3 &pcfg_pull_none>, 1389 <3 28 3 &pcfg_pull_none>, 1390 <3 29 3 &pcfg_pull_none>, 1391 <4 0 3 &pcfg_pull_none>, 1392 <4 5 3 &pcfg_pull_none>, 1393 <4 4 3 &pcfg_pull_none>, 1394 <4 1 3 &pcfg_pull_none>, 1395 <4 2 3 &pcfg_pull_none>, 1396 <4 3 3 &pcfg_pull_none>; 1397 }; 1398 }; 1399 }; 1400 1401 power: power-controller { 1402 compatible = "rockchip,rk3288-power-controller"; 1403 #power-domain-cells = <1>; 1404 rockchip,pmu = <&pmu>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 1408 pd_gpu { 1409 reg = <RK3288_PD_GPU>; 1410 clocks = <&cru ACLK_GPU>; 1411 }; 1412 1413 pd_hevc { 1414 reg = <RK3288_PD_HEVC>; 1415 clocks = <&cru ACLK_HEVC>, 1416 <&cru SCLK_HEVC_CABAC>, 1417 <&cru SCLK_HEVC_CORE>, 1418 <&cru HCLK_HEVC>; 1419 }; 1420 1421 pd_vio { 1422 reg = <RK3288_PD_VIO>; 1423 clocks = <&cru ACLK_IEP>, 1424 <&cru ACLK_ISP>, 1425 <&cru ACLK_RGA>, 1426 <&cru ACLK_VIP>, 1427 <&cru ACLK_VOP0>, 1428 <&cru ACLK_VOP1>, 1429 <&cru DCLK_VOP0>, 1430 <&cru DCLK_VOP1>, 1431 <&cru HCLK_IEP>, 1432 <&cru HCLK_ISP>, 1433 <&cru HCLK_RGA>, 1434 <&cru HCLK_VIP>, 1435 <&cru HCLK_VOP0>, 1436 <&cru HCLK_VOP1>, 1437 <&cru PCLK_EDP_CTRL>, 1438 <&cru PCLK_HDMI_CTRL>, 1439 <&cru PCLK_LVDS_PHY>, 1440 <&cru PCLK_MIPI_CSI>, 1441 <&cru PCLK_MIPI_DSI0>, 1442 <&cru PCLK_MIPI_DSI1>, 1443 <&cru SCLK_EDP_24M>, 1444 <&cru SCLK_EDP>, 1445 <&cru SCLK_HDMI_CEC>, 1446 <&cru SCLK_HDMI_HDCP>, 1447 <&cru SCLK_ISP_JPE>, 1448 <&cru SCLK_ISP>, 1449 <&cru SCLK_RGA>; 1450 }; 1451 1452 pd_video { 1453 reg = <RK3288_PD_VIDEO>; 1454 clocks = <&cru ACLK_VCODEC>, 1455 <&cru HCLK_VCODEC>; 1456 }; 1457 }; 1458}; 1459