1/* 2 * Google Veyron (and derivatives) board device tree source 3 * 4 * Copyright 2014 Google, Inc 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9#include <dt-bindings/clock/rockchip,rk808.h> 10#include <dt-bindings/input/input.h> 11#include "rk3288.dtsi" 12 13/ { 14 memory { 15 reg = <0x0 0x80000000>; 16 }; 17 18 chosen { 19 stdout-path = &uart2; 20 }; 21 22 config { 23 u-boot,dm-pre-reloc; 24 u-boot,boot0 = &spi_flash; 25 }; 26 27 firmware { 28 chromeos { 29 pinctrl-names = "default"; 30 pinctrl-0 = <&fw_wp_ap>; 31 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>; 32 }; 33 }; 34 35 backlight: backlight { 36 compatible = "pwm-backlight"; 37 brightness-levels = < 38 0 1 2 3 4 5 6 7 39 8 9 10 11 12 13 14 15 40 16 17 18 19 20 21 22 23 41 24 25 26 27 28 29 30 31 42 32 33 34 35 36 37 38 39 43 40 41 42 43 44 45 46 47 44 48 49 50 51 52 53 54 55 45 56 57 58 59 60 61 62 63 46 64 65 66 67 68 69 70 71 47 72 73 74 75 76 77 78 79 48 80 81 82 83 84 85 86 87 49 88 89 90 91 92 93 94 95 50 96 97 98 99 100 101 102 103 51 104 105 106 107 108 109 110 111 52 112 113 114 115 116 117 118 119 53 120 121 122 123 124 125 126 127 54 128 129 130 131 132 133 134 135 55 136 137 138 139 140 141 142 143 56 144 145 146 147 148 149 150 151 57 152 153 154 155 156 157 158 159 58 160 161 162 163 164 165 166 167 59 168 169 170 171 172 173 174 175 60 176 177 178 179 180 181 182 183 61 184 185 186 187 188 189 190 191 62 192 193 194 195 196 197 198 199 63 200 201 202 203 204 205 206 207 64 208 209 210 211 212 213 214 215 65 216 217 218 219 220 221 222 223 66 224 225 226 227 228 229 230 231 67 232 233 234 235 236 237 238 239 68 240 241 242 243 244 245 246 247 69 248 249 250 251 252 253 254 255>; 70 default-brightness-level = <128>; 71 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 72 backlight-boot-off; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&bl_en>; 75 pwms = <&pwm0 0 1000000 0>; 76 }; 77 78 panel: panel { 79 compatible ="cnm,n116bgeea2","simple-panel"; 80 status = "okay"; 81 power-supply = <&vcc33_lcd>; 82 backlight = <&backlight>; 83 }; 84 85 gpio_keys: gpio-keys { 86 compatible = "gpio-keys"; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pwr_key_h>; 92 power { 93 label = "Power"; 94 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; 95 linux,code = <KEY_POWER>; 96 debounce-interval = <100>; 97 gpio-key,wakeup; 98 }; 99 }; 100 101 gpio-restart { 102 compatible = "gpio-restart"; 103 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&ap_warm_reset_h>; 106 priority = /bits/ 8 <200>; 107 }; 108 109 emmc_pwrseq: emmc-pwrseq { 110 compatible = "mmc-pwrseq-emmc"; 111 pinctrl-0 = <&emmc_reset>; 112 pinctrl-names = "default"; 113 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; 114 }; 115 116 sound { 117 compatible = "rockchip,rockchip-audio-max98090"; 118 rockchip,model = "ROCKCHIP-I2S"; 119 rockchip,i2s-controller = <&i2s>; 120 rockchip,audio-codec = <&max98090>; 121 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; 122 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 123 rockchip,headset-codec = <&headsetcodec>; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&mic_det>, <&hp_det>; 126 }; 127 128 vdd_logic: pwm-regulator { 129 compatible = "pwm-regulator"; 130 pwms = <&pwm1 0 2000 0>; 131 132 voltage-table = <1350000 0>, 133 <1300000 10>, 134 <1250000 20>, 135 <1200000 31>, 136 <1150000 41>, 137 <1100000 52>, 138 <1050000 62>, 139 <1000000 72>, 140 < 950000 83>; 141 142 regulator-min-microvolt = <950000>; 143 regulator-max-microvolt = <1350000>; 144 regulator-name = "vdd_logic"; 145 regulator-ramp-delay = <4000>; 146 }; 147 148 vcc33_sys: vcc33-sys { 149 compatible = "regulator-fixed"; 150 regulator-name = "vcc33_sys"; 151 regulator-always-on; 152 regulator-boot-on; 153 regulator-min-microvolt = <3300000>; 154 regulator-max-microvolt = <3300000>; 155 vin-supply = <&vccsys>; 156 }; 157 158 vcc_5v: vcc-5v { 159 compatible = "regulator-fixed"; 160 regulator-name = "vcc_5v"; 161 regulator-always-on; 162 regulator-boot-on; 163 regulator-min-microvolt = <5000000>; 164 regulator-max-microvolt = <5000000>; 165 }; 166 167 vcc50_hdmi: vcc50-hdmi { 168 compatible = "regulator-fixed"; 169 regulator-name = "vcc50_hdmi"; 170 regulator-always-on; 171 regulator-boot-on; 172 vin-supply = <&vcc_5v>; 173 }; 174 175 bt_regulator: bt-regulator { 176 /* 177 * On the module itself this is one of these (depending 178 * on the actual card pouplated): 179 * - BT_I2S_WS_BT_RFDISABLE_L 180 * - No connect 181 */ 182 183 compatible = "regulator-fixed"; 184 enable-active-high; 185 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&bt_enable_l>; 188 regulator-name = "bt_regulator"; 189 }; 190 191 wifi_regulator: wifi-regulator { 192 /* 193 * On the module itself this is one of these (depending 194 * on the actual card populated): 195 * - SDIO_RESET_L_WL_REG_ON 196 * - PDN (power down when low) 197 */ 198 199 compatible = "regulator-fixed"; 200 enable-active-high; 201 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&wifi_enable_h>; 204 regulator-name = "wifi_regulator"; 205 206 /* Faux input supply. See bt_regulator description. */ 207 vin-supply = <&bt_regulator>; 208 }; 209 210 io-domains { 211 compatible = "rockchip,rk3288-io-voltage-domain"; 212 rockchip,grf = <&grf>; 213 214 audio-supply = <&vcc18_codec>; 215 bb-supply = <&vcc33_io>; 216 dvp-supply = <&vcc_18>; 217 flash0-supply = <&vcc18_flashio>; 218 gpio1830-supply = <&vcc33_io>; 219 gpio30-supply = <&vcc33_io>; 220 lcdc-supply = <&vcc33_lcd>; 221 sdcard-supply = <&vccio_sd>; 222 wifi-supply = <&vcc18_wl>; 223 }; 224}; 225 226&cpu0 { 227 cpu0-supply = <&vdd_cpu>; 228}; 229 230&dmc { 231 logic-supply = <&vdd_logic>; 232 rockchip,odt-disable-freq = <333000000>; 233 rockchip,dll-disable-freq = <333000000>; 234 rockchip,sr-enable-freq = <333000000>; 235 rockchip,pd-enable-freq = <666000000>; 236 rockchip,auto-self-refresh-cnt = <0>; 237 rockchip,auto-power-down-cnt = <64>; 238 rockchip,ddr-speed-bin = <21>; 239 rockchip,trcd = <10>; 240 rockchip,trp = <10>; 241 operating-points = < 242 /* KHz uV */ 243 200000 1050000 244 333000 1100000 245 533000 1150000 246 666000 1200000 247 >; 248 rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa 249 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 250 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 251 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 252 0x5 0x0>; 253 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 254 0xa60 0x40 0x10 0x0>; 255 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; 256}; 257 258&efuse { 259 status = "okay"; 260}; 261 262&emmc { 263 broken-cd; 264 bus-width = <8>; 265 cap-mmc-highspeed; 266 mmc-hs200-1_8v; 267 mmc-pwrseq = <&emmc_pwrseq>; 268 disable-wp; 269 non-removable; 270 num-slots = <1>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>; 273 status = "okay"; 274}; 275 276&sdio0 { 277 broken-cd; 278 bus-width = <4>; 279 cap-sd-highspeed; 280 sd-uhs-sdr12; 281 sd-uhs-sdr25; 282 sd-uhs-sdr50; 283 sd-uhs-sdr104; 284 cap-sdio-irq; 285 card-external-vcc-supply = <&wifi_regulator>; 286 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, 287 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>; 288 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock"; 289 keep-power-in-suspend; 290 non-removable; 291 num-slots = <1>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; 294 status = "okay"; 295 vmmc-supply = <&vcc33_sys>; 296 vqmmc-supply = <&vcc18_wl>; 297}; 298 299&sdmmc { 300 bus-width = <4>; 301 cap-mmc-highspeed; 302 cap-sd-highspeed; 303 sd-uhs-sdr12; 304 sd-uhs-sdr25; 305 sd-uhs-sdr50; 306 sd-uhs-sdr104; 307 card-detect-delay = <200>; 308 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; 309 num-slots = <1>; 310 status = "okay"; 311 vmmc-supply = <&vcc33_sd>; 312 vqmmc-supply = <&vccio_sd>; 313}; 314 315&spi2 { 316 status = "okay"; 317 u-boot,dm-pre-reloc; 318 319 spi_flash: spiflash@0 { 320 u-boot,dm-pre-reloc; 321 compatible = "spidev", "spi-flash"; 322 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ 323 reg = <0>; 324 }; 325}; 326 327&i2c0 { 328 status = "okay"; 329 330 clock-frequency = <400000>; 331 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ 332 i2c-scl-rising-time-ns = <100>; /* 45ns measured */ 333 u-boot,dm-pre-reloc; 334 335 rk808: pmic@1b { 336 compatible = "rockchip,rk808"; 337 clock-output-names = "xin32k", "wifibt_32kin"; 338 interrupt-parent = <&gpio0>; 339 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pmic_int_l>; 342 reg = <0x1b>; 343 rockchip,system-power-controller; 344 wakeup-source; 345 #clock-cells = <1>; 346 u-boot,dm-pre-reloc; 347 348 vcc1-supply = <&vcc33_sys>; 349 vcc2-supply = <&vcc33_sys>; 350 vcc3-supply = <&vcc33_sys>; 351 vcc4-supply = <&vcc33_sys>; 352 vcc6-supply = <&vcc_5v>; 353 vcc7-supply = <&vcc33_sys>; 354 vcc8-supply = <&vcc33_sys>; 355 vcc9-supply = <&vcc_5v>; 356 vcc10-supply = <&vcc33_sys>; 357 vcc11-supply = <&vcc_5v>; 358 vcc12-supply = <&vcc_18>; 359 360 vddio-supply = <&vcc33_io>; 361 362 regulators { 363 vdd_cpu: DCDC_REG1 { 364 regulator-always-on; 365 regulator-boot-on; 366 regulator-min-microvolt = <750000>; 367 regulator-max-microvolt = <1450000>; 368 regulator-name = "vdd_arm"; 369 regulator-ramp-delay = <6001>; 370 regulator-suspend-mem-disabled; 371 }; 372 373 vdd_gpu: DCDC_REG2 { 374 regulator-always-on; 375 regulator-boot-on; 376 regulator-min-microvolt = <800000>; 377 regulator-max-microvolt = <1250000>; 378 regulator-name = "vdd_gpu"; 379 regulator-ramp-delay = <6001>; 380 regulator-suspend-mem-disabled; 381 }; 382 383 vcc135_ddr: DCDC_REG3 { 384 regulator-always-on; 385 regulator-boot-on; 386 regulator-name = "vcc135_ddr"; 387 regulator-suspend-mem-enabled; 388 }; 389 390 /* 391 * vcc_18 has several aliases. (vcc18_flashio and 392 * vcc18_wl). We'll add those aliases here just to 393 * make it easier to follow the schematic. The signals 394 * are actually hooked together and only separated for 395 * power measurement purposes). 396 */ 397 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { 398 regulator-always-on; 399 regulator-boot-on; 400 regulator-min-microvolt = <1800000>; 401 regulator-max-microvolt = <1800000>; 402 regulator-name = "vcc_18"; 403 regulator-suspend-mem-microvolt = <1800000>; 404 }; 405 406 /* 407 * Note that both vcc33_io and vcc33_pmuio are always 408 * powered together. To simplify the logic in the dts 409 * we just refer to vcc33_io every time something is 410 * powered from vcc33_pmuio. In fact, on later boards 411 * (such as danger) they're the same net. 412 */ 413 vcc33_io: LDO_REG1 { 414 regulator-always-on; 415 regulator-boot-on; 416 regulator-min-microvolt = <3300000>; 417 regulator-max-microvolt = <3300000>; 418 regulator-name = "vcc33_io"; 419 regulator-suspend-mem-microvolt = <3300000>; 420 }; 421 422 vdd_10: LDO_REG3 { 423 regulator-always-on; 424 regulator-boot-on; 425 regulator-min-microvolt = <1000000>; 426 regulator-max-microvolt = <1000000>; 427 regulator-name = "vdd_10"; 428 regulator-suspend-mem-microvolt = <1000000>; 429 }; 430 431 vccio_sd: LDO_REG4 { 432 regulator-min-microvolt = <1800000>; 433 regulator-max-microvolt = <3300000>; 434 regulator-name = "vccio_sd"; 435 regulator-suspend-mem-disabled; 436 }; 437 438 vcc33_sd: LDO_REG5 { 439 regulator-min-microvolt = <3300000>; 440 regulator-max-microvolt = <3300000>; 441 regulator-name = "vcc33_sd"; 442 regulator-suspend-mem-disabled; 443 }; 444 445 vcc18_codec: LDO_REG6 { 446 regulator-always-on; 447 regulator-boot-on; 448 regulator-min-microvolt = <1800000>; 449 regulator-max-microvolt = <1800000>; 450 regulator-name = "vcc18_codec"; 451 regulator-suspend-mem-disabled; 452 }; 453 454 vdd10_lcd_pwren_h: LDO_REG7 { 455 regulator-always-on; 456 regulator-boot-on; 457 regulator-min-microvolt = <2500000>; 458 regulator-max-microvolt = <2500000>; 459 regulator-name = "vdd10_lcd_pwren_h"; 460 regulator-suspend-mem-disabled; 461 }; 462 463 vcc33_lcd: SWITCH_REG1 { 464 regulator-always-on; 465 regulator-boot-on; 466 regulator-name = "vcc33_lcd"; 467 regulator-suspend-mem-disabled; 468 }; 469 }; 470 }; 471}; 472 473&i2c1 { 474 status = "okay"; 475 476 clock-frequency = <400000>; 477 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ 478 i2c-scl-rising-time-ns = <100>; /* 40ns measured */ 479 480 tpm: tpm@20 { 481 compatible = "infineon,slb9645tt"; 482 reg = <0x20>; 483 powered-while-suspended; 484 }; 485}; 486 487&i2c2 { 488 status = "okay"; 489 490 /* 100kHz since 4.7k resistors don't rise fast enough */ 491 clock-frequency = <100000>; 492 i2c-scl-falling-time-ns = <50>; /* 10ns measured */ 493 i2c-scl-rising-time-ns = <800>; /* 600ns measured */ 494 495 max98090: max98090@10 { 496 compatible = "maxim,max98090"; 497 reg = <0x10>; 498 interrupt-parent = <&gpio6>; 499 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&int_codec>; 502 }; 503}; 504 505&i2c3 { 506 status = "okay"; 507 508 clock-frequency = <400000>; 509 i2c-scl-falling-time-ns = <50>; 510 i2c-scl-rising-time-ns = <300>; 511}; 512 513&i2c4 { 514 status = "okay"; 515 516 clock-frequency = <400000>; 517 i2c-scl-falling-time-ns = <50>; /* 11ns measured */ 518 i2c-scl-rising-time-ns = <300>; /* 225ns measured */ 519 520 headsetcodec: ts3a227e@3b { 521 compatible = "ti,ts3a227e"; 522 reg = <0x3b>; 523 interrupt-parent = <&gpio0>; 524 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&ts3a227e_int_l>; 527 ti,micbias = <7>; /* MICBIAS = 2.8V */ 528 }; 529}; 530 531&i2c5 { 532 status = "okay"; 533 534 clock-frequency = <100000>; 535 i2c-scl-falling-time-ns = <300>; 536 i2c-scl-rising-time-ns = <1000>; 537}; 538 539&i2s { 540 status = "okay"; 541 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; 542 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; 543}; 544 545&wdt { 546 status = "okay"; 547}; 548 549&pwm0 { 550 status = "okay"; 551}; 552 553&pwm1 { 554 status = "okay"; 555}; 556 557&uart0 { 558 status = "okay"; 559 560 /* Pins don't include flow control by default; add that in */ 561 pinctrl-names = "default"; 562 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 563 /* We need to go faster than 24MHz, so adjust clock parents / rates */ 564 assigned-clocks = <&cru SCLK_UART0>; 565 assigned-clock-rates = <48000000>; 566}; 567 568&uart1 { 569 status = "okay"; 570}; 571 572&uart2 { 573 status = "okay"; 574 u-boot,dm-pre-reloc; 575 reg-shift = <2>; 576}; 577 578&vopb { 579 status = "okay"; 580}; 581 582&vopb_mmu { 583 status = "okay"; 584}; 585 586&vopl { 587 status = "okay"; 588}; 589 590&vopl_mmu { 591 status = "okay"; 592}; 593 594&edp { 595 status = "okay"; 596 rockchip,panel = <&panel>; 597}; 598 599&hdmi { 600 status = "okay"; 601}; 602 603&hdmi_audio { 604 status = "okay"; 605}; 606 607&gpu { 608 status = "okay"; 609}; 610 611&tsadc { 612 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 613 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 614 status = "okay"; 615}; 616 617&pinctrl { 618 u-boot,dm-pre-reloc; 619 pinctrl-names = "default", "sleep"; 620 pinctrl-0 = < 621 /* Common for sleep and wake, but no owners */ 622 &ddr0_retention 623 &ddrio_pwroff 624 &global_pwroff 625 626 /* Wake only */ 627 &bt_dev_wake_awake 628 >; 629 pinctrl-1 = < 630 /* Common for sleep and wake, but no owners */ 631 &ddr0_retention 632 &ddrio_pwroff 633 &global_pwroff 634 635 /* Sleep only */ 636 &bt_dev_wake_sleep 637 >; 638 639 /* Add this for sdmmc pins to SD card */ 640 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 641 drive-strength = <8>; 642 }; 643 644 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 645 bias-pull-up; 646 drive-strength = <8>; 647 }; 648 649 pcfg_output_high: pcfg-output-high { 650 output-high; 651 }; 652 653 pcfg_output_low: pcfg-output-low { 654 output-low; 655 }; 656 657 backlight { 658 bl_en: bl-en { 659 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; 660 }; 661 }; 662 663 buttons { 664 pwr_key_h: pwr-key-h { 665 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; 666 }; 667 }; 668 669 codec { 670 hp_det: hp-det { 671 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; 672 }; 673 int_codec: int-codec { 674 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>; 675 }; 676 mic_det: mic-det { 677 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; 678 }; 679 }; 680 681 emmc { 682 emmc_reset: emmc-reset { 683 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; 684 }; 685 686 /* 687 * We run eMMC at max speed; bump up drive strength. 688 * We also have external pulls, so disable the internal ones. 689 */ 690 emmc_clk: emmc-clk { 691 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 692 }; 693 694 emmc_cmd: emmc-cmd { 695 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 696 }; 697 698 emmc_bus8: emmc-bus8 { 699 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 700 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 701 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 702 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 703 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 704 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 705 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 706 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 707 }; 708 }; 709 710 headset { 711 ts3a227e_int_l: ts3a227e-int-l { 712 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 713 }; 714 }; 715 716 pmic { 717 pmic_int_l: pmic-int-l { 718 /* 719 * Causes jerry to hang when probing bus 0 720 * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; 721 */ 722 }; 723 }; 724 725 reboot { 726 ap_warm_reset_h: ap-warm-reset-h { 727 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; 728 }; 729 }; 730 731 sdio0 { 732 wifi_enable_h: wifienable-h { 733 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; 734 }; 735 736 /* NOTE: mislabelled on schematic; should be bt_enable_h */ 737 bt_enable_l: bt-enable-l { 738 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; 739 }; 740 741 /* 742 * We run sdio0 at max speed; bump up drive strength. 743 * We also have external pulls, so disable the internal ones. 744 */ 745 sdio0_bus4: sdio0-bus4 { 746 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 747 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 748 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 749 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 750 }; 751 752 sdio0_cmd: sdio0-cmd { 753 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 754 }; 755 756 sdio0_clk: sdio0-clk { 757 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 758 }; 759 760 /* 761 * These pins are only present on very new veyron boards; on 762 * older boards bt_dev_wake is simply always high. Note that 763 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt 764 * to map this pin everywhere 765 */ 766 bt_dev_wake_sleep: bt-dev-wake-sleep { 767 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>; 768 }; 769 770 bt_dev_wake_awake: bt-dev-wake-awake { 771 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>; 772 }; 773 }; 774 775 sdmmc { 776 /* 777 * We run sdmmc at max speed; bump up drive strength. 778 * We also have external pulls, so disable the internal ones. 779 */ 780 sdmmc_bus4: sdmmc-bus4 { 781 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 782 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 783 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 784 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 785 }; 786 787 sdmmc_clk: sdmmc-clk { 788 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 789 }; 790 791 sdmmc_cmd: sdmmc-cmd { 792 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 793 }; 794 795 /* 796 * Builtin CD line is hooked to ground to prevent JTAG at boot 797 * (and also to get the voltage rail correct). Make we 798 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't 799 * think there's a card inserted 800 */ 801 sdmmc_cd_disabled: sdmmc-cd-disabled { 802 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; 803 }; 804 805 /* This is where we actually hook up CD */ 806 sdmmc_cd_gpio: sdmmc-cd-gpio { 807 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; 808 }; 809 }; 810 811 tpm { 812 tpm_int_h: tpm-int-h { 813 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; 814 }; 815 }; 816 817 write-protect { 818 fw_wp_ap: fw-wp-ap { 819 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; 820 }; 821 }; 822}; 823 824&usbphy { 825 status = "okay"; 826}; 827 828&usb_host0_ehci { 829 status = "okay"; 830 needs-reset-on-resume; 831}; 832 833&usb_host1 { 834 status = "okay"; 835}; 836 837&usb_otg { 838 dr_mode = "host"; 839 status = "okay"; 840 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; 841 assigned-clock-parents = <&cru SCLK_OTGPHY0>; 842}; 843 844&sdmmc { 845 u-boot,dm-pre-reloc; 846}; 847 848&gpio3 { 849 u-boot,dm-pre-reloc; 850}; 851 852&gpio8 { 853 u-boot,dm-pre-reloc; 854}; 855