1/* 2 * Google Veyron (and derivatives) board device tree source 3 * 4 * Copyright 2014 Google, Inc 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9#include <dt-bindings/clock/rockchip,rk808.h> 10#include <dt-bindings/input/input.h> 11#include "rk3288.dtsi" 12 13/ { 14 memory { 15 reg = <0x0 0x80000000>; 16 }; 17 18 chosen { 19 stdout-path = &uart2; 20 }; 21 22 config { 23 u-boot,dm-pre-reloc; 24 u-boot,boot0 = &spi_flash; 25 }; 26 27 firmware { 28 chromeos { 29 pinctrl-names = "default"; 30 pinctrl-0 = <&fw_wp_ap>; 31 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>; 32 }; 33 }; 34 35 backlight: backlight { 36 compatible = "pwm-backlight"; 37 brightness-levels = < 38 0 1 2 3 4 5 6 7 39 8 9 10 11 12 13 14 15 40 16 17 18 19 20 21 22 23 41 24 25 26 27 28 29 30 31 42 32 33 34 35 36 37 38 39 43 40 41 42 43 44 45 46 47 44 48 49 50 51 52 53 54 55 45 56 57 58 59 60 61 62 63 46 64 65 66 67 68 69 70 71 47 72 73 74 75 76 77 78 79 48 80 81 82 83 84 85 86 87 49 88 89 90 91 92 93 94 95 50 96 97 98 99 100 101 102 103 51 104 105 106 107 108 109 110 111 52 112 113 114 115 116 117 118 119 53 120 121 122 123 124 125 126 127 54 128 129 130 131 132 133 134 135 55 136 137 138 139 140 141 142 143 56 144 145 146 147 148 149 150 151 57 152 153 154 155 156 157 158 159 58 160 161 162 163 164 165 166 167 59 168 169 170 171 172 173 174 175 60 176 177 178 179 180 181 182 183 61 184 185 186 187 188 189 190 191 62 192 193 194 195 196 197 198 199 63 200 201 202 203 204 205 206 207 64 208 209 210 211 212 213 214 215 65 216 217 218 219 220 221 222 223 66 224 225 226 227 228 229 230 231 67 232 233 234 235 236 237 238 239 68 240 241 242 243 244 245 246 247 69 248 249 250 251 252 253 254 255>; 70 default-brightness-level = <128>; 71 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 72 backlight-boot-off; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&bl_en>; 75 pwms = <&pwm0 0 1000000 0>; 76 }; 77 78 panel: panel { 79 compatible ="cnm,n116bgeea2","simple-panel"; 80 status = "okay"; 81 power-supply = <&vcc33_lcd>; 82 backlight = <&backlight>; 83 }; 84 85 gpio_keys: gpio-keys { 86 compatible = "gpio-keys"; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pwr_key_h>; 92 power { 93 label = "Power"; 94 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; 95 linux,code = <KEY_POWER>; 96 debounce-interval = <100>; 97 gpio-key,wakeup; 98 }; 99 }; 100 101 gpio-restart { 102 compatible = "gpio-restart"; 103 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&ap_warm_reset_h>; 106 priority = /bits/ 8 <200>; 107 }; 108 109 emmc_pwrseq: emmc-pwrseq { 110 compatible = "mmc-pwrseq-emmc"; 111 pinctrl-0 = <&emmc_reset>; 112 pinctrl-names = "default"; 113 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; 114 }; 115 116 sound { 117 compatible = "rockchip,rockchip-audio-max98090"; 118 rockchip,model = "ROCKCHIP-I2S"; 119 rockchip,i2s-controller = <&i2s>; 120 rockchip,audio-codec = <&max98090>; 121 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; 122 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 123 rockchip,headset-codec = <&headsetcodec>; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&mic_det>, <&hp_det>; 126 }; 127 128 vdd_logic: pwm-regulator { 129 compatible = "pwm-regulator"; 130 pwms = <&pwm1 0 2000 0>; 131 132 voltage-table = <1350000 0>, 133 <1300000 10>, 134 <1250000 20>, 135 <1200000 31>, 136 <1150000 41>, 137 <1100000 52>, 138 <1050000 62>, 139 <1000000 72>, 140 < 950000 83>; 141 142 regulator-min-microvolt = <950000>; 143 regulator-max-microvolt = <1350000>; 144 regulator-name = "vdd_logic"; 145 regulator-ramp-delay = <4000>; 146 }; 147 148 vcc33_sys: vcc33-sys { 149 compatible = "regulator-fixed"; 150 regulator-name = "vcc33_sys"; 151 regulator-always-on; 152 regulator-boot-on; 153 regulator-min-microvolt = <3300000>; 154 regulator-max-microvolt = <3300000>; 155 vin-supply = <&vccsys>; 156 }; 157 158 vcc_5v: vcc-5v { 159 compatible = "regulator-fixed"; 160 regulator-name = "vcc_5v"; 161 regulator-always-on; 162 regulator-boot-on; 163 regulator-min-microvolt = <5000000>; 164 regulator-max-microvolt = <5000000>; 165 }; 166 167 vcc50_hdmi: vcc50-hdmi { 168 compatible = "regulator-fixed"; 169 regulator-name = "vcc50_hdmi"; 170 regulator-always-on; 171 regulator-boot-on; 172 vin-supply = <&vcc_5v>; 173 }; 174 175 bt_regulator: bt-regulator { 176 /* 177 * On the module itself this is one of these (depending 178 * on the actual card pouplated): 179 * - BT_I2S_WS_BT_RFDISABLE_L 180 * - No connect 181 */ 182 183 compatible = "regulator-fixed"; 184 enable-active-high; 185 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&bt_enable_l>; 188 regulator-name = "bt_regulator"; 189 }; 190 191 wifi_regulator: wifi-regulator { 192 /* 193 * On the module itself this is one of these (depending 194 * on the actual card populated): 195 * - SDIO_RESET_L_WL_REG_ON 196 * - PDN (power down when low) 197 */ 198 199 compatible = "regulator-fixed"; 200 enable-active-high; 201 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&wifi_enable_h>; 204 regulator-name = "wifi_regulator"; 205 206 /* Faux input supply. See bt_regulator description. */ 207 vin-supply = <&bt_regulator>; 208 }; 209 210 io-domains { 211 compatible = "rockchip,rk3288-io-voltage-domain"; 212 rockchip,grf = <&grf>; 213 214 audio-supply = <&vcc18_codec>; 215 bb-supply = <&vcc33_io>; 216 dvp-supply = <&vcc_18>; 217 flash0-supply = <&vcc18_flashio>; 218 gpio1830-supply = <&vcc33_io>; 219 gpio30-supply = <&vcc33_io>; 220 lcdc-supply = <&vcc33_lcd>; 221 sdcard-supply = <&vccio_sd>; 222 wifi-supply = <&vcc18_wl>; 223 }; 224}; 225 226&cpu0 { 227 cpu0-supply = <&vdd_cpu>; 228}; 229 230&dmc { 231 logic-supply = <&vdd_logic>; 232 rockchip,odt-disable-freq = <333000000>; 233 rockchip,dll-disable-freq = <333000000>; 234 rockchip,sr-enable-freq = <333000000>; 235 rockchip,pd-enable-freq = <666000000>; 236 rockchip,auto-self-refresh-cnt = <0>; 237 rockchip,auto-power-down-cnt = <64>; 238 rockchip,ddr-speed-bin = <21>; 239 rockchip,trcd = <10>; 240 rockchip,trp = <10>; 241 operating-points = < 242 /* KHz uV */ 243 200000 1050000 244 333000 1100000 245 533000 1150000 246 666000 1200000 247 >; 248 rockchip,num-channels = <2>; 249 rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa 250 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 251 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 252 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 253 0x5 0x0>; 254 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 255 0xa60 0x40 0x10 0x0>; 256 rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>; 257 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; 258}; 259 260&efuse { 261 status = "okay"; 262}; 263 264&emmc { 265 broken-cd; 266 bus-width = <8>; 267 cap-mmc-highspeed; 268 mmc-hs200-1_8v; 269 mmc-pwrseq = <&emmc_pwrseq>; 270 disable-wp; 271 non-removable; 272 num-slots = <1>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>; 275 status = "okay"; 276}; 277 278&sdio0 { 279 broken-cd; 280 bus-width = <4>; 281 cap-sd-highspeed; 282 sd-uhs-sdr12; 283 sd-uhs-sdr25; 284 sd-uhs-sdr50; 285 sd-uhs-sdr104; 286 cap-sdio-irq; 287 card-external-vcc-supply = <&wifi_regulator>; 288 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, 289 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>; 290 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock"; 291 keep-power-in-suspend; 292 non-removable; 293 num-slots = <1>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; 296 status = "okay"; 297 vmmc-supply = <&vcc33_sys>; 298 vqmmc-supply = <&vcc18_wl>; 299}; 300 301&sdmmc { 302 bus-width = <4>; 303 cap-mmc-highspeed; 304 cap-sd-highspeed; 305 sd-uhs-sdr12; 306 sd-uhs-sdr25; 307 sd-uhs-sdr50; 308 sd-uhs-sdr104; 309 card-detect-delay = <200>; 310 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; 311 num-slots = <1>; 312 status = "okay"; 313 vmmc-supply = <&vcc33_sd>; 314 vqmmc-supply = <&vccio_sd>; 315}; 316 317&spi2 { 318 status = "okay"; 319 u-boot,dm-pre-reloc; 320 321 spi_flash: spiflash@0 { 322 u-boot,dm-pre-reloc; 323 compatible = "spidev", "spi-flash"; 324 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ 325 reg = <0>; 326 }; 327}; 328 329&i2c0 { 330 status = "okay"; 331 332 clock-frequency = <400000>; 333 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ 334 i2c-scl-rising-time-ns = <100>; /* 45ns measured */ 335 u-boot,dm-pre-reloc; 336 337 rk808: pmic@1b { 338 compatible = "rockchip,rk808"; 339 clock-output-names = "xin32k", "wifibt_32kin"; 340 interrupt-parent = <&gpio0>; 341 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pmic_int_l>; 344 reg = <0x1b>; 345 rockchip,system-power-controller; 346 wakeup-source; 347 #clock-cells = <1>; 348 u-boot,dm-pre-reloc; 349 350 vcc1-supply = <&vcc33_sys>; 351 vcc2-supply = <&vcc33_sys>; 352 vcc3-supply = <&vcc33_sys>; 353 vcc4-supply = <&vcc33_sys>; 354 vcc6-supply = <&vcc_5v>; 355 vcc7-supply = <&vcc33_sys>; 356 vcc8-supply = <&vcc33_sys>; 357 vcc9-supply = <&vcc_5v>; 358 vcc10-supply = <&vcc33_sys>; 359 vcc11-supply = <&vcc_5v>; 360 vcc12-supply = <&vcc_18>; 361 362 vddio-supply = <&vcc33_io>; 363 364 regulators { 365 vdd_cpu: DCDC_REG1 { 366 regulator-always-on; 367 regulator-boot-on; 368 regulator-min-microvolt = <750000>; 369 regulator-max-microvolt = <1450000>; 370 regulator-name = "vdd_arm"; 371 regulator-ramp-delay = <6001>; 372 regulator-suspend-mem-disabled; 373 }; 374 375 vdd_gpu: DCDC_REG2 { 376 regulator-always-on; 377 regulator-boot-on; 378 regulator-min-microvolt = <800000>; 379 regulator-max-microvolt = <1250000>; 380 regulator-name = "vdd_gpu"; 381 regulator-ramp-delay = <6001>; 382 regulator-suspend-mem-disabled; 383 }; 384 385 vcc135_ddr: DCDC_REG3 { 386 regulator-always-on; 387 regulator-boot-on; 388 regulator-name = "vcc135_ddr"; 389 regulator-suspend-mem-enabled; 390 }; 391 392 /* 393 * vcc_18 has several aliases. (vcc18_flashio and 394 * vcc18_wl). We'll add those aliases here just to 395 * make it easier to follow the schematic. The signals 396 * are actually hooked together and only separated for 397 * power measurement purposes). 398 */ 399 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { 400 regulator-always-on; 401 regulator-boot-on; 402 regulator-min-microvolt = <1800000>; 403 regulator-max-microvolt = <1800000>; 404 regulator-name = "vcc_18"; 405 regulator-suspend-mem-microvolt = <1800000>; 406 }; 407 408 /* 409 * Note that both vcc33_io and vcc33_pmuio are always 410 * powered together. To simplify the logic in the dts 411 * we just refer to vcc33_io every time something is 412 * powered from vcc33_pmuio. In fact, on later boards 413 * (such as danger) they're the same net. 414 */ 415 vcc33_io: LDO_REG1 { 416 regulator-always-on; 417 regulator-boot-on; 418 regulator-min-microvolt = <3300000>; 419 regulator-max-microvolt = <3300000>; 420 regulator-name = "vcc33_io"; 421 regulator-suspend-mem-microvolt = <3300000>; 422 }; 423 424 vdd_10: LDO_REG3 { 425 regulator-always-on; 426 regulator-boot-on; 427 regulator-min-microvolt = <1000000>; 428 regulator-max-microvolt = <1000000>; 429 regulator-name = "vdd_10"; 430 regulator-suspend-mem-microvolt = <1000000>; 431 }; 432 433 vccio_sd: LDO_REG4 { 434 regulator-min-microvolt = <1800000>; 435 regulator-max-microvolt = <3300000>; 436 regulator-name = "vccio_sd"; 437 regulator-suspend-mem-disabled; 438 }; 439 440 vcc33_sd: LDO_REG5 { 441 regulator-min-microvolt = <3300000>; 442 regulator-max-microvolt = <3300000>; 443 regulator-name = "vcc33_sd"; 444 regulator-suspend-mem-disabled; 445 }; 446 447 vcc18_codec: LDO_REG6 { 448 regulator-always-on; 449 regulator-boot-on; 450 regulator-min-microvolt = <1800000>; 451 regulator-max-microvolt = <1800000>; 452 regulator-name = "vcc18_codec"; 453 regulator-suspend-mem-disabled; 454 }; 455 456 vdd10_lcd_pwren_h: LDO_REG7 { 457 regulator-always-on; 458 regulator-boot-on; 459 regulator-min-microvolt = <2500000>; 460 regulator-max-microvolt = <2500000>; 461 regulator-name = "vdd10_lcd_pwren_h"; 462 regulator-suspend-mem-disabled; 463 }; 464 465 vcc33_lcd: SWITCH_REG1 { 466 regulator-always-on; 467 regulator-boot-on; 468 regulator-name = "vcc33_lcd"; 469 regulator-suspend-mem-disabled; 470 }; 471 }; 472 }; 473}; 474 475&i2c1 { 476 status = "okay"; 477 478 clock-frequency = <400000>; 479 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ 480 i2c-scl-rising-time-ns = <100>; /* 40ns measured */ 481 482 tpm: tpm@20 { 483 compatible = "infineon,slb9645tt"; 484 reg = <0x20>; 485 powered-while-suspended; 486 }; 487}; 488 489&i2c2 { 490 status = "okay"; 491 492 /* 100kHz since 4.7k resistors don't rise fast enough */ 493 clock-frequency = <100000>; 494 i2c-scl-falling-time-ns = <50>; /* 10ns measured */ 495 i2c-scl-rising-time-ns = <800>; /* 600ns measured */ 496 497 max98090: max98090@10 { 498 compatible = "maxim,max98090"; 499 reg = <0x10>; 500 interrupt-parent = <&gpio6>; 501 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&int_codec>; 504 }; 505}; 506 507&i2c3 { 508 status = "okay"; 509 510 clock-frequency = <400000>; 511 i2c-scl-falling-time-ns = <50>; 512 i2c-scl-rising-time-ns = <300>; 513}; 514 515&i2c4 { 516 status = "okay"; 517 518 clock-frequency = <400000>; 519 i2c-scl-falling-time-ns = <50>; /* 11ns measured */ 520 i2c-scl-rising-time-ns = <300>; /* 225ns measured */ 521 522 headsetcodec: ts3a227e@3b { 523 compatible = "ti,ts3a227e"; 524 reg = <0x3b>; 525 interrupt-parent = <&gpio0>; 526 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&ts3a227e_int_l>; 529 ti,micbias = <7>; /* MICBIAS = 2.8V */ 530 }; 531}; 532 533&i2c5 { 534 status = "okay"; 535 536 clock-frequency = <100000>; 537 i2c-scl-falling-time-ns = <300>; 538 i2c-scl-rising-time-ns = <1000>; 539}; 540 541&i2s { 542 status = "okay"; 543 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; 544 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; 545}; 546 547&wdt { 548 status = "okay"; 549}; 550 551&pwm0 { 552 status = "okay"; 553}; 554 555&pwm1 { 556 status = "okay"; 557}; 558 559&uart0 { 560 status = "okay"; 561 562 /* Pins don't include flow control by default; add that in */ 563 pinctrl-names = "default"; 564 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 565 /* We need to go faster than 24MHz, so adjust clock parents / rates */ 566 assigned-clocks = <&cru SCLK_UART0>; 567 assigned-clock-rates = <48000000>; 568}; 569 570&uart1 { 571 status = "okay"; 572}; 573 574&uart2 { 575 status = "okay"; 576 u-boot,dm-pre-reloc; 577 reg-shift = <2>; 578}; 579 580&vopb { 581 status = "okay"; 582}; 583 584&vopb_mmu { 585 status = "okay"; 586}; 587 588&vopl { 589 status = "okay"; 590}; 591 592&vopl_mmu { 593 status = "okay"; 594}; 595 596&edp { 597 status = "okay"; 598 rockchip,panel = <&panel>; 599}; 600 601&hdmi { 602 status = "okay"; 603}; 604 605&hdmi_audio { 606 status = "okay"; 607}; 608 609&gpu { 610 status = "okay"; 611}; 612 613&tsadc { 614 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 615 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 616 status = "okay"; 617}; 618 619&pinctrl { 620 u-boot,dm-pre-reloc; 621 pinctrl-names = "default", "sleep"; 622 pinctrl-0 = < 623 /* Common for sleep and wake, but no owners */ 624 &ddr0_retention 625 &ddrio_pwroff 626 &global_pwroff 627 628 /* Wake only */ 629 &bt_dev_wake_awake 630 >; 631 pinctrl-1 = < 632 /* Common for sleep and wake, but no owners */ 633 &ddr0_retention 634 &ddrio_pwroff 635 &global_pwroff 636 637 /* Sleep only */ 638 &bt_dev_wake_sleep 639 >; 640 641 /* Add this for sdmmc pins to SD card */ 642 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 643 drive-strength = <8>; 644 }; 645 646 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 647 bias-pull-up; 648 drive-strength = <8>; 649 }; 650 651 pcfg_output_high: pcfg-output-high { 652 output-high; 653 }; 654 655 pcfg_output_low: pcfg-output-low { 656 output-low; 657 }; 658 659 backlight { 660 bl_en: bl-en { 661 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; 662 }; 663 }; 664 665 buttons { 666 pwr_key_h: pwr-key-h { 667 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; 668 }; 669 }; 670 671 codec { 672 hp_det: hp-det { 673 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; 674 }; 675 int_codec: int-codec { 676 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>; 677 }; 678 mic_det: mic-det { 679 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; 680 }; 681 }; 682 683 emmc { 684 emmc_reset: emmc-reset { 685 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; 686 }; 687 688 /* 689 * We run eMMC at max speed; bump up drive strength. 690 * We also have external pulls, so disable the internal ones. 691 */ 692 emmc_clk: emmc-clk { 693 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 694 }; 695 696 emmc_cmd: emmc-cmd { 697 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 698 }; 699 700 emmc_bus8: emmc-bus8 { 701 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 702 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 703 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 704 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 705 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 706 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 707 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 708 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 709 }; 710 }; 711 712 headset { 713 ts3a227e_int_l: ts3a227e-int-l { 714 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 715 }; 716 }; 717 718 pmic { 719 pmic_int_l: pmic-int-l { 720 /* 721 * Causes jerry to hang when probing bus 0 722 * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; 723 */ 724 }; 725 }; 726 727 reboot { 728 ap_warm_reset_h: ap-warm-reset-h { 729 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; 730 }; 731 }; 732 733 sdio0 { 734 wifi_enable_h: wifienable-h { 735 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; 736 }; 737 738 /* NOTE: mislabelled on schematic; should be bt_enable_h */ 739 bt_enable_l: bt-enable-l { 740 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; 741 }; 742 743 /* 744 * We run sdio0 at max speed; bump up drive strength. 745 * We also have external pulls, so disable the internal ones. 746 */ 747 sdio0_bus4: sdio0-bus4 { 748 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 749 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 750 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 751 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 752 }; 753 754 sdio0_cmd: sdio0-cmd { 755 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 756 }; 757 758 sdio0_clk: sdio0-clk { 759 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 760 }; 761 762 /* 763 * These pins are only present on very new veyron boards; on 764 * older boards bt_dev_wake is simply always high. Note that 765 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt 766 * to map this pin everywhere 767 */ 768 bt_dev_wake_sleep: bt-dev-wake-sleep { 769 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>; 770 }; 771 772 bt_dev_wake_awake: bt-dev-wake-awake { 773 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>; 774 }; 775 }; 776 777 sdmmc { 778 /* 779 * We run sdmmc at max speed; bump up drive strength. 780 * We also have external pulls, so disable the internal ones. 781 */ 782 sdmmc_bus4: sdmmc-bus4 { 783 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 784 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 785 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 786 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 787 }; 788 789 sdmmc_clk: sdmmc-clk { 790 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 791 }; 792 793 sdmmc_cmd: sdmmc-cmd { 794 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 795 }; 796 797 /* 798 * Builtin CD line is hooked to ground to prevent JTAG at boot 799 * (and also to get the voltage rail correct). Make we 800 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't 801 * think there's a card inserted 802 */ 803 sdmmc_cd_disabled: sdmmc-cd-disabled { 804 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; 805 }; 806 807 /* This is where we actually hook up CD */ 808 sdmmc_cd_gpio: sdmmc-cd-gpio { 809 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; 810 }; 811 }; 812 813 tpm { 814 tpm_int_h: tpm-int-h { 815 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; 816 }; 817 }; 818 819 write-protect { 820 fw_wp_ap: fw-wp-ap { 821 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; 822 }; 823 }; 824}; 825 826&usbphy { 827 status = "okay"; 828}; 829 830&usb_host0_ehci { 831 status = "okay"; 832 needs-reset-on-resume; 833}; 834 835&usb_host1 { 836 status = "okay"; 837}; 838 839&usb_otg { 840 dr_mode = "host"; 841 status = "okay"; 842 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; 843 assigned-clock-parents = <&cru SCLK_OTGPHY0>; 844}; 845 846&sdmmc { 847 u-boot,dm-pre-reloc; 848}; 849 850&gpio3 { 851 u-boot,dm-pre-reloc; 852}; 853 854&gpio8 { 855 u-boot,dm-pre-reloc; 856}; 857