1/* 2 * Device tree file for Phytec phyCORE-RK3288 SoM 3 * Copyright (C) 2017 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <w.egorov@phytec.de> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/net/ti-dp83867.h> 46#include "rk3288.dtsi" 47 48/ { 49 model = "Phytec RK3288 phyCORE"; 50 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; 51 52 /* 53 * Set the minimum memory size here and 54 * let the bootloader set the real size. 55 */ 56 memory { 57 device_type = "memory"; 58 reg = <0 0x8000000>; 59 }; 60 61 aliases { 62 rtc0 = &i2c_rtc; 63 rtc1 = &rk818; 64 }; 65 66 ext_gmac: external-gmac-clock { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <125000000>; 70 clock-output-names = "ext_gmac"; 71 }; 72 73 io_domains: io_domains { 74 compatible = "rockchip,rk3288-io-voltage-domain"; 75 76 status = "okay"; 77 sdcard-supply = <&vdd_io_sd>; 78 flash0-supply = <&vdd_emmc_io>; 79 flash1-supply = <&vdd_misc_1v8>; 80 gpio1830-supply = <&vdd_3v3_io>; 81 gpio30-supply = <&vdd_3v3_io>; 82 bb-supply = <&vdd_3v3_io>; 83 dvp-supply = <&vdd_3v3_io>; 84 lcdc-supply = <&vdd_3v3_io>; 85 wifi-supply = <&vdd_3v3_io>; 86 audio-supply = <&vdd_3v3_io>; 87 }; 88 89 leds: user-leds { 90 compatible = "gpio-leds"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&user_led>; 93 94 user { 95 label = "green_led"; 96 gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 97 linux,default-trigger = "heartbeat"; 98 default-state = "keep"; 99 }; 100 }; 101 102 vdd_emmc_io: vdd-emmc-io { 103 compatible = "regulator-fixed"; 104 regulator-name = "vdd_emmc_io"; 105 regulator-min-microvolt = <1800000>; 106 regulator-max-microvolt = <1800000>; 107 vin-supply = <&vdd_3v3_io>; 108 }; 109 110 vdd_in_otg_out: vdd-in-otg-out { 111 compatible = "regulator-fixed"; 112 regulator-name = "vdd_in_otg_out"; 113 regulator-always-on; 114 regulator-boot-on; 115 regulator-min-microvolt = <5000000>; 116 regulator-max-microvolt = <5000000>; 117 }; 118 119 vdd_misc_1v8: vdd-misc-1v8 { 120 compatible = "regulator-fixed"; 121 regulator-name = "vdd_misc_1v8"; 122 regulator-always-on; 123 regulator-boot-on; 124 regulator-min-microvolt = <1800000>; 125 regulator-max-microvolt = <1800000>; 126 }; 127}; 128 129&cpu0 { 130 cpu0-supply = <&vdd_cpu>; 131 operating-points = < 132 /* KHz uV */ 133 1800000 1400000 134 1608000 1350000 135 1512000 1300000 136 1416000 1200000 137 1200000 1100000 138 1008000 1050000 139 816000 1000000 140 696000 950000 141 600000 900000 142 408000 900000 143 312000 900000 144 216000 900000 145 126000 900000 146 >; 147}; 148 149&emmc { 150 status = "okay"; 151 u-boot,dm-pre-reloc; 152 153 bus-width = <8>; 154 cap-mmc-highspeed; 155 disable-wp; 156 non-removable; 157 num-slots = <1>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; 160 vmmc-supply = <&vdd_3v3_io>; 161 vqmmc-supply = <&vdd_emmc_io>; 162}; 163 164&gmac { 165 assigned-clocks = <&cru SCLK_MAC>; 166 assigned-clock-parents = <&ext_gmac>; 167 clock_in_out = "input"; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; 170 phy-handle = <&phy0>; 171 phy-supply = <&vdd_eth_2v5>; 172 phy-mode = "rgmii-id"; 173 snps,reset-active-low; 174 snps,reset-delays-us = <0 10000 1000000>; 175 snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; 176 tx_delay = <0x0>; 177 rx_delay = <0x0>; 178 179 mdio0 { 180 compatible = "snps,dwmac-mdio"; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 phy0: ethernet-phy@0 { 185 compatible = "ethernet-phy-ieee802.3-c22"; 186 reg = <0>; 187 interrupt-parent = <&gpio4>; 188 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 189 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 190 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 191 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 192 enet-phy-lane-no-swap; 193 }; 194 }; 195}; 196 197&hdmi { 198 ddc-i2c-bus = <&i2c5>; 199}; 200 201&i2c0 { 202 status = "okay"; 203 u-boot,dm-pre-reloc; 204 205 clock-frequency = <400000>; 206 207 rk818: pmic@1c { 208 status = "okay"; 209 compatible = "rockchip,rk818"; 210 reg = <0x1c>; 211 interrupt-parent = <&gpio0>; 212 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pmic_int>; 215 rockchip,system-power-controller; 216 wakeup-source; 217 #clock-cells = <1>; 218 u-boot,dm-pre-reloc; 219 220 vcc1-supply = <&vdd_sys>; 221 vcc2-supply = <&vdd_sys>; 222 vcc3-supply = <&vdd_sys>; 223 vcc4-supply = <&vdd_sys>; 224 boost-supply = <&vdd_in_otg_out>; 225 vcc6-supply = <&vdd_sys>; 226 vcc7-supply = <&vdd_misc_1v8>; 227 vcc8-supply = <&vdd_misc_1v8>; 228 vcc9-supply = <&vdd_3v3_io>; 229 vddio-supply = <&vdd_3v3_io>; 230 231 regulators { 232 u-boot,dm-pre-reloc; 233 vdd_log: DCDC_REG1 { 234 regulator-name = "vdd_log"; 235 regulator-always-on; 236 regulator-boot-on; 237 regulator-min-microvolt = <1100000>; 238 regulator-max-microvolt = <1100000>; 239 regulator-state-mem { 240 regulator-off-in-suspend; 241 }; 242 }; 243 244 vdd_gpu: DCDC_REG2 { 245 regulator-name = "vdd_gpu"; 246 regulator-always-on; 247 regulator-boot-on; 248 regulator-min-microvolt = <800000>; 249 regulator-max-microvolt = <1250000>; 250 regulator-state-mem { 251 regulator-on-in-suspend; 252 regulator-suspend-microvolt = <1000000>; 253 }; 254 }; 255 256 vcc_ddr: DCDC_REG3 { 257 regulator-name = "vcc_ddr"; 258 regulator-always-on; 259 regulator-boot-on; 260 regulator-state-mem { 261 regulator-on-in-suspend; 262 }; 263 }; 264 265 vdd_3v3_io: DCDC_REG4 { 266 regulator-name = "vdd_3v3_io"; 267 regulator-always-on; 268 regulator-boot-on; 269 regulator-min-microvolt = <3300000>; 270 regulator-max-microvolt = <3300000>; 271 regulator-state-mem { 272 regulator-on-in-suspend; 273 regulator-suspend-microvolt = <3300000>; 274 }; 275 }; 276 277 vdd_sys: DCDC_BOOST { 278 regulator-name = "vdd_sys"; 279 regulator-always-on; 280 regulator-boot-on; 281 regulator-min-microvolt = <5000000>; 282 regulator-max-microvolt = <5000000>; 283 regulator-state-mem { 284 regulator-on-in-suspend; 285 regulator-suspend-microvolt = <5000000>; 286 }; 287 }; 288 289 /* vcc9 */ 290 vdd_sd: SWITCH_REG { 291 regulator-name = "vdd_sd"; 292 regulator-always-on; 293 regulator-boot-on; 294 regulator-state-mem { 295 regulator-off-in-suspend; 296 }; 297 }; 298 299 /* vcc6 */ 300 vdd_eth_2v5: LDO_REG2 { 301 regulator-name = "vdd_eth_2v5"; 302 regulator-always-on; 303 regulator-boot-on; 304 regulator-min-microvolt = <2500000>; 305 regulator-max-microvolt = <2500000>; 306 regulator-state-mem { 307 regulator-on-in-suspend; 308 regulator-suspend-microvolt = <2500000>; 309 }; 310 }; 311 312 /* vcc7 */ 313 vdd_1v0: LDO_REG3 { 314 regulator-name = "vdd_1v0"; 315 regulator-always-on; 316 regulator-boot-on; 317 regulator-min-microvolt = <1000000>; 318 regulator-max-microvolt = <1000000>; 319 regulator-state-mem { 320 regulator-on-in-suspend; 321 regulator-suspend-microvolt = <1000000>; 322 }; 323 }; 324 325 /* vcc8 */ 326 vdd_1v8_lcd_ldo: LDO_REG4 { 327 regulator-name = "vdd_1v8_lcd_ldo"; 328 regulator-always-on; 329 regulator-boot-on; 330 regulator-min-microvolt = <1800000>; 331 regulator-max-microvolt = <1800000>; 332 regulator-state-mem { 333 regulator-on-in-suspend; 334 regulator-suspend-microvolt = <1800000>; 335 }; 336 }; 337 338 /* vcc8 */ 339 vdd_1v0_lcd: LDO_REG6 { 340 regulator-name = "vdd_1v0_lcd"; 341 regulator-always-on; 342 regulator-boot-on; 343 regulator-min-microvolt = <1000000>; 344 regulator-max-microvolt = <1000000>; 345 regulator-state-mem { 346 regulator-on-in-suspend; 347 regulator-suspend-microvolt = <1000000>; 348 }; 349 }; 350 351 /* vcc7 */ 352 vdd_1v8_ldo: LDO_REG7 { 353 regulator-name = "vdd_1v8_ldo"; 354 regulator-always-on; 355 regulator-boot-on; 356 regulator-min-microvolt = <1800000>; 357 regulator-max-microvolt = <1800000>; 358 regulator-state-mem { 359 regulator-off-in-suspend; 360 regulator-suspend-microvolt = <1800000>; 361 }; 362 }; 363 364 /* vcc9 */ 365 vdd_io_sd: LDO_REG9 { 366 regulator-name = "vdd_io_sd"; 367 regulator-always-on; 368 regulator-boot-on; 369 regulator-min-microvolt = <3300000>; 370 regulator-max-microvolt = <3300000>; 371 regulator-state-mem { 372 regulator-on-in-suspend; 373 regulator-suspend-microvolt = <3300000>; 374 }; 375 }; 376 }; 377 }; 378 379 /* M24C32-D */ 380 i2c_eeprom: eeprom@50 { 381 compatible = "atmel,24c32"; 382 reg = <0x50>; 383 pagesize = <32>; 384 }; 385 386 vdd_cpu: regulator@60 { 387 compatible = "fcs,fan53555"; 388 reg = <0x60>; 389 fcs,suspend-voltage-selector = <1>; 390 regulator-always-on; 391 regulator-boot-on; 392 regulator-enable-ramp-delay = <300>; 393 regulator-name = "vdd_cpu"; 394 regulator-min-microvolt = <800000>; 395 regulator-max-microvolt = <1430000>; 396 regulator-ramp-delay = <8000>; 397 vin-supply = <&vdd_sys>; 398 }; 399}; 400 401&pinctrl { 402 pcfg_output_high: pcfg-output-high { 403 output-high; 404 }; 405 406 emmc { 407 /* 408 * We run eMMC at max speed; bump up drive strength. 409 * We also have external pulls, so disable the internal ones. 410 */ 411 emmc_clk: emmc-clk { 412 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; 413 }; 414 415 emmc_cmd: emmc-cmd { 416 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; 417 }; 418 419 emmc_bus8: emmc-bus8 { 420 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, 421 <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, 422 <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, 423 <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, 424 <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, 425 <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, 426 <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, 427 <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; 428 }; 429 }; 430 431 gmac { 432 phy_int: phy-int { 433 rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; 434 }; 435 436 phy_rst: phy-rst { 437 rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; 438 }; 439 }; 440 441 leds { 442 user_led: user-led { 443 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; 444 }; 445 }; 446 447 pmic { 448 pmic_int: pmic-int { 449 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; 450 }; 451 452 /* Pin for switching state between sleep and non-sleep state */ 453 pmic_sleep: pmic-sleep { 454 rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; 455 }; 456 }; 457}; 458 459&pwm1 { 460 status = "okay"; 461}; 462 463&saradc { 464 status = "okay"; 465 vref-supply = <&vdd_1v8_ldo>; 466}; 467 468&spi2 { 469 status = "okay"; 470 471 serial_flash: flash@0 { 472 compatible = "micron,n25q128a13", "jedec,spi-nor"; 473 reg = <0x0>; 474 spi-max-frequency = <50000000>; 475 m25p,fast-read; 476 #address-cells = <1>; 477 #size-cells = <1>; 478 status = "okay"; 479 }; 480}; 481 482&tsadc { 483 status = "okay"; 484 rockchip,hw-tshut-mode = <0>; 485 rockchip,hw-tshut-polarity = <0>; 486}; 487 488&vopb { 489 status = "okay"; 490}; 491 492&vopb_mmu { 493 status = "okay"; 494}; 495 496&vopl { 497 status = "okay"; 498}; 499 500&vopl_mmu { 501 status = "okay"; 502}; 503 504&wdt { 505 status = "okay"; 506}; 507