1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3228-cru.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@f00 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a7"; 33 reg = <0xf00>; 34 resets = <&cru SRST_CORE0>; 35 operating-points = < 36 /* KHz uV */ 37 816000 1000000 38 >; 39 #cooling-cells = <2>; /* min followed by max */ 40 clock-latency = <40000>; 41 clocks = <&cru ARMCLK>; 42 }; 43 44 cpu1: cpu@f01 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a7"; 47 reg = <0xf01>; 48 resets = <&cru SRST_CORE1>; 49 }; 50 51 cpu2: cpu@f02 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0xf02>; 55 resets = <&cru SRST_CORE2>; 56 }; 57 58 cpu3: cpu@f03 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf03>; 62 resets = <&cru SRST_CORE3>; 63 }; 64 }; 65 66 amba { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges; 71 72 pdma: pdma@110f0000 { 73 compatible = "arm,pl330", "arm,primecell"; 74 reg = <0x110f0000 0x4000>; 75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 77 #dma-cells = <1>; 78 clocks = <&cru ACLK_DMAC>; 79 clock-names = "apb_pclk"; 80 }; 81 }; 82 83 arm-pmu { 84 compatible = "arm,cortex-a7-pmu"; 85 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 89 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 90 }; 91 92 timer { 93 compatible = "arm,armv7-timer"; 94 arm,cpu-registers-not-fw-configured; 95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 99 clock-frequency = <24000000>; 100 }; 101 102 xin24m: oscillator { 103 compatible = "fixed-clock"; 104 clock-frequency = <24000000>; 105 clock-output-names = "xin24m"; 106 #clock-cells = <0>; 107 }; 108 109 bus_intmem@10080000 { 110 compatible = "mmio-sram"; 111 reg = <0x10080000 0x9000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0 0x10080000 0x9000>; 115 smp-sram@0 { 116 compatible = "rockchip,rk322x-smp-sram"; 117 reg = <0x00 0x10>; 118 }; 119 ddr_sram: ddr-sram@1000 { 120 compatible = "rockchip,rk322x-ddr-sram"; 121 reg = <0x1000 0x8000>; 122 }; 123 }; 124 125 i2s1: i2s1@100b0000 { 126 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 127 reg = <0x100b0000 0x4000>; 128 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 clock-names = "i2s_clk", "i2s_hclk"; 132 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 133 dmas = <&pdma 14>, <&pdma 15>; 134 dma-names = "tx", "rx"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&i2s1_bus>; 137 status = "disabled"; 138 }; 139 140 i2s0: i2s0@100c0000 { 141 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 142 reg = <0x100c0000 0x4000>; 143 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 clock-names = "i2s_clk", "i2s_hclk"; 147 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 148 dmas = <&pdma 11>, <&pdma 12>; 149 dma-names = "tx", "rx"; 150 status = "disabled"; 151 }; 152 153 i2s2: i2s2@100e0000 { 154 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 155 reg = <0x100e0000 0x4000>; 156 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 clock-names = "i2s_clk", "i2s_hclk"; 160 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 161 dmas = <&pdma 0>, <&pdma 1>; 162 dma-names = "tx", "rx"; 163 status = "disabled"; 164 }; 165 166 grf: syscon@11000000 { 167 u-boot,dm-pre-reloc; 168 compatible = "rockchip,rk3228-grf", "syscon"; 169 reg = <0x11000000 0x1000>; 170 }; 171 172 uart0: serial@11010000 { 173 compatible = "snps,dw-apb-uart"; 174 reg = <0x11010000 0x100>; 175 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 176 clock-frequency = <24000000>; 177 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 178 clock-names = "baudclk", "apb_pclk"; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 181 reg-shift = <2>; 182 reg-io-width = <4>; 183 status = "disabled"; 184 }; 185 186 uart1: serial@11020000 { 187 compatible = "snps,dw-apb-uart"; 188 reg = <0x11020000 0x100>; 189 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 190 clock-frequency = <24000000>; 191 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 192 clock-names = "baudclk", "apb_pclk"; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&uart1_xfer>; 195 reg-shift = <2>; 196 reg-io-width = <4>; 197 status = "disabled"; 198 }; 199 200 uart2: serial@11030000 { 201 compatible = "snps,dw-apb-uart"; 202 reg = <0x11030000 0x100>; 203 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 204 clock-frequency = <24000000>; 205 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 206 clock-names = "baudclk", "apb_pclk"; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&uart2_xfer>; 209 reg-shift = <2>; 210 reg-io-width = <4>; 211 status = "disabled"; 212 }; 213 214 i2c0: i2c@11050000 { 215 compatible = "rockchip,rk3228-i2c"; 216 reg = <0x11050000 0x1000>; 217 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 clock-names = "i2c"; 221 clocks = <&cru PCLK_I2C0>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&i2c0_xfer>; 224 status = "disabled"; 225 }; 226 227 i2c1: i2c@11060000 { 228 compatible = "rockchip,rk3228-i2c"; 229 reg = <0x11060000 0x1000>; 230 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 clock-names = "i2c"; 234 clocks = <&cru PCLK_I2C1>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&i2c1_xfer>; 237 status = "disabled"; 238 }; 239 240 i2c2: i2c@11070000 { 241 compatible = "rockchip,rk3228-i2c"; 242 reg = <0x11070000 0x1000>; 243 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 clock-names = "i2c"; 247 clocks = <&cru PCLK_I2C2>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&i2c2_xfer>; 250 status = "disabled"; 251 }; 252 253 i2c3: i2c@11080000 { 254 compatible = "rockchip,rk3228-i2c"; 255 reg = <0x11080000 0x1000>; 256 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clock-names = "i2c"; 260 clocks = <&cru PCLK_I2C3>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&i2c3_xfer>; 263 status = "disabled"; 264 }; 265 266 pwm0: pwm@110b0000 { 267 compatible = "rockchip,rk3288-pwm"; 268 reg = <0x110b0000 0x10>; 269 #pwm-cells = <3>; 270 clocks = <&cru PCLK_PWM>; 271 clock-names = "pwm"; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pwm0_pin>; 274 status = "disabled"; 275 }; 276 277 pwm1: pwm@110b0010 { 278 compatible = "rockchip,rk3288-pwm"; 279 reg = <0x110b0010 0x10>; 280 #pwm-cells = <3>; 281 clocks = <&cru PCLK_PWM>; 282 clock-names = "pwm"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pwm1_pin>; 285 status = "disabled"; 286 }; 287 288 pwm2: pwm@110b0020 { 289 compatible = "rockchip,rk3288-pwm"; 290 reg = <0x110b0020 0x10>; 291 #pwm-cells = <3>; 292 clocks = <&cru PCLK_PWM>; 293 clock-names = "pwm"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pwm2_pin>; 296 status = "disabled"; 297 }; 298 299 pwm3: pwm@110b0030 { 300 compatible = "rockchip,rk3288-pwm"; 301 reg = <0x110b0030 0x10>; 302 #pwm-cells = <2>; 303 clocks = <&cru PCLK_PWM>; 304 clock-names = "pwm"; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pwm3_pin>; 307 status = "disabled"; 308 }; 309 310 timer: timer@110c0000 { 311 compatible = "rockchip,rk3288-timer"; 312 reg = <0x110c0000 0x20>; 313 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&xin24m>, <&cru PCLK_TIMER>; 315 clock-names = "timer", "pclk"; 316 }; 317 318 cru: clock-controller@110e0000 { 319 u-boot,dm-pre-reloc; 320 compatible = "rockchip,rk3228-cru"; 321 reg = <0x110e0000 0x1000>; 322 rockchip,grf = <&grf>; 323 #clock-cells = <1>; 324 #reset-cells = <1>; 325 assigned-clocks = <&cru PLL_GPLL>; 326 assigned-clock-rates = <594000000>; 327 }; 328 329 thermal-zones { 330 cpu_thermal: cpu-thermal { 331 polling-delay-passive = <100>; /* milliseconds */ 332 polling-delay = <5000>; /* milliseconds */ 333 334 thermal-sensors = <&tsadc 0>; 335 336 trips { 337 cpu_alert0: cpu_alert0 { 338 temperature = <70000>; /* millicelsius */ 339 hysteresis = <2000>; /* millicelsius */ 340 type = "passive"; 341 }; 342 cpu_alert1: cpu_alert1 { 343 temperature = <75000>; /* millicelsius */ 344 hysteresis = <2000>; /* millicelsius */ 345 type = "passive"; 346 }; 347 cpu_crit: cpu_crit { 348 temperature = <90000>; /* millicelsius */ 349 hysteresis = <2000>; /* millicelsius */ 350 type = "critical"; 351 }; 352 }; 353 354 cooling-maps { 355 map0 { 356 trip = <&cpu_alert0>; 357 cooling-device = 358 <&cpu0 THERMAL_NO_LIMIT 6>; 359 }; 360 map1 { 361 trip = <&cpu_alert1>; 362 cooling-device = 363 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 364 }; 365 }; 366 }; 367 }; 368 369 tsadc: tsadc@11150000 { 370 compatible = "rockchip,rk3228-tsadc"; 371 reg = <0x11150000 0x100>; 372 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 374 clock-names = "tsadc", "apb_pclk"; 375 resets = <&cru SRST_TSADC>; 376 reset-names = "tsadc-apb"; 377 pinctrl-names = "init", "default", "sleep"; 378 pinctrl-0 = <&otp_gpio>; 379 pinctrl-1 = <&otp_out>; 380 pinctrl-2 = <&otp_gpio>; 381 #thermal-sensor-cells = <0>; 382 rockchip,hw-tshut-temp = <95000>; 383 status = "disabled"; 384 }; 385 386 emmc: dwmmc@30020000 { 387 compatible = "rockchip,rk3288-dw-mshc"; 388 reg = <0x30020000 0x4000>; 389 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 390 clock-frequency = <37500000>; 391 max-frequency = <37500000>; 392 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 393 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 394 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 395 bus-width = <8>; 396 default-sample-phase = <158>; 397 num-slots = <1>; 398 fifo-depth = <0x100>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 401 resets = <&cru SRST_EMMC>; 402 reset-names = "reset"; 403 status = "disabled"; 404 }; 405 406 gmac: ethernet@30200000 { 407 compatible = "rockchip,rk3228-gmac"; 408 reg = <0x30200000 0x10000>; 409 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "macirq"; 411 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 412 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 413 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 414 <&cru PCLK_GMAC>; 415 clock-names = "stmmaceth", "mac_clk_rx", 416 "mac_clk_tx", "clk_mac_ref", 417 "clk_mac_refout", "aclk_mac", 418 "pclk_mac"; 419 resets = <&cru SRST_GMAC>; 420 reset-names = "stmmaceth"; 421 rockchip,grf = <&grf>; 422 status = "disabled"; 423 }; 424 425 gic: interrupt-controller@32010000 { 426 compatible = "arm,gic-400"; 427 interrupt-controller; 428 #interrupt-cells = <3>; 429 #address-cells = <0>; 430 431 reg = <0x32011000 0x1000>, 432 <0x32012000 0x2000>, 433 <0x32014000 0x2000>, 434 <0x32016000 0x2000>; 435 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 436 }; 437 438 pinctrl: pinctrl { 439 compatible = "rockchip,rk3228-pinctrl"; 440 rockchip,grf = <&grf>; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges; 444 445 gpio0: gpio0@11110000 { 446 compatible = "rockchip,gpio-bank"; 447 reg = <0x11110000 0x100>; 448 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru PCLK_GPIO0>; 450 451 gpio-controller; 452 #gpio-cells = <2>; 453 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 458 gpio1: gpio1@11120000 { 459 compatible = "rockchip,gpio-bank"; 460 reg = <0x11120000 0x100>; 461 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cru PCLK_GPIO1>; 463 464 gpio-controller; 465 #gpio-cells = <2>; 466 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 }; 470 471 gpio2: gpio2@11130000 { 472 compatible = "rockchip,gpio-bank"; 473 reg = <0x11130000 0x100>; 474 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&cru PCLK_GPIO2>; 476 477 gpio-controller; 478 #gpio-cells = <2>; 479 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 }; 483 484 gpio3: gpio3@11140000 { 485 compatible = "rockchip,gpio-bank"; 486 reg = <0x11140000 0x100>; 487 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&cru PCLK_GPIO3>; 489 490 gpio-controller; 491 #gpio-cells = <2>; 492 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 }; 496 497 pcfg_pull_up: pcfg-pull-up { 498 bias-pull-up; 499 }; 500 501 pcfg_pull_down: pcfg-pull-down { 502 bias-pull-down; 503 }; 504 505 pcfg_pull_none: pcfg-pull-none { 506 bias-disable; 507 }; 508 509 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 510 drive-strength = <12>; 511 }; 512 513 emmc { 514 emmc_clk: emmc-clk { 515 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 516 }; 517 518 emmc_cmd: emmc-cmd { 519 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 520 }; 521 522 emmc_bus8: emmc-bus8 { 523 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, 524 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, 525 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, 526 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, 527 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, 528 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 529 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, 530 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 531 }; 532 }; 533 534 gmac { 535 rgmii_pins: rgmii-pins { 536 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 537 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 538 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 539 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 540 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 541 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 542 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 543 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 544 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 545 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 546 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 547 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 548 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 549 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 550 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 551 }; 552 553 rmii_pins: rmii-pins { 554 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 555 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 556 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 557 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 558 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 559 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 560 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 561 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 562 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 563 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 564 }; 565 566 phy_pins: phy-pins { 567 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, 568 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 569 }; 570 }; 571 572 i2c0 { 573 i2c0_xfer: i2c0-xfer { 574 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 575 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 576 }; 577 }; 578 579 i2c1 { 580 i2c1_xfer: i2c1-xfer { 581 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 582 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 583 }; 584 }; 585 586 i2c2 { 587 i2c2_xfer: i2c2-xfer { 588 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 589 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 590 }; 591 }; 592 593 i2c3 { 594 i2c3_xfer: i2c3-xfer { 595 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 596 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 597 }; 598 }; 599 600 i2s1 { 601 i2s1_bus: i2s1-bus { 602 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 603 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 604 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 605 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 606 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 607 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 608 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 609 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 610 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 611 }; 612 }; 613 614 pwm0 { 615 pwm0_pin: pwm0-pin { 616 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 617 }; 618 }; 619 620 pwm1 { 621 pwm1_pin: pwm1-pin { 622 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 623 }; 624 }; 625 626 pwm2 { 627 pwm2_pin: pwm2-pin { 628 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 629 }; 630 }; 631 632 pwm3 { 633 pwm3_pin: pwm3-pin { 634 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 635 }; 636 }; 637 638 tsadc { 639 otp_gpio: otp-gpio { 640 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 641 }; 642 643 otp_out: otp-out { 644 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 645 }; 646 }; 647 648 uart0 { 649 uart0_xfer: uart0-xfer { 650 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 651 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; 652 }; 653 654 uart0_cts: uart0-cts { 655 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 656 }; 657 658 uart0_rts: uart0-rts { 659 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 660 }; 661 }; 662 663 uart1 { 664 uart1_xfer: uart1-xfer { 665 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 666 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 667 }; 668 669 uart1_cts: uart1-cts { 670 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 671 }; 672 673 uart1_rts: uart1-rts { 674 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 675 }; 676 }; 677 678 uart2 { 679 uart2_xfer: uart2-xfer { 680 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 681 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 682 }; 683 684 uart2_cts: uart2-cts { 685 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 686 }; 687 688 uart2_rts: uart2-rts { 689 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 690 }; 691 }; 692 }; 693 694 dmc: dmc@11200000 { 695 u-boot,dm-pre-reloc; 696 compatible = "rockchip,rk3228-dmc", "syscon"; 697 rockchip,cru = <&cru>; 698 rockchip,grf = <&grf>; 699 rockchip,msch = <&service_msch>; 700 reg = <0x11200000 0x3fc 701 0x12000000 0x400>; 702 rockchip,sram = <&ddr_sram>; 703 }; 704 705 service_msch: syscon@31090000 { 706 u-boot,dm-pre-reloc; 707 compatible = "rockchip,rk3228-msch", "syscon"; 708 reg = <0x31090000 0x2000>; 709 }; 710}; 711