1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3228-cru.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@f00 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a7"; 33 reg = <0xf00>; 34 resets = <&cru SRST_CORE0>; 35 operating-points = < 36 /* KHz uV */ 37 816000 1000000 38 >; 39 #cooling-cells = <2>; /* min followed by max */ 40 clock-latency = <40000>; 41 clocks = <&cru ARMCLK>; 42 }; 43 44 cpu1: cpu@f01 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a7"; 47 reg = <0xf01>; 48 resets = <&cru SRST_CORE1>; 49 }; 50 51 cpu2: cpu@f02 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a7"; 54 reg = <0xf02>; 55 resets = <&cru SRST_CORE2>; 56 }; 57 58 cpu3: cpu@f03 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a7"; 61 reg = <0xf03>; 62 resets = <&cru SRST_CORE3>; 63 }; 64 }; 65 66 amba { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges; 71 72 pdma: pdma@110f0000 { 73 compatible = "arm,pl330", "arm,primecell"; 74 reg = <0x110f0000 0x4000>; 75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 77 #dma-cells = <1>; 78 clocks = <&cru ACLK_DMAC>; 79 clock-names = "apb_pclk"; 80 }; 81 }; 82 83 arm-pmu { 84 compatible = "arm,cortex-a7-pmu"; 85 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 89 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 90 }; 91 92 timer { 93 compatible = "arm,armv7-timer"; 94 arm,cpu-registers-not-fw-configured; 95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 99 clock-frequency = <24000000>; 100 }; 101 102 xin24m: oscillator { 103 compatible = "fixed-clock"; 104 clock-frequency = <24000000>; 105 clock-output-names = "xin24m"; 106 #clock-cells = <0>; 107 }; 108 109 bus_intmem@10080000 { 110 compatible = "mmio-sram"; 111 reg = <0x10080000 0x9000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0 0x10080000 0x9000>; 115 smp-sram@0 { 116 compatible = "rockchip,rk322x-smp-sram"; 117 reg = <0x00 0x10>; 118 }; 119 ddr_sram: ddr-sram@1000 { 120 compatible = "rockchip,rk322x-ddr-sram"; 121 reg = <0x1000 0x8000>; 122 }; 123 }; 124 125 i2s1: i2s1@100b0000 { 126 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 127 reg = <0x100b0000 0x4000>; 128 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 clock-names = "i2s_clk", "i2s_hclk"; 132 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 133 dmas = <&pdma 14>, <&pdma 15>; 134 dma-names = "tx", "rx"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&i2s1_bus>; 137 status = "disabled"; 138 }; 139 140 i2s0: i2s0@100c0000 { 141 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 142 reg = <0x100c0000 0x4000>; 143 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 clock-names = "i2s_clk", "i2s_hclk"; 147 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 148 dmas = <&pdma 11>, <&pdma 12>; 149 dma-names = "tx", "rx"; 150 status = "disabled"; 151 }; 152 153 i2s2: i2s2@100e0000 { 154 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; 155 reg = <0x100e0000 0x4000>; 156 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 clock-names = "i2s_clk", "i2s_hclk"; 160 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 161 dmas = <&pdma 0>, <&pdma 1>; 162 dma-names = "tx", "rx"; 163 status = "disabled"; 164 }; 165 166 grf: syscon@11000000 { 167 u-boot,dm-pre-reloc; 168 compatible = "rockchip,rk3228-grf", "syscon"; 169 reg = <0x11000000 0x1000>; 170 }; 171 172 uart0: serial@11010000 { 173 compatible = "snps,dw-apb-uart"; 174 reg = <0x11010000 0x100>; 175 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 176 clock-frequency = <24000000>; 177 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 178 clock-names = "baudclk", "apb_pclk"; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 181 reg-shift = <2>; 182 reg-io-width = <4>; 183 status = "disabled"; 184 }; 185 186 uart1: serial@11020000 { 187 compatible = "snps,dw-apb-uart"; 188 reg = <0x11020000 0x100>; 189 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 190 clock-frequency = <24000000>; 191 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 192 clock-names = "baudclk", "apb_pclk"; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&uart1_xfer>; 195 reg-shift = <2>; 196 reg-io-width = <4>; 197 status = "disabled"; 198 }; 199 200 uart2: serial@11030000 { 201 compatible = "snps,dw-apb-uart"; 202 reg = <0x11030000 0x100>; 203 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 204 clock-frequency = <24000000>; 205 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 206 clock-names = "baudclk", "apb_pclk"; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&uart2_xfer>; 209 reg-shift = <2>; 210 reg-io-width = <4>; 211 status = "disabled"; 212 }; 213 214 i2c0: i2c@11050000 { 215 compatible = "rockchip,rk3228-i2c"; 216 reg = <0x11050000 0x1000>; 217 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 clock-names = "i2c"; 221 clocks = <&cru PCLK_I2C0>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&i2c0_xfer>; 224 status = "disabled"; 225 }; 226 227 i2c1: i2c@11060000 { 228 compatible = "rockchip,rk3228-i2c"; 229 reg = <0x11060000 0x1000>; 230 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 clock-names = "i2c"; 234 clocks = <&cru PCLK_I2C1>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&i2c1_xfer>; 237 status = "disabled"; 238 }; 239 240 i2c2: i2c@11070000 { 241 compatible = "rockchip,rk3228-i2c"; 242 reg = <0x11070000 0x1000>; 243 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 clock-names = "i2c"; 247 clocks = <&cru PCLK_I2C2>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&i2c2_xfer>; 250 status = "disabled"; 251 }; 252 253 i2c3: i2c@11080000 { 254 compatible = "rockchip,rk3228-i2c"; 255 reg = <0x11080000 0x1000>; 256 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clock-names = "i2c"; 260 clocks = <&cru PCLK_I2C3>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&i2c3_xfer>; 263 status = "disabled"; 264 }; 265 266 pwm0: pwm@110b0000 { 267 compatible = "rockchip,rk3288-pwm"; 268 reg = <0x110b0000 0x10>; 269 #pwm-cells = <3>; 270 clocks = <&cru PCLK_PWM>; 271 clock-names = "pwm"; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pwm0_pin>; 274 status = "disabled"; 275 }; 276 277 pwm1: pwm@110b0010 { 278 compatible = "rockchip,rk3288-pwm"; 279 reg = <0x110b0010 0x10>; 280 #pwm-cells = <3>; 281 clocks = <&cru PCLK_PWM>; 282 clock-names = "pwm"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pwm1_pin>; 285 status = "disabled"; 286 }; 287 288 pwm2: pwm@110b0020 { 289 compatible = "rockchip,rk3288-pwm"; 290 reg = <0x110b0020 0x10>; 291 #pwm-cells = <3>; 292 clocks = <&cru PCLK_PWM>; 293 clock-names = "pwm"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pwm2_pin>; 296 status = "disabled"; 297 }; 298 299 pwm3: pwm@110b0030 { 300 compatible = "rockchip,rk3288-pwm"; 301 reg = <0x110b0030 0x10>; 302 #pwm-cells = <2>; 303 clocks = <&cru PCLK_PWM>; 304 clock-names = "pwm"; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pwm3_pin>; 307 status = "disabled"; 308 }; 309 310 timer: timer@110c0000 { 311 compatible = "rockchip,rk3288-timer"; 312 reg = <0x110c0000 0x20>; 313 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&xin24m>, <&cru PCLK_TIMER>; 315 clock-names = "timer", "pclk"; 316 }; 317 318 cru: clock-controller@110e0000 { 319 u-boot,dm-pre-reloc; 320 compatible = "rockchip,rk3228-cru"; 321 reg = <0x110e0000 0x1000>; 322 rockchip,grf = <&grf>; 323 #clock-cells = <1>; 324 #reset-cells = <1>; 325 assigned-clocks = <&cru PLL_GPLL>; 326 assigned-clock-rates = <594000000>; 327 }; 328 329 thermal-zones { 330 cpu_thermal: cpu-thermal { 331 polling-delay-passive = <100>; /* milliseconds */ 332 polling-delay = <5000>; /* milliseconds */ 333 334 thermal-sensors = <&tsadc 0>; 335 336 trips { 337 cpu_alert0: cpu_alert0 { 338 temperature = <70000>; /* millicelsius */ 339 hysteresis = <2000>; /* millicelsius */ 340 type = "passive"; 341 }; 342 cpu_alert1: cpu_alert1 { 343 temperature = <75000>; /* millicelsius */ 344 hysteresis = <2000>; /* millicelsius */ 345 type = "passive"; 346 }; 347 cpu_crit: cpu_crit { 348 temperature = <90000>; /* millicelsius */ 349 hysteresis = <2000>; /* millicelsius */ 350 type = "critical"; 351 }; 352 }; 353 354 cooling-maps { 355 map0 { 356 trip = <&cpu_alert0>; 357 cooling-device = 358 <&cpu0 THERMAL_NO_LIMIT 6>; 359 }; 360 map1 { 361 trip = <&cpu_alert1>; 362 cooling-device = 363 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 364 }; 365 }; 366 }; 367 }; 368 369 tsadc: tsadc@11150000 { 370 compatible = "rockchip,rk3228-tsadc"; 371 reg = <0x11150000 0x100>; 372 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 374 clock-names = "tsadc", "apb_pclk"; 375 resets = <&cru SRST_TSADC>; 376 reset-names = "tsadc-apb"; 377 pinctrl-names = "init", "default", "sleep"; 378 pinctrl-0 = <&otp_gpio>; 379 pinctrl-1 = <&otp_out>; 380 pinctrl-2 = <&otp_gpio>; 381 #thermal-sensor-cells = <0>; 382 rockchip,hw-tshut-temp = <95000>; 383 status = "disabled"; 384 }; 385 386 emmc: dwmmc@30020000 { 387 compatible = "rockchip,rk3288-dw-mshc"; 388 reg = <0x30020000 0x4000>; 389 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 390 clock-frequency = <37500000>; 391 max-frequency = <37500000>; 392 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 393 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 394 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 395 bus-width = <8>; 396 default-sample-phase = <158>; 397 num-slots = <1>; 398 fifo-depth = <0x100>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 401 resets = <&cru SRST_EMMC>; 402 reset-names = "reset"; 403 status = "disabled"; 404 }; 405 406 usb20_otg: usb@30040000 { 407 compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", 408 "snps,dwc2"; 409 reg = <0x30040000 0x40000>; 410 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 411 hnp-srp-disable; 412 dr_mode = "otg"; 413 status = "disabled"; 414 }; 415 416 gmac: ethernet@30200000 { 417 compatible = "rockchip,rk3228-gmac"; 418 reg = <0x30200000 0x10000>; 419 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 420 interrupt-names = "macirq"; 421 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 422 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, 423 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 424 <&cru PCLK_GMAC>; 425 clock-names = "stmmaceth", "mac_clk_rx", 426 "mac_clk_tx", "clk_mac_ref", 427 "clk_mac_refout", "aclk_mac", 428 "pclk_mac"; 429 resets = <&cru SRST_GMAC>; 430 reset-names = "stmmaceth"; 431 rockchip,grf = <&grf>; 432 status = "disabled"; 433 }; 434 435 gic: interrupt-controller@32010000 { 436 compatible = "arm,gic-400"; 437 interrupt-controller; 438 #interrupt-cells = <3>; 439 #address-cells = <0>; 440 441 reg = <0x32011000 0x1000>, 442 <0x32012000 0x2000>, 443 <0x32014000 0x2000>, 444 <0x32016000 0x2000>; 445 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 446 }; 447 448 pinctrl: pinctrl { 449 compatible = "rockchip,rk3228-pinctrl"; 450 rockchip,grf = <&grf>; 451 #address-cells = <1>; 452 #size-cells = <1>; 453 ranges; 454 455 gpio0: gpio0@11110000 { 456 compatible = "rockchip,gpio-bank"; 457 reg = <0x11110000 0x100>; 458 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&cru PCLK_GPIO0>; 460 461 gpio-controller; 462 #gpio-cells = <2>; 463 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 }; 467 468 gpio1: gpio1@11120000 { 469 compatible = "rockchip,gpio-bank"; 470 reg = <0x11120000 0x100>; 471 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&cru PCLK_GPIO1>; 473 474 gpio-controller; 475 #gpio-cells = <2>; 476 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 }; 480 481 gpio2: gpio2@11130000 { 482 compatible = "rockchip,gpio-bank"; 483 reg = <0x11130000 0x100>; 484 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cru PCLK_GPIO2>; 486 487 gpio-controller; 488 #gpio-cells = <2>; 489 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 }; 493 494 gpio3: gpio3@11140000 { 495 compatible = "rockchip,gpio-bank"; 496 reg = <0x11140000 0x100>; 497 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cru PCLK_GPIO3>; 499 500 gpio-controller; 501 #gpio-cells = <2>; 502 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 }; 506 507 pcfg_pull_up: pcfg-pull-up { 508 bias-pull-up; 509 }; 510 511 pcfg_pull_down: pcfg-pull-down { 512 bias-pull-down; 513 }; 514 515 pcfg_pull_none: pcfg-pull-none { 516 bias-disable; 517 }; 518 519 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 520 drive-strength = <12>; 521 }; 522 523 emmc { 524 emmc_clk: emmc-clk { 525 rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 526 }; 527 528 emmc_cmd: emmc-cmd { 529 rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 530 }; 531 532 emmc_bus8: emmc-bus8 { 533 rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, 534 <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, 535 <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, 536 <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, 537 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, 538 <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, 539 <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, 540 <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; 541 }; 542 }; 543 544 gmac { 545 rgmii_pins: rgmii-pins { 546 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 547 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 548 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 549 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 550 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 551 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 552 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 553 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 554 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 555 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 556 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 557 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, 558 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, 559 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 560 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 561 }; 562 563 rmii_pins: rmii-pins { 564 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 565 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 566 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 567 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 568 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 569 <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, 570 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 571 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 572 <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 573 <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; 574 }; 575 576 phy_pins: phy-pins { 577 rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, 578 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; 579 }; 580 }; 581 582 i2c0 { 583 i2c0_xfer: i2c0-xfer { 584 rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 585 <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 586 }; 587 }; 588 589 i2c1 { 590 i2c1_xfer: i2c1-xfer { 591 rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 592 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; 593 }; 594 }; 595 596 i2c2 { 597 i2c2_xfer: i2c2-xfer { 598 rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 599 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 600 }; 601 }; 602 603 i2c3 { 604 i2c3_xfer: i2c3-xfer { 605 rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 606 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 607 }; 608 }; 609 610 i2s1 { 611 i2s1_bus: i2s1-bus { 612 rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 613 <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 614 <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 615 <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 616 <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 617 <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 618 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 619 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 620 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 621 }; 622 }; 623 624 pwm0 { 625 pwm0_pin: pwm0-pin { 626 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 627 }; 628 }; 629 630 pwm1 { 631 pwm1_pin: pwm1-pin { 632 rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; 633 }; 634 }; 635 636 pwm2 { 637 pwm2_pin: pwm2-pin { 638 rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; 639 }; 640 }; 641 642 pwm3 { 643 pwm3_pin: pwm3-pin { 644 rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; 645 }; 646 }; 647 648 tsadc { 649 otp_gpio: otp-gpio { 650 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 651 }; 652 653 otp_out: otp-out { 654 rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; 655 }; 656 }; 657 658 uart0 { 659 uart0_xfer: uart0-xfer { 660 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 661 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; 662 }; 663 664 uart0_cts: uart0-cts { 665 rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; 666 }; 667 668 uart0_rts: uart0-rts { 669 rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 670 }; 671 }; 672 673 uart1 { 674 uart1_xfer: uart1-xfer { 675 rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 676 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; 677 }; 678 679 uart1_cts: uart1-cts { 680 rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 681 }; 682 683 uart1_rts: uart1-rts { 684 rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 685 }; 686 }; 687 688 uart2 { 689 uart2_xfer: uart2-xfer { 690 rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, 691 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 692 }; 693 694 uart2_cts: uart2-cts { 695 rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 696 }; 697 698 uart2_rts: uart2-rts { 699 rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 700 }; 701 }; 702 }; 703 704 dmc: dmc@11200000 { 705 u-boot,dm-pre-reloc; 706 compatible = "rockchip,rk3228-dmc", "syscon"; 707 rockchip,cru = <&cru>; 708 rockchip,grf = <&grf>; 709 rockchip,msch = <&service_msch>; 710 reg = <0x11200000 0x3fc 711 0x12000000 0x400>; 712 rockchip,sram = <&ddr_sram>; 713 }; 714 715 service_msch: syscon@31090000 { 716 u-boot,dm-pre-reloc; 717 compatible = "rockchip,rk3228-msch", "syscon"; 718 reg = <0x31090000 0x2000>; 719 }; 720}; 721