xref: /openbmc/u-boot/arch/arm/dts/rk3188.dtsi (revision 7abb7e8f) 
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * SPDX-License-Identifier:     GPL-2.0+ or X11
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rockchip.h>
10#include <dt-bindings/clock/rk3188-cru.h>
11#include "rk3xxx.dtsi"
12
13/ {
14	compatible = "rockchip,rk3188";
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		enable-method = "rockchip,rk3066-smp";
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a9";
24			next-level-cache = <&L2>;
25			reg = <0x0>;
26			operating-points = <
27				/* kHz    uV */
28				1608000 1350000
29				1416000 1250000
30				1200000 1150000
31				1008000 1075000
32				 816000  975000
33				 600000  950000
34				 504000  925000
35				 312000  875000
36			>;
37			clock-latency = <40000>;
38			clocks = <&cru ARMCLK>;
39		};
40		cpu@1 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a9";
43			next-level-cache = <&L2>;
44			reg = <0x1>;
45		};
46		cpu@2 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a9";
49			next-level-cache = <&L2>;
50			reg = <0x2>;
51		};
52		cpu@3 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a9";
55			next-level-cache = <&L2>;
56			reg = <0x3>;
57		};
58	};
59
60	sram: sram@10080000 {
61		compatible = "mmio-sram";
62		reg = <0x10080000 0x8000>;
63		#address-cells = <1>;
64		#size-cells = <1>;
65		ranges = <0 0x10080000 0x8000>;
66
67		smp-sram@0 {
68			compatible = "rockchip,rk3066-smp-sram";
69			reg = <0x0 0x50>;
70		};
71	};
72
73	i2s0: i2s@1011a000 {
74		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
75		reg = <0x1011a000 0x2000>;
76		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
77		#address-cells = <1>;
78		#size-cells = <0>;
79		pinctrl-names = "default";
80		pinctrl-0 = <&i2s0_bus>;
81		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
82		dma-names = "tx", "rx";
83		clock-names = "i2s_hclk", "i2s_clk";
84		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
85		rockchip,playback-channels = <2>;
86		rockchip,capture-channels = <2>;
87		status = "disabled";
88	};
89
90	spdif: sound@1011e000 {
91		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
92		reg = <0x1011e000 0x2000>;
93		#sound-dai-cells = <0>;
94		clock-names = "hclk", "mclk";
95		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
96		dmas = <&dmac1_s 8>;
97		dma-names = "tx";
98		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
99		pinctrl-names = "default";
100		pinctrl-0 = <&spdif_tx>;
101		status = "disabled";
102	};
103
104	cru: clock-controller@20000000 {
105		compatible = "rockchip,rk3188-cru";
106		reg = <0x20000000 0x1000>;
107		rockchip,grf = <&grf>;
108
109		#clock-cells = <1>;
110		#reset-cells = <1>;
111	};
112
113	efuse: efuse@20010000 {
114		compatible = "rockchip,rockchip-efuse";
115		reg = <0x20010000 0x4000>;
116		#address-cells = <1>;
117		#size-cells = <1>;
118		clocks = <&cru PCLK_EFUSE>;
119		clock-names = "pclk_efuse";
120
121		cpu_leakage: cpu_leakage@17 {
122			reg = <0x17 0x1>;
123		};
124	};
125
126	usbphy: phy {
127		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
128		rockchip,grf = <&grf>;
129		#address-cells = <1>;
130		#size-cells = <0>;
131		status = "disabled";
132
133		usbphy0: usb-phy@10c {
134			#phy-cells = <0>;
135			reg = <0x10c>;
136			clocks = <&cru SCLK_OTGPHY0>;
137			clock-names = "phyclk";
138			#clock-cells = <0>;
139		};
140
141		usbphy1: usb-phy@11c {
142			#phy-cells = <0>;
143			reg = <0x11c>;
144			clocks = <&cru SCLK_OTGPHY1>;
145			clock-names = "phyclk";
146			#clock-cells = <0>;
147		};
148	};
149
150	pinctrl: pinctrl {
151		compatible = "rockchip,rk3188-pinctrl";
152		rockchip,grf = <&grf>;
153		rockchip,pmu = <&pmu>;
154
155		#address-cells = <1>;
156		#size-cells = <1>;
157		ranges;
158
159		gpio0: gpio0@2000a000 {
160			compatible = "rockchip,gpio-bank";
161			reg = <0x2000a000 0x100>;
162			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
163			clocks = <&cru PCLK_GPIO0>;
164
165			gpio-controller;
166			#gpio-cells = <2>;
167
168			interrupt-controller;
169			#interrupt-cells = <2>;
170		};
171
172		gpio1: gpio1@2003c000 {
173			compatible = "rockchip,gpio-bank";
174			reg = <0x2003c000 0x100>;
175			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
176			clocks = <&cru PCLK_GPIO1>;
177
178			gpio-controller;
179			#gpio-cells = <2>;
180
181			interrupt-controller;
182			#interrupt-cells = <2>;
183		};
184
185		gpio2: gpio2@2003e000 {
186			compatible = "rockchip,gpio-bank";
187			reg = <0x2003e000 0x100>;
188			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
189			clocks = <&cru PCLK_GPIO2>;
190
191			gpio-controller;
192			#gpio-cells = <2>;
193
194			interrupt-controller;
195			#interrupt-cells = <2>;
196		};
197
198		gpio3: gpio3@20080000 {
199			compatible = "rockchip,gpio-bank";
200			reg = <0x20080000 0x100>;
201			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
202			clocks = <&cru PCLK_GPIO3>;
203
204			gpio-controller;
205			#gpio-cells = <2>;
206
207			interrupt-controller;
208			#interrupt-cells = <2>;
209		};
210
211		pcfg_pull_up: pcfg_pull_up {
212			bias-pull-up;
213		};
214
215		pcfg_pull_down: pcfg_pull_down {
216			bias-pull-down;
217		};
218
219		pcfg_pull_none: pcfg_pull_none {
220			bias-disable;
221		};
222
223		emmc {
224			emmc_clk: emmc-clk {
225				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
226			};
227
228			emmc_cmd: emmc-cmd {
229				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
230			};
231
232			emmc_rst: emmc-rst {
233				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
234			};
235
236			/*
237			 * The data pins are shared between nandc and emmc and
238			 * not accessible through pinctrl. Also they should've
239			 * been already set correctly by firmware, as
240			 * flash/emmc is the boot-device.
241			 */
242		};
243
244		emac {
245			emac_xfer: emac-xfer {
246				rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
247						<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
248						<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
249						<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
250						<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
251						<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
252						<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
253						<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
254			};
255
256			emac_mdio: emac-mdio {
257				rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
258						<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
259			};
260		};
261
262		i2c0 {
263			i2c0_xfer: i2c0-xfer {
264				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
265						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
266			};
267		};
268
269		i2c1 {
270			i2c1_xfer: i2c1-xfer {
271				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
272						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
273			};
274		};
275
276		i2c2 {
277			i2c2_xfer: i2c2-xfer {
278				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
279						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
280			};
281		};
282
283		i2c3 {
284			i2c3_xfer: i2c3-xfer {
285				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
286						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
287			};
288		};
289
290		i2c4 {
291			i2c4_xfer: i2c4-xfer {
292				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
293						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
294			};
295		};
296
297		pwm0 {
298			pwm0_out: pwm0-out {
299				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
300			};
301		};
302
303		pwm1 {
304			pwm1_out: pwm1-out {
305				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
306			};
307		};
308
309		pwm2 {
310			pwm2_out: pwm2-out {
311				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
312			};
313		};
314
315		pwm3 {
316			pwm3_out: pwm3-out {
317				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
318			};
319		};
320
321		spi0 {
322			spi0_clk: spi0-clk {
323				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
324			};
325			spi0_cs0: spi0-cs0 {
326				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
327			};
328			spi0_tx: spi0-tx {
329				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
330			};
331			spi0_rx: spi0-rx {
332				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
333			};
334			spi0_cs1: spi0-cs1 {
335				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
336			};
337		};
338
339		spi1 {
340			spi1_clk: spi1-clk {
341				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
342			};
343			spi1_cs0: spi1-cs0 {
344				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
345			};
346			spi1_rx: spi1-rx {
347				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
348			};
349			spi1_tx: spi1-tx {
350				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
351			};
352			spi1_cs1: spi1-cs1 {
353				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
354			};
355		};
356
357		uart0 {
358			uart0_xfer: uart0-xfer {
359				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
360						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
361			};
362
363			uart0_cts: uart0-cts {
364				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
365			};
366
367			uart0_rts: uart0-rts {
368				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
369			};
370		};
371
372		uart1 {
373			uart1_xfer: uart1-xfer {
374				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
375						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
376			};
377
378			uart1_cts: uart1-cts {
379				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
380			};
381
382			uart1_rts: uart1-rts {
383				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
384			};
385		};
386
387		uart2 {
388			uart2_xfer: uart2-xfer {
389				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
390						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
391			};
392			/* no rts / cts for uart2 */
393		};
394
395		uart3 {
396			uart3_xfer: uart3-xfer {
397				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
398						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
399			};
400
401			uart3_cts: uart3-cts {
402				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
403			};
404
405			uart3_rts: uart3-rts {
406				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
407			};
408		};
409
410		sd0 {
411			sd0_clk: sd0-clk {
412				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
413			};
414
415			sd0_cmd: sd0-cmd {
416				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
417			};
418
419			sd0_cd: sd0-cd {
420				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
421			};
422
423			sd0_wp: sd0-wp {
424				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
425			};
426
427			sd0_pwr: sd0-pwr {
428				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
429			};
430
431			sd0_bus1: sd0-bus-width1 {
432				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
433			};
434
435			sd0_bus4: sd0-bus-width4 {
436				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
437						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
438						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
439						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
440			};
441		};
442
443		sd1 {
444			sd1_clk: sd1-clk {
445				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
446			};
447
448			sd1_cmd: sd1-cmd {
449				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
450			};
451
452			sd1_cd: sd1-cd {
453				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
454			};
455
456			sd1_wp: sd1-wp {
457				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
458			};
459
460			sd1_bus1: sd1-bus-width1 {
461				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
462			};
463
464			sd1_bus4: sd1-bus-width4 {
465				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
466						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
467						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
468						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
469			};
470		};
471
472		i2s0 {
473			i2s0_bus: i2s0-bus {
474				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
475						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
476						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
477						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
478						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
479						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
480			};
481		};
482
483		spdif {
484			spdif_tx: spdif-tx {
485				rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
486			};
487		};
488	};
489};
490
491&emac {
492	compatible = "rockchip,rk3188-emac";
493};
494
495&global_timer {
496	interrupts = <GIC_PPI 11 0xf04>;
497};
498
499&grf {
500	compatible = "rockchip,rk3188-grf", "syscon";
501};
502
503&local_timer {
504	interrupts = <GIC_PPI 13 0xf04>;
505};
506
507&i2c0 {
508	compatible = "rockchip,rk3188-i2c";
509	pinctrl-names = "default";
510	pinctrl-0 = <&i2c0_xfer>;
511};
512
513&i2c1 {
514	compatible = "rockchip,rk3188-i2c";
515	pinctrl-names = "default";
516	pinctrl-0 = <&i2c1_xfer>;
517};
518
519&i2c2 {
520	compatible = "rockchip,rk3188-i2c";
521	pinctrl-names = "default";
522	pinctrl-0 = <&i2c2_xfer>;
523};
524
525&i2c3 {
526	compatible = "rockchip,rk3188-i2c";
527	pinctrl-names = "default";
528	pinctrl-0 = <&i2c3_xfer>;
529};
530
531&i2c4 {
532	compatible = "rockchip,rk3188-i2c";
533	pinctrl-names = "default";
534	pinctrl-0 = <&i2c4_xfer>;
535};
536
537&pmu {
538	compatible = "rockchip,rk3188-pmu", "syscon";
539};
540
541&pwm0 {
542	pinctrl-names = "default";
543	pinctrl-0 = <&pwm0_out>;
544};
545
546&pwm1 {
547	pinctrl-names = "default";
548	pinctrl-0 = <&pwm1_out>;
549};
550
551&pwm2 {
552	pinctrl-names = "default";
553	pinctrl-0 = <&pwm2_out>;
554};
555
556&pwm3 {
557	pinctrl-names = "default";
558	pinctrl-0 = <&pwm3_out>;
559};
560
561&spi0 {
562	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
563	pinctrl-names = "default";
564	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
565};
566
567&spi1 {
568	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
569	pinctrl-names = "default";
570	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
571};
572
573&uart0 {
574	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
575	pinctrl-names = "default";
576	pinctrl-0 = <&uart0_xfer>;
577};
578
579&uart1 {
580	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
581	pinctrl-names = "default";
582	pinctrl-0 = <&uart1_xfer>;
583};
584
585&uart2 {
586	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
587	pinctrl-names = "default";
588	pinctrl-0 = <&uart2_xfer>;
589};
590
591&uart3 {
592	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
593	pinctrl-names = "default";
594	pinctrl-0 = <&uart3_xfer>;
595};
596
597&wdt {
598	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
599};
600