xref: /openbmc/u-boot/arch/arm/dts/rk3188.dtsi (revision 30b1ecd2) 
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * SPDX-License-Identifier:     GPL-2.0+ or X11
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rockchip.h>
10#include <dt-bindings/clock/rk3188-cru.h>
11#include "rk3xxx.dtsi"
12
13/ {
14	compatible = "rockchip,rk3188";
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		enable-method = "rockchip,rk3066-smp";
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a9";
24			next-level-cache = <&L2>;
25			reg = <0x0>;
26			operating-points = <
27				/* kHz    uV */
28				1608000 1350000
29				1416000 1250000
30				1200000 1150000
31				1008000 1075000
32				 816000  975000
33				 600000  950000
34				 504000  925000
35				 312000  875000
36			>;
37			clock-latency = <40000>;
38			clocks = <&cru ARMCLK>;
39		};
40		cpu@1 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a9";
43			next-level-cache = <&L2>;
44			reg = <0x1>;
45		};
46		cpu@2 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a9";
49			next-level-cache = <&L2>;
50			reg = <0x2>;
51		};
52		cpu@3 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a9";
55			next-level-cache = <&L2>;
56			reg = <0x3>;
57		};
58	};
59
60	sram: sram@10080000 {
61		compatible = "mmio-sram";
62		reg = <0x10080000 0x8000>;
63		#address-cells = <1>;
64		#size-cells = <1>;
65		ranges = <0 0x10080000 0x8000>;
66
67		smp-sram@0 {
68			compatible = "rockchip,rk3066-smp-sram";
69			reg = <0x0 0x50>;
70		};
71	};
72
73	i2s0: i2s@1011a000 {
74		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
75		reg = <0x1011a000 0x2000>;
76		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
77		#address-cells = <1>;
78		#size-cells = <0>;
79		pinctrl-names = "default";
80		pinctrl-0 = <&i2s0_bus>;
81		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
82		dma-names = "tx", "rx";
83		clock-names = "i2s_hclk", "i2s_clk";
84		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
85		rockchip,playback-channels = <2>;
86		rockchip,capture-channels = <2>;
87		status = "disabled";
88	};
89
90	spdif: sound@1011e000 {
91		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
92		reg = <0x1011e000 0x2000>;
93		#sound-dai-cells = <0>;
94		clock-names = "hclk", "mclk";
95		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
96		dmas = <&dmac1_s 8>;
97		dma-names = "tx";
98		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
99		pinctrl-names = "default";
100		pinctrl-0 = <&spdif_tx>;
101		status = "disabled";
102	};
103
104	cru: clock-controller@20000000 {
105		compatible = "rockchip,rk3188-cru";
106		reg = <0x20000000 0x1000>;
107		rockchip,grf = <&grf>;
108		u-boot,dm-spl;
109
110		#clock-cells = <1>;
111		#reset-cells = <1>;
112	};
113
114	efuse: efuse@20010000 {
115		compatible = "rockchip,rockchip-efuse";
116		reg = <0x20010000 0x4000>;
117		#address-cells = <1>;
118		#size-cells = <1>;
119		clocks = <&cru PCLK_EFUSE>;
120		clock-names = "pclk_efuse";
121
122		cpu_leakage: cpu_leakage@17 {
123			reg = <0x17 0x1>;
124		};
125	};
126
127	usbphy: phy {
128		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
129		rockchip,grf = <&grf>;
130		#address-cells = <1>;
131		#size-cells = <0>;
132		status = "disabled";
133
134		usbphy0: usb-phy@10c {
135			#phy-cells = <0>;
136			reg = <0x10c>;
137			clocks = <&cru SCLK_OTGPHY0>;
138			clock-names = "phyclk";
139			#clock-cells = <0>;
140		};
141
142		usbphy1: usb-phy@11c {
143			#phy-cells = <0>;
144			reg = <0x11c>;
145			clocks = <&cru SCLK_OTGPHY1>;
146			clock-names = "phyclk";
147			#clock-cells = <0>;
148		};
149	};
150
151	pinctrl: pinctrl {
152		compatible = "rockchip,rk3188-pinctrl";
153		rockchip,grf = <&grf>;
154		rockchip,pmu = <&pmu>;
155
156		#address-cells = <1>;
157		#size-cells = <1>;
158		ranges;
159		u-boot,dm-spl;
160
161		gpio0: gpio0@2000a000 {
162			compatible = "rockchip,gpio-bank";
163			reg = <0x2000a000 0x100>;
164			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
165			clocks = <&cru PCLK_GPIO0>;
166
167			gpio-controller;
168			#gpio-cells = <2>;
169
170			interrupt-controller;
171			#interrupt-cells = <2>;
172		};
173
174		gpio1: gpio1@2003c000 {
175			compatible = "rockchip,gpio-bank";
176			reg = <0x2003c000 0x100>;
177			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
178			clocks = <&cru PCLK_GPIO1>;
179
180			gpio-controller;
181			#gpio-cells = <2>;
182
183			interrupt-controller;
184			#interrupt-cells = <2>;
185		};
186
187		gpio2: gpio2@2003e000 {
188			compatible = "rockchip,gpio-bank";
189			reg = <0x2003e000 0x100>;
190			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
191			clocks = <&cru PCLK_GPIO2>;
192
193			gpio-controller;
194			#gpio-cells = <2>;
195
196			interrupt-controller;
197			#interrupt-cells = <2>;
198		};
199
200		gpio3: gpio3@20080000 {
201			compatible = "rockchip,gpio-bank";
202			reg = <0x20080000 0x100>;
203			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
204			clocks = <&cru PCLK_GPIO3>;
205
206			gpio-controller;
207			#gpio-cells = <2>;
208
209			interrupt-controller;
210			#interrupt-cells = <2>;
211		};
212
213		pcfg_pull_up: pcfg_pull_up {
214			bias-pull-up;
215		};
216
217		pcfg_pull_down: pcfg_pull_down {
218			bias-pull-down;
219		};
220
221		pcfg_pull_none: pcfg_pull_none {
222			bias-disable;
223		};
224
225		emmc {
226			emmc_clk: emmc-clk {
227				rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
228			};
229
230			emmc_cmd: emmc-cmd {
231				rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
232			};
233
234			emmc_rst: emmc-rst {
235				rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
236			};
237
238			/*
239			 * The data pins are shared between nandc and emmc and
240			 * not accessible through pinctrl. Also they should've
241			 * been already set correctly by firmware, as
242			 * flash/emmc is the boot-device.
243			 */
244		};
245
246		emac {
247			emac_xfer: emac-xfer {
248				rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
249						<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
250						<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
251						<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
252						<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
253						<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
254						<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
255						<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
256			};
257
258			emac_mdio: emac-mdio {
259				rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
260						<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
261			};
262		};
263
264		i2c0 {
265			i2c0_xfer: i2c0-xfer {
266				rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
267						<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
268			};
269		};
270
271		i2c1 {
272			i2c1_xfer: i2c1-xfer {
273				rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
274						<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
275			};
276		};
277
278		i2c2 {
279			i2c2_xfer: i2c2-xfer {
280				rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
281						<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
282			};
283		};
284
285		i2c3 {
286			i2c3_xfer: i2c3-xfer {
287				rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
288						<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
289			};
290		};
291
292		i2c4 {
293			i2c4_xfer: i2c4-xfer {
294				rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
295						<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
296			};
297		};
298
299		pwm0 {
300			pwm0_out: pwm0-out {
301				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
302			};
303		};
304
305		pwm1 {
306			pwm1_out: pwm1-out {
307				rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
308			};
309		};
310
311		pwm2 {
312			pwm2_out: pwm2-out {
313				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
314			};
315		};
316
317		pwm3 {
318			pwm3_out: pwm3-out {
319				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
320			};
321		};
322
323		spi0 {
324			spi0_clk: spi0-clk {
325				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
326			};
327			spi0_cs0: spi0-cs0 {
328				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
329			};
330			spi0_tx: spi0-tx {
331				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
332			};
333			spi0_rx: spi0-rx {
334				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
335			};
336			spi0_cs1: spi0-cs1 {
337				rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
338			};
339		};
340
341		spi1 {
342			spi1_clk: spi1-clk {
343				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
344			};
345			spi1_cs0: spi1-cs0 {
346				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
347			};
348			spi1_rx: spi1-rx {
349				rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
350			};
351			spi1_tx: spi1-tx {
352				rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
353			};
354			spi1_cs1: spi1-cs1 {
355				rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
356			};
357		};
358
359		uart0 {
360			uart0_xfer: uart0-xfer {
361				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
362						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
363			};
364
365			uart0_cts: uart0-cts {
366				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
367			};
368
369			uart0_rts: uart0-rts {
370				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
371			};
372		};
373
374		uart1 {
375			uart1_xfer: uart1-xfer {
376				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
377						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
378			};
379
380			uart1_cts: uart1-cts {
381				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
382			};
383
384			uart1_rts: uart1-rts {
385				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
386			};
387		};
388
389		uart2 {
390			uart2_xfer: uart2-xfer {
391				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
392						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
393			};
394			/* no rts / cts for uart2 */
395		};
396
397		uart3 {
398			uart3_xfer: uart3-xfer {
399				rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
400						<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
401			};
402
403			uart3_cts: uart3-cts {
404				rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
405			};
406
407			uart3_rts: uart3-rts {
408				rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
409			};
410		};
411
412		sd0 {
413			sd0_clk: sd0-clk {
414				rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
415			};
416
417			sd0_cmd: sd0-cmd {
418				rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
419			};
420
421			sd0_cd: sd0-cd {
422				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
423			};
424
425			sd0_wp: sd0-wp {
426				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
427			};
428
429			sd0_pwr: sd0-pwr {
430				rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
431			};
432
433			sd0_bus1: sd0-bus-width1 {
434				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
435			};
436
437			sd0_bus4: sd0-bus-width4 {
438				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
439						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
440						<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
441						<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
442			};
443		};
444
445		sd1 {
446			sd1_clk: sd1-clk {
447				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
448			};
449
450			sd1_cmd: sd1-cmd {
451				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
452			};
453
454			sd1_cd: sd1-cd {
455				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
456			};
457
458			sd1_wp: sd1-wp {
459				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
460			};
461
462			sd1_bus1: sd1-bus-width1 {
463				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
464			};
465
466			sd1_bus4: sd1-bus-width4 {
467				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
468						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
469						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
470						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
471			};
472		};
473
474		i2s0 {
475			i2s0_bus: i2s0-bus {
476				rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
477						<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
478						<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
479						<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
480						<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
481						<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
482			};
483		};
484
485		spdif {
486			spdif_tx: spdif-tx {
487				rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
488			};
489		};
490	};
491};
492
493&emac {
494	compatible = "rockchip,rk3188-emac";
495};
496
497&global_timer {
498	interrupts = <GIC_PPI 11 0xf04>;
499};
500
501&grf {
502	compatible = "rockchip,rk3188-grf", "syscon";
503};
504
505&local_timer {
506	interrupts = <GIC_PPI 13 0xf04>;
507};
508
509&i2c0 {
510	compatible = "rockchip,rk3188-i2c";
511	pinctrl-names = "default";
512	pinctrl-0 = <&i2c0_xfer>;
513};
514
515&i2c1 {
516	compatible = "rockchip,rk3188-i2c";
517	pinctrl-names = "default";
518	pinctrl-0 = <&i2c1_xfer>;
519};
520
521&i2c2 {
522	compatible = "rockchip,rk3188-i2c";
523	pinctrl-names = "default";
524	pinctrl-0 = <&i2c2_xfer>;
525};
526
527&i2c3 {
528	compatible = "rockchip,rk3188-i2c";
529	pinctrl-names = "default";
530	pinctrl-0 = <&i2c3_xfer>;
531};
532
533&i2c4 {
534	compatible = "rockchip,rk3188-i2c";
535	pinctrl-names = "default";
536	pinctrl-0 = <&i2c4_xfer>;
537};
538
539&pmu {
540	compatible = "rockchip,rk3188-pmu", "syscon";
541};
542
543&pwm0 {
544	pinctrl-names = "default";
545	pinctrl-0 = <&pwm0_out>;
546};
547
548&pwm1 {
549	pinctrl-names = "default";
550	pinctrl-0 = <&pwm1_out>;
551};
552
553&pwm2 {
554	pinctrl-names = "default";
555	pinctrl-0 = <&pwm2_out>;
556};
557
558&pwm3 {
559	pinctrl-names = "default";
560	pinctrl-0 = <&pwm3_out>;
561};
562
563&spi0 {
564	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
565	pinctrl-names = "default";
566	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
567};
568
569&spi1 {
570	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
571	pinctrl-names = "default";
572	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
573};
574
575&uart0 {
576	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
577	pinctrl-names = "default";
578	pinctrl-0 = <&uart0_xfer>;
579};
580
581&uart1 {
582	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
583	pinctrl-names = "default";
584	pinctrl-0 = <&uart1_xfer>;
585};
586
587&uart2 {
588	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
589	pinctrl-names = "default";
590	pinctrl-0 = <&uart2_xfer>;
591};
592
593&uart3 {
594	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
595	pinctrl-names = "default";
596	pinctrl-0 = <&uart3_xfer>;
597};
598
599&wdt {
600	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
601};
602