1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3128-cru.h> 12#include "skeleton.dtsi" 13 14/ { 15 compatible = "rockchip,rk3128"; 16 rockchip,sram = <&sram>; 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 spi0 = &spi0; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 mmc0 = &emmc; 35 mmc1 = &sdmmc; 36 }; 37 38 memory { 39 device_type = "memory"; 40 reg = <0x60000000 0x40000000>; 41 }; 42 43 arm-pmu { 44 compatible = "arm,cortex-a7-pmu"; 45 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "rockchip,rk3128-smp"; 55 56 cpu0:cpu@0x000 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a7"; 59 reg = <0x000>; 60 operating-points = < 61 /* KHz uV */ 62 816000 1000000 63 >; 64 #cooling-cells = <2>; /* min followed by max */ 65 clock-latency = <40000>; 66 clocks = <&cru ARMCLK>; 67 }; 68 69 cpu1:cpu@0x001 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a7"; 72 reg = <0x001>; 73 }; 74 75 cpu2:cpu@0x002 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a7"; 78 reg = <0x002>; 79 }; 80 81 cpu3:cpu@0x003 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a7"; 84 reg = <0x003>; 85 }; 86 }; 87 88 cpu_axi_bus: cpu_axi_bus { 89 compatible = "rockchip,cpu_axi_bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges; 93 94 qos { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 crypto { 100 reg = <0x10128080 0x20>; 101 }; 102 103 core { 104 reg = <0x1012a000 0x20>; 105 }; 106 107 peri { 108 reg = <0x1012c000 0x20>; 109 }; 110 111 gpu { 112 reg = <0x1012d000 0x20>; 113 }; 114 115 vpu { 116 reg = <0x1012e000 0x20>; 117 }; 118 119 rga { 120 reg = <0x1012f000 0x20>; 121 }; 122 ebc { 123 reg = <0x1012f080 0x20>; 124 }; 125 126 iep { 127 reg = <0x1012f100 0x20>; 128 }; 129 130 lcdc { 131 reg = <0x1012f180 0x20>; 132 rockchip,priority = <3 3>; 133 }; 134 135 vip { 136 reg = <0x1012f200 0x20>; 137 rockchip,priority = <3 3>; 138 }; 139 }; 140 141 msch { 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges; 145 146 msch@10128000 { 147 reg = <0x10128000 0x20>; 148 rockchip,read-latency = <0x3f>; 149 }; 150 }; 151 }; 152 153 psci { 154 compatible = "arm,psci"; 155 method = "smc"; 156 cpu_suspend = <0x84000001>; 157 cpu_off = <0x84000002>; 158 cpu_on = <0x84000003>; 159 migrate = <0x84000005>; 160 }; 161 162 amba { 163 compatible = "arm,amba-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 interrupt-parent = <&gic>; 167 ranges; 168 169 pdma: pdma@20078000 { 170 compatible = "arm,pl330", "arm,primecell"; 171 reg = <0x20078000 0x4000>; 172 arm,pl330-broken-no-flushp;//2 173 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 175 #dma-cells = <1>; 176 clocks = <&cru ACLK_DMAC2>; 177 clock-names = "apb_pclk"; 178 }; 179 }; 180 181 xin24m: xin24m { 182 compatible = "fixed-clock"; 183 clock-frequency = <24000000>; 184 clock-output-names = "xin24m"; 185 #clock-cells = <0>; 186 }; 187 188 xin12m: xin12m { 189 compatible = "fixed-clock"; 190 clocks = <&xin24m>; 191 clock-frequency = <12000000>; 192 clock-output-names = "xin12m"; 193 #clock-cells = <0>; 194 }; 195 196 timer { 197 compatible = "arm,armv7-timer"; 198 arm,cpu-registers-not-fw-configured; 199 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 200 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 201 clock-frequency = <24000000>; 202 }; 203 204 timer@20044000 { 205 compatible = "arm,armv7-timer"; 206 reg = <0x20044000 0xb8>; 207 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 208 rockchip,broadcast = <1>; 209 }; 210 211 watchdog: wdt@2004c000 { 212 compatible = "rockchip,watch dog"; 213 reg = <0x2004c000 0x100>; 214 clock-names = "pclk_wdt"; 215 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 216 rockchip,irq = <1>; 217 rockchip,timeout = <60>; 218 rockchip,atboot = <1>; 219 rockchip,debug = <0>; 220 }; 221 222 reset: reset@20000110 { 223 compatible = "rockchip,reset"; 224 reg = <0x20000110 0x24>; 225 #reset-cells = <1>; 226 }; 227 228 nandc: nandc@10500000 { 229 compatible = "rockchip,rk-nandc"; 230 reg = <0x10500000 0x4000>; 231 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; 234 nandc_id = <0>; 235 clocks = <&cru SCLK_NANDC>, 236 <&cru HCLK_NANDC>, 237 <&cru SRST_NANDC>; 238 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; 239 }; 240 241 dmc: dmc@20004000 { 242 u-boot,dm-pre-reloc; 243 compatible = "rockchip,rk3128-dmc", "syscon"; 244 reg = <0x0 0x20004000 0x0 0x1000>; 245 }; 246 247 cru: clock-controller@20000000 { 248 u-boot,dm-pre-reloc; 249 compatible = "rockchip,rk3128-cru"; 250 reg = <0x20000000 0x1000>; 251 rockchip,grf = <&grf>; 252 #clock-cells = <1>; 253 #reset-cells = <1>; 254 assigned-clocks = <&cru PLL_GPLL>; 255 assigned-clock-rates = <594000000>; 256 }; 257 258 uart0: serial0@20060000 { 259 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 260 reg = <0x20060000 0x100>; 261 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 clock-frequency = <24000000>; 265 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 266 clock-names = "baudclk", "apb_pclk"; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 269 dmas = <&pdma 2>, <&pdma 3>; 270 #dma-cells = <2>; 271 }; 272 273 uart1: serial1@20064000 { 274 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 275 reg = <0x20064000 0x100>; 276 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 277 reg-shift = <2>; 278 reg-io-width = <4>; 279 clock-frequency = <24000000>; 280 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 281 clock-names = "baudclk", "apb_pclk"; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&uart1_xfer>; 284 dmas = <&pdma 4>, <&pdma 5>; 285 #dma-cells = <2>; 286 }; 287 288 uart2: serial2@20068000 { 289 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; 290 reg = <0x20068000 0x100>; 291 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 292 reg-shift = <2>; 293 reg-io-width = <4>; 294 clock-frequency = <24000000>; 295 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 296 clock-names = "baudclk", "apb_pclk"; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&uart2_xfer>; 299 dmas = <&pdma 6>, <&pdma 7>; 300 #dma-cells = <2>; 301 }; 302 303 saradc: saradc@2006c000 { 304 compatible = "rockchip,saradc"; 305 reg = <0x2006c000 0x100>; 306 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 307 #io-channel-cells = <1>; 308 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 309 clock-names = "saradc", "apb_pclk"; 310 resets = <&cru SRST_SARADC>; 311 reset-names = "saradc-apb"; 312 status = "disabled"; 313 }; 314 315 pwm0: pwm0@20050000 { 316 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 317 reg = <0x20050000 0x10>; 318 #pwm-cells = <3>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pwm0_pin>; 321 clocks = <&cru PCLK_PWM>; 322 clock-names = "pwm"; 323 }; 324 325 pwm1: pwm1@20050010 { 326 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 327 reg = <0x20050010 0x10>; 328 #pwm-cells = <3>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pwm1_pin>; 331 clocks = <&cru PCLK_PWM>; 332 clock-names = "pwm"; 333 }; 334 335 pwm2: pwm2@20050020 { 336 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 337 reg = <0x20050020 0x10>; 338 #pwm-cells = <3>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pwm2_pin>; 341 clocks = <&cru PCLK_PWM>; 342 clock-names = "pwm"; 343 }; 344 345 pwm3: pwm3@20050030 { 346 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; 347 reg = <0x20050030 0x10>; 348 #pwm-cells = <3>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pwm3_pin>; 351 clocks = <&cru PCLK_PWM>; 352 clock-names = "pwm"; 353 }; 354 355 sram: sram@10080400 { 356 compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; 357 reg = <0x10080400 0x1C00>; 358 map-exec; 359 map-cacheable; 360 }; 361 362 pmu: syscon@100a0000 { 363 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; 364 reg = <0x100a0000 0x1000>; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 }; 368 369 gic: interrupt-controller@10139000 { 370 compatible = "arm,gic-400"; 371 interrupt-controller; 372 #interrupt-cells = <3>; 373 #address-cells = <0>; 374 reg = <0x10139000 0x1000>, 375 <0x1013a000 0x1000>, 376 <0x1013c000 0x2000>, 377 <0x1013e000 0x2000>; 378 interrupts = <GIC_PPI 9 0xf04>; 379 }; 380 381 u2phy: usb2-phy { 382 compatible = "rockchip,rk3128-usb2phy"; 383 reg = <0x017c 0x0c>; 384 rockchip,grf = <&grf>; 385 clocks = <&cru SCLK_OTGPHY0>; 386 clock-names = "phyclk"; 387 #clock-cells = <0>; 388 clock-output-names = "usb480m_phy"; 389 #phy-cells = <1>; 390 status = "disabled"; 391 392 u2phy_otg: otg-port { 393 #phy-cells = <0>; 394 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 397 interrupt-names = "otg-bvalid", "otg-id", 398 "linestate"; 399 status = "disabled"; 400 }; 401 402 u2phy_host: host-port { 403 #phy-cells = <0>; 404 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 405 interrupt-names = "linestate"; 406 status = "disabled"; 407 }; 408 }; 409 410 usb_otg: usb@10180000 { 411 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", 412 "snps,dwc2"; 413 reg = <0x10180000 0x40000>; 414 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 415 dr_mode = "otg"; 416 g-use-dma; 417 hnp-srp-disable; 418 phys = <&u2phy 0>; 419 phy-names = "usb"; 420 status = "disabled"; 421 }; 422 423 usb_host_ehci: usb@101c0000 { 424 compatible = "generic-ehci"; 425 reg = <0x101c0000 0x20000>; 426 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 427 phys = <&u2phy 1>; 428 phy-names = "usb"; 429 status = "disabled"; 430 }; 431 432 usb_host_ohci: usb@101e0000 { 433 compatible = "generic-ohci"; 434 reg = <0x101e0000 0x20000>; 435 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 436 phys = <&u2phy 1>; 437 phy-names = "usb"; 438 status = "disabled"; 439 }; 440 441 sdmmc: dwmmc@10214000 { 442 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; 443 reg = <0x10214000 0x4000>; 444 max-frequency = <150000000>; 445 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 447 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 448 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 449 fifo-depth = <0x100>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 452 bus-width = <4>; 453 status = "disabled"; 454 }; 455 456 emmc: dwmmc@1021c000 { 457 u-boot,dm-pre-reloc; 458 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; 459 reg = <0x1021c000 0x4000>; 460 max-frequency = <150000000>; 461 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 463 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 464 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 465 bus-width = <8>; 466 default-sample-phase = <158>; 467 num-slots = <1>; 468 fifo-depth = <0x100>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 471 resets = <&cru SRST_EMMC>; 472 reset-names = "reset"; 473 status = "disabled"; 474 }; 475 476 i2c0: i2c0@20072000 { 477 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 478 reg = <20072000 0x1000>; 479 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 clock-names = "i2c"; 483 clocks = <&cru PCLK_I2C0>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&i2c0_xfer>; 486 }; 487 488 i2c1: i2c1@20056000 { 489 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 490 reg = <0x20056000 0x1000>; 491 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 clock-names = "i2c"; 495 clocks = <&cru PCLK_I2C1>; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&i2c1_xfer>; 498 }; 499 500 i2c2: i2c2@2005a000 { 501 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 502 reg = <0x2005a000 0x1000>; 503 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 clock-names = "i2c"; 507 clocks = <&cru PCLK_I2C2>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&i2c2_xfer>; 510 }; 511 512 i2c3: i2c3@2005e000 { 513 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; 514 reg = <0x2005e000 0x1000>; 515 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 clock-names = "i2c"; 519 clocks = <&cru PCLK_I2C3>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&i2c3_xfer>; 522 }; 523 524 spi0: spi@20074000 { 525 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; 526 reg = <0x20074000 0x1000>; 527 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; 532 rockchip,spi-src-clk = <0>; 533 num-cs = <2>; 534 clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; 535 clock-names = "spi","pclk_spi0"; 536 dmas = <&pdma 8>, <&pdma 9>; 537 #dma-cells = <2>; 538 dma-names = "tx", "rx"; 539 }; 540 541 grf: syscon@20008000 { 542 u-boot,dm-pre-reloc; 543 compatible = "rockchip,rk3128-grf", "syscon"; 544 reg = <0x20008000 0x1000>; 545 }; 546 547 pinctrl: pinctrl@20008000 { 548 compatible = "rockchip,rk3128-pinctrl"; 549 reg = <0x20008000 0xA8>, 550 <0x200080A8 0x4C>, 551 <0x20008118 0x20>, 552 <0x20008100 0x04>; 553 reg-names = "base", "mux", "pull", "drv"; 554 rockchip,grf = <&grf>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 ranges; 558 559 gpio0: gpio0@2007c000 { 560 compatible = "rockchip,gpio-bank"; 561 reg = <0x2007c000 0x100>; 562 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&cru PCLK_GPIO0>; 564 gpio-controller; 565 #gpio-cells = <2>; 566 interrupt-controller; 567 #interrupt-cells = <2>; 568 }; 569 570 gpio1: gpio1@20080000 { 571 compatible = "rockchip,gpio-bank"; 572 reg = <0x20080000 0x100>; 573 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cru PCLK_GPIO1>; 575 gpio-controller; 576 #gpio-cells = <2>; 577 interrupt-controller; 578 #interrupt-cells = <2>; 579 }; 580 581 gpio2: gpio2@20084000 { 582 compatible = "rockchip,gpio-bank"; 583 reg = <0x20084000 0x100>; 584 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&cru PCLK_GPIO2>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 interrupt-controller; 589 #interrupt-cells = <2>; 590 }; 591 592 gpio3: gpio2@20088000 { 593 compatible = "rockchip,gpio-bank"; 594 reg = <0x20088000 0x100>; 595 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cru PCLK_GPIO3>; 597 gpio-controller; 598 #gpio-cells = <2>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 }; 602 603 pcfg_pull_up: pcfg-pull-up { 604 bias-pull-up; 605 }; 606 607 pcfg_pull_down: pcfg-pull-down { 608 bias-pull-down; 609 }; 610 611 pcfg_pull_none: pcfg-pull-none { 612 bias-disable; 613 }; 614 615 emmc { 616 /* 617 * We run eMMC at max speed; bump up drive strength. 618 * We also have external pulls, so disable the internal ones. 619 */ 620 621 emmc_clk: emmc-clk { 622 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; 623 }; 624 625 emmc_cmd: emmc-cmd { 626 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 627 }; 628 629 emmc_pwren: emmc-pwren { 630 rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; 631 }; 632 633 emmc_bus8: emmc-bus8 { 634 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, 635 <1 25 RK_FUNC_2 &pcfg_pull_none>, 636 <1 26 RK_FUNC_2 &pcfg_pull_none>, 637 <1 27 RK_FUNC_2 &pcfg_pull_none>, 638 <1 28 RK_FUNC_2 &pcfg_pull_none>, 639 <1 29 RK_FUNC_2 &pcfg_pull_none>, 640 <1 30 RK_FUNC_2 &pcfg_pull_none>, 641 <1 31 RK_FUNC_2 &pcfg_pull_none>; 642 }; 643 }; 644 645 nandc{ 646 nandc_ale:nandc-ale { 647 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 648 }; 649 650 nandc_cle:nandc-cle { 651 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 652 }; 653 654 nandc_wrn:nandc-wrn { 655 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 656 }; 657 658 nandc_rdn:nandc-rdn { 659 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 660 }; 661 662 nandc_rdy:nandc-rdy { 663 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 664 }; 665 666 nandc_cs0:nandc-cs0 { 667 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 668 }; 669 670 nandc_data: nandc-data { 671 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 672 }; 673 }; 674 675 uart0 { 676 uart0_xfer: uart0-xfer { 677 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, 678 <0 17 RK_FUNC_1 &pcfg_pull_none>; 679 }; 680 681 uart0_cts: uart0-cts { 682 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; 683 }; 684 685 uart0_rts: uart0-rts { 686 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; 687 }; 688 }; 689 690 uart1 { 691 uart1_xfer: uart1-xfer { 692 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, 693 <2 23 RK_FUNC_1 &pcfg_pull_none>; 694 }; 695 }; 696 697 uart2 { 698 uart2_xfer: uart2-xfer { 699 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, 700 <1 19 RK_FUNC_2 &pcfg_pull_none>; 701 }; 702 }; 703 704 sdmmc { 705 sdmmc_clk: sdmmc-clk { 706 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 707 }; 708 709 sdmmc_cmd: sdmmc-cmd { 710 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; 711 }; 712 713 sdmmc_wp: sdmmc-wp { 714 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; 715 }; 716 717 sdmmc_pwren: sdmmc-pwren { 718 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; 719 }; 720 721 sdmmc_bus4: sdmmc-bus4 { 722 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, 723 <1 RK_PC3 1 &pcfg_pull_up>, 724 <1 RK_PC4 1 &pcfg_pull_up>, 725 <1 RK_PC5 1 &pcfg_pull_up>; 726 }; 727 }; 728 729 pwm0 { 730 pwm0_pin: pwm0-pin { 731 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; 732 }; 733 }; 734 735 pwm1 { 736 pwm1_pin: pwm1-pin { 737 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; 738 }; 739 }; 740 741 pwm2 { 742 pwm2_pin: pwm2-pin { 743 rockchip,pins = <0 1 2 &pcfg_pull_none>; 744 }; 745 }; 746 747 pwm3 { 748 pwm3_pin: pwm3-pin { 749 rockchip,pins = <0 27 1 &pcfg_pull_none>; 750 }; 751 }; 752 753 i2c0 { 754 i2c0_xfer: i2c0-xfer { 755 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, 756 <0 1 RK_FUNC_1 &pcfg_pull_none>; 757 }; 758 }; 759 760 i2c1 { 761 i2c1_xfer: i2c1-xfer { 762 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, 763 <0 3 RK_FUNC_1 &pcfg_pull_none>; 764 }; 765 }; 766 767 i2c2 { 768 i2c2_xfer: i2c2-xfer { 769 rockchip,pins = <2 20 3 &pcfg_pull_none>, 770 <2 21 3 &pcfg_pull_none>; 771 }; 772 }; 773 774 i2c3 { 775 i2c3_xfer: i2c3-xfer { 776 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 777 <0 7 RK_FUNC_1 &pcfg_pull_none>; 778 }; 779 }; 780 781 spi0 { 782 spi0_txd_mux0:spi0-txd-mux0 { 783 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 784 }; 785 786 spi0_rxd_mux0:spi0-rxd-mux0 { 787 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 788 }; 789 790 spi0_clk_mux0:spi0-clk-mux0 { 791 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 792 }; 793 794 spi0_cs0_mux0:spi0-cs0-mux0 { 795 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 796 }; 797 798 spi0_cs1_mux0:spi0-cs1-mux0 { 799 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 800 }; 801 }; 802 803 }; 804}; 805