xref: /openbmc/u-boot/arch/arm/dts/rk3036.dtsi (revision cbd2fba1) 
1// SPDX-License-Identifier: GPL-2.0+
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <dt-bindings/clock/rk3036-cru.h>
8#include "skeleton.dtsi"
9
10/ {
11	compatible = "rockchip,rk3036";
12
13	interrupt-parent = <&gic>;
14
15	aliases {
16		gpio0 = &gpio0;
17		gpio1 = &gpio1;
18		gpio2 = &gpio2;
19		i2c1 = &i2c1;
20		serial0 = &uart0;
21		serial1 = &uart1;
22		serial2 = &uart2;
23		mmc0 = &emmc;
24		mmc1 = &sdmmc;
25	};
26
27	memory {
28		device_type = "memory";
29		reg = <0x60000000 0x40000000>;
30	};
31
32        arm-pmu {
33                compatible = "arm,cortex-a7-pmu";
34                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
35                             <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
36                interrupt-affinity = <&cpu0>, <&cpu1>;
37        };
38
39	cpus {
40		#address-cells = <1>;
41		#size-cells = <0>;
42		enable-method = "rockchip,rk3036-smp";
43
44		cpu0: cpu@f00 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a7";
47			reg = <0xf00>;
48			operating-points = <
49				/* KHz    uV */
50				 816000 1000000
51			>;
52			#cooling-cells = <2>; /* min followed by max */
53			clock-latency = <40000>;
54			clocks = <&cru ARMCLK>;
55			resets = <&cru SRST_CORE0>;
56		};
57		cpu1: cpu@f01 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a7";
60			reg = <0xf01>;
61			resets = <&cru SRST_CORE1>;
62		};
63	};
64
65	amba {
66		compatible = "arm,amba-bus";
67		#address-cells = <1>;
68		#size-cells = <1>;
69		ranges;
70
71                pdma: pdma@20078000 {
72                        compatible = "arm,pl330", "arm,primecell";
73                        reg = <0x20078000 0x4000>;
74                        arm,pl330-broken-no-flushp;
75                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
76                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
77                        #dma-cells = <1>;
78                        clocks = <&cru ACLK_DMAC2>;
79                        clock-names = "apb_pclk";
80                };
81	};
82
83	xin24m: oscillator {
84		compatible = "fixed-clock";
85		clock-frequency = <24000000>;
86		clock-output-names = "xin24m";
87		#clock-cells = <0>;
88	};
89
90	timer {
91		compatible = "arm,armv7-timer";
92		arm,cpu-registers-not-fw-configured;
93		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
94			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
95			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
96			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
97		clock-frequency = <24000000>;
98	};
99
100	cru: clock-controller@20000000 {
101		compatible = "rockchip,rk3036-cru";
102		reg = <0x20000000 0x1000>;
103		rockchip,grf = <&grf>;
104		#clock-cells = <1>;
105		#reset-cells = <1>;
106		assigned-clocks = <&cru PLL_GPLL>;
107		assigned-clock-rates = <594000000>;
108	};
109
110	uart0: serial@20060000 {
111		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
112		reg = <0x20060000 0x100>;
113		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
114		reg-shift = <2>;
115		reg-io-width = <4>;
116		clock-frequency = <24000000>;
117		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
118		clock-names = "baudclk", "apb_pclk";
119		pinctrl-names = "default";
120		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
121	};
122
123	uart1: serial@20064000 {
124		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
125		reg = <0x20064000 0x100>;
126		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
127		reg-shift = <2>;
128		reg-io-width = <4>;
129		clock-frequency = <24000000>;
130		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
131		clock-names = "baudclk", "apb_pclk";
132		pinctrl-names = "default";
133		pinctrl-0 = <&uart1_xfer>;
134	};
135
136	uart2: serial@20068000 {
137		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
138		reg = <0x20068000 0x100>;
139		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
140		reg-shift = <2>;
141		reg-io-width = <4>;
142		clock-frequency = <24000000>;
143		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
144		clock-names = "baudclk", "apb_pclk";
145		pinctrl-names = "default";
146		pinctrl-0 = <&uart2_xfer>;
147	};
148
149	pwm0: pwm@20050000 {
150		compatible = "rockchip,rk2928-pwm";
151		reg = <0x20050000 0x10>;
152		#pwm-cells = <3>;
153		pinctrl-names = "default";
154		pinctrl-0 = <&pwm0_pin>;
155		clocks = <&cru PCLK_PWM>;
156		clock-names = "pwm";
157		status = "disabled";
158	};
159
160	pwm1: pwm@20050010 {
161		compatible = "rockchip,rk2928-pwm";
162		reg = <0x20050010 0x10>;
163		#pwm-cells = <3>;
164		pinctrl-names = "default";
165		pinctrl-0 = <&pwm1_pin>;
166		clocks = <&cru PCLK_PWM>;
167		clock-names = "pwm";
168		status = "disabled";
169	};
170
171	pwm2: pwm@20050020 {
172		compatible = "rockchip,rk2928-pwm";
173		reg = <0x20050020 0x10>;
174		#pwm-cells = <3>;
175		pinctrl-names = "default";
176		pinctrl-0 = <&pwm2_pin>;
177		clocks = <&cru PCLK_PWM>;
178		clock-names = "pwm";
179		status = "disabled";
180	};
181
182	pwm3: pwm@20050030 {
183		compatible = "rockchip,rk2928-pwm";
184		reg = <0x20050030 0x10>;
185		#pwm-cells = <2>;
186		pinctrl-names = "default";
187		pinctrl-0 = <&pwm3_pin>;
188		clocks = <&cru PCLK_PWM>;
189		clock-names = "pwm";
190		status = "disabled";
191	};
192
193	sram: sram@10080000 {
194		compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
195		reg = <0x10080000 0x2000>;
196	};
197
198	gic: interrupt-controller@10139000 {
199		compatible = "arm,gic-400";
200		interrupt-controller;
201		#interrupt-cells = <3>;
202		#address-cells = <0>;
203
204		reg = <0x10139000 0x1000>,
205		      <0x1013a000 0x1000>,
206		      <0x1013c000 0x2000>,
207		      <0x1013e000 0x2000>;
208		interrupts = <GIC_PPI 9 0xf04>;
209	};
210
211	grf: syscon@20008000 {
212		compatible = "rockchip,rk3036-grf", "syscon";
213		reg = <0x20008000 0x1000>;
214	};
215
216	usb_otg: usb@10180000 {
217		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
218				"snps,dwc2";
219		reg = <0x10180000 0x40000>;
220		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
221		clocks = <&cru HCLK_OTG0>;
222		clock-names = "otg";
223		dr_mode = "otg";
224		g-np-tx-fifo-size = <16>;
225		g-rx-fifo-size = <275>;
226		g-tx-fifo-size = <256 128 128 64 64 32>;
227		g-use-dma;
228		status = "disabled";
229	};
230
231	usb_host: usb@101c0000 {
232		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
233				"snps,dwc2";
234		reg = <0x101c0000 0x40000>;
235		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
236		clocks = <&cru HCLK_OTG1>;
237		clock-names = "otg";
238		dr_mode = "host";
239		status = "disabled";
240	};
241
242	emmc: dwmmc@1021c000 {
243		compatible = "rockchip,rk3288-dw-mshc";
244		clock-frequency = <37500000>;
245		max-frequency = <37500000>;
246		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
247		<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
248		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
249		dmas = <&pdma 12>;
250		dma-names = "rx-tx";
251		fifo-depth = <0x100>;
252		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
253		reg = <0x1021c000 0x4000>;
254		broken-cd;
255		bus-width = <8>;
256		cap-mmc-highspeed;
257		mmc-ddr-1_8v;
258		disable-wp;
259		fifo-mode;
260		non-removable;
261		num-slots = <1>;
262		default-sample-phase = <158>;
263		pinctrl-names = "default";
264		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
265	};
266
267	sdmmc: dwmmc@10214000 {
268		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
269		reg = <0x10214000 0x4000>;
270		clock-frequency = <37500000>;
271		max-frequency = <37500000>;
272		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
273		clock-names = "biu", "ciu";
274		fifo-depth = <0x100>;
275		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
276		status = "disabled";
277	};
278
279	pinctrl: pinctrl {
280		compatible = "rockchip,rk3036-pinctrl";
281		rockchip,grf = <&grf>;
282		#address-cells = <1>;
283		#size-cells = <1>;
284		ranges;
285
286		gpio0: gpio0@2007c000 {
287			compatible = "rockchip,gpio-bank";
288			reg = <0x2007c000 0x100>;
289			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
290			clocks = <&cru PCLK_GPIO0>;
291
292			gpio-controller;
293			#gpio-cells = <2>;
294
295			interrupt-controller;
296			#interrupt-cells = <2>;
297		};
298
299		gpio1: gpio1@20080000 {
300			compatible = "rockchip,gpio-bank";
301			reg = <0x20080000 0x100>;
302			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
303			clocks = <&cru PCLK_GPIO1>;
304
305			gpio-controller;
306			#gpio-cells = <2>;
307
308			interrupt-controller;
309			#interrupt-cells = <2>;
310		};
311
312		gpio2: gpio2@20084000 {
313			compatible = "rockchip,gpio-bank";
314			reg = <0x20084000 0x100>;
315			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
316			clocks = <&cru PCLK_GPIO2>;
317
318			gpio-controller;
319			#gpio-cells = <2>;
320
321			interrupt-controller;
322			#interrupt-cells = <2>;
323		};
324
325		pcfg_pull_up: pcfg-pull-up {
326			bias-pull-up;
327		};
328
329		pcfg_pull_down: pcfg-pull-down {
330			bias-pull-down;
331		};
332
333		pcfg_pull_none: pcfg-pull-none {
334			bias-disable;
335		};
336
337		emmc {
338			/*
339			 * We run eMMC at max speed; bump up drive strength.
340			 * We also have external pulls, so disable the internal ones.
341			 */
342			emmc_clk: emmc-clk {
343				rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
344			};
345
346			emmc_cmd: emmc-cmd {
347				rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
348			};
349
350			emmc_bus8: emmc-bus8 {
351				rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
352						<1 25 RK_FUNC_2 &pcfg_pull_none>,
353						<1 26 RK_FUNC_2 &pcfg_pull_none>,
354						<1 27 RK_FUNC_2 &pcfg_pull_none>;
355				/*
356						<1 28 RK_FUNC_2 &pcfg_pull_up>,
357						<1 29 RK_FUNC_2 &pcfg_pull_up>,
358						<1 30 RK_FUNC_2 &pcfg_pull_up>,
359						<1 31 RK_FUNC_2 &pcfg_pull_up>;
360						*/
361			};
362		};
363
364		uart0 {
365			uart0_xfer: uart0-xfer {
366				rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
367						<0 17 RK_FUNC_1 &pcfg_pull_none>;
368			};
369
370			uart0_cts: uart0-cts {
371				rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
372			};
373
374			uart0_rts: uart0-rts {
375				rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
376			};
377		};
378
379		uart1 {
380			uart1_xfer: uart1-xfer {
381				rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
382						<2 23 RK_FUNC_1 &pcfg_pull_none>;
383			};
384			/* no rts / cts for uart1 */
385		};
386
387                uart2 {
388                        uart2_xfer: uart2-xfer {
389                                rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
390                                                <1 19 RK_FUNC_2 &pcfg_pull_none>;
391                        };
392                        /* no rts / cts for uart2 */
393                };
394
395		pwm0 {
396			pwm0_pin: pwm0-pin {
397				rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
398			};
399		};
400
401		pwm1 {
402			pwm1_pin: pwm1-pin {
403				rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
404			};
405		};
406
407		pwm2 {
408			pwm2_pin: pwm2-pin {
409				rockchip,pins = <0 1 2 &pcfg_pull_none>;
410			};
411		};
412
413		pwm3 {
414			pwm3_pin: pwm3-pin {
415				rockchip,pins = <0 27 1 &pcfg_pull_none>;
416			};
417		};
418
419		i2c1 {
420			i2c1_xfer: i2c1-xfer {
421				rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
422						<0 3 RK_FUNC_1 &pcfg_pull_none>;
423			};
424		};
425	};
426
427	i2c1: i2c@20056000 {
428		compatible = "rockchip,rk3288-i2c";
429		reg = <0x20056000 0x1000>;
430		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
431		#address-cells = <1>;
432		#size-cells = <0>;
433		clock-names = "i2c";
434		clocks = <&cru PCLK_I2C1>;
435		pinctrl-names = "default";
436		pinctrl-0 = <&i2c1_xfer>;
437		status = "disabled";
438	};
439};
440