1/* 2 * Device Tree Source for the r8a77995 SoC 3 * 4 * Copyright (C) 2016 Renesas Electronics Corp. 5 * Copyright (C) 2017 Glider bvba 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/r8a77995-cpg-mssr.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/r8a77995-sysc.h> 15 16/ { 17 compatible = "renesas,r8a77995"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 a53_0: cpu@0 { 31 compatible = "arm,cortex-a53", "arm,armv8"; 32 reg = <0x0>; 33 device_type = "cpu"; 34 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 35 next-level-cache = <&L2_CA53>; 36 enable-method = "psci"; 37 }; 38 39 L2_CA53: cache-controller-1 { 40 compatible = "cache"; 41 power-domains = <&sysc R8A77995_PD_CA53_SCU>; 42 cache-unified; 43 cache-level = <2>; 44 }; 45 }; 46 47 extal_clk: extal { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 /* This value must be overridden by the board */ 51 clock-frequency = <0>; 52 u-boot,dm-pre-reloc; 53 }; 54 55 scif_clk: scif { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 }; 60 61 soc { 62 compatible = "simple-bus"; 63 interrupt-parent = <&gic>; 64 #address-cells = <2>; 65 #size-cells = <2>; 66 ranges; 67 u-boot,dm-pre-reloc; 68 69 gic: interrupt-controller@f1010000 { 70 compatible = "arm,gic-400"; 71 #interrupt-cells = <3>; 72 #address-cells = <0>; 73 interrupt-controller; 74 reg = <0x0 0xf1010000 0 0x1000>, 75 <0x0 0xf1020000 0 0x20000>, 76 <0x0 0xf1040000 0 0x20000>, 77 <0x0 0xf1060000 0 0x20000>; 78 interrupts = <GIC_PPI 9 79 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 80 clocks = <&cpg CPG_MOD 408>; 81 clock-names = "clk"; 82 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 83 resets = <&cpg 408>; 84 }; 85 86 timer { 87 compatible = "arm,armv8-timer"; 88 interrupts = <GIC_PPI 13 89 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 14 91 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 92 <GIC_PPI 11 93 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 94 <GIC_PPI 10 95 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 96 }; 97 98 rwdt: watchdog@e6020000 { 99 compatible = "renesas,r8a77995-wdt", 100 "renesas,rcar-gen3-wdt"; 101 reg = <0 0xe6020000 0 0x0c>; 102 clocks = <&cpg CPG_MOD 402>; 103 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 104 resets = <&cpg 402>; 105 status = "disabled"; 106 }; 107 108 pmu_a53 { 109 compatible = "arm,cortex-a53-pmu"; 110 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 cpg: clock-controller@e6150000 { 114 compatible = "renesas,r8a77995-cpg-mssr"; 115 reg = <0 0xe6150000 0 0x1000>; 116 clocks = <&extal_clk>; 117 clock-names = "extal"; 118 #clock-cells = <2>; 119 #power-domain-cells = <0>; 120 #reset-cells = <1>; 121 u-boot,dm-pre-reloc; 122 }; 123 124 rst: reset-controller@e6160000 { 125 compatible = "renesas,r8a77995-rst"; 126 reg = <0 0xe6160000 0 0x0200>; 127 }; 128 129 pfc: pin-controller@e6060000 { 130 compatible = "renesas,pfc-r8a77995"; 131 reg = <0 0xe6060000 0 0x508>; 132 }; 133 134 prr: chipid@fff00044 { 135 compatible = "renesas,prr"; 136 reg = <0 0xfff00044 0 4>; 137 u-boot,dm-pre-reloc; 138 }; 139 140 sysc: system-controller@e6180000 { 141 compatible = "renesas,r8a77995-sysc"; 142 reg = <0 0xe6180000 0 0x0400>; 143 #power-domain-cells = <1>; 144 }; 145 146 intc_ex: interrupt-controller@e61c0000 { 147 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 148 #interrupt-cells = <2>; 149 interrupt-controller; 150 reg = <0 0xe61c0000 0 0x200>; 151 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 152 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 153 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 154 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 155 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 156 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&cpg CPG_MOD 407>; 158 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 159 resets = <&cpg 407>; 160 }; 161 162 gpio0: gpio@e6050000 { 163 compatible = "renesas,gpio-r8a77995", 164 "renesas,rcar-gen3-gpio", 165 "renesas,gpio-rcar"; 166 reg = <0 0xe6050000 0 0x50>; 167 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 0 9>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 912>; 174 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 175 resets = <&cpg 912>; 176 }; 177 178 gpio1: gpio@e6051000 { 179 compatible = "renesas,gpio-r8a77995", 180 "renesas,rcar-gen3-gpio", 181 "renesas,gpio-rcar"; 182 reg = <0 0xe6051000 0 0x50>; 183 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 184 #gpio-cells = <2>; 185 gpio-controller; 186 gpio-ranges = <&pfc 0 32 32>; 187 #interrupt-cells = <2>; 188 interrupt-controller; 189 clocks = <&cpg CPG_MOD 911>; 190 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 191 resets = <&cpg 911>; 192 }; 193 194 gpio2: gpio@e6052000 { 195 compatible = "renesas,gpio-r8a77995", 196 "renesas,rcar-gen3-gpio", 197 "renesas,gpio-rcar"; 198 reg = <0 0xe6052000 0 0x50>; 199 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 200 #gpio-cells = <2>; 201 gpio-controller; 202 gpio-ranges = <&pfc 0 64 32>; 203 #interrupt-cells = <2>; 204 interrupt-controller; 205 clocks = <&cpg CPG_MOD 910>; 206 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 207 resets = <&cpg 910>; 208 }; 209 210 gpio3: gpio@e6053000 { 211 compatible = "renesas,gpio-r8a77995", 212 "renesas,rcar-gen3-gpio", 213 "renesas,gpio-rcar"; 214 reg = <0 0xe6053000 0 0x50>; 215 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 216 #gpio-cells = <2>; 217 gpio-controller; 218 gpio-ranges = <&pfc 0 96 10>; 219 #interrupt-cells = <2>; 220 interrupt-controller; 221 clocks = <&cpg CPG_MOD 909>; 222 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 223 resets = <&cpg 909>; 224 }; 225 226 gpio4: gpio@e6054000 { 227 compatible = "renesas,gpio-r8a77995", 228 "renesas,rcar-gen3-gpio", 229 "renesas,gpio-rcar"; 230 reg = <0 0xe6054000 0 0x50>; 231 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 232 #gpio-cells = <2>; 233 gpio-controller; 234 gpio-ranges = <&pfc 0 128 32>; 235 #interrupt-cells = <2>; 236 interrupt-controller; 237 clocks = <&cpg CPG_MOD 908>; 238 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 239 resets = <&cpg 908>; 240 }; 241 242 gpio5: gpio@e6055000 { 243 compatible = "renesas,gpio-r8a77995", 244 "renesas,rcar-gen3-gpio", 245 "renesas,gpio-rcar"; 246 reg = <0 0xe6055000 0 0x50>; 247 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 248 #gpio-cells = <2>; 249 gpio-controller; 250 gpio-ranges = <&pfc 0 160 21>; 251 #interrupt-cells = <2>; 252 interrupt-controller; 253 clocks = <&cpg CPG_MOD 907>; 254 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 255 resets = <&cpg 907>; 256 }; 257 258 gpio6: gpio@e6055400 { 259 compatible = "renesas,gpio-r8a77995", 260 "renesas,rcar-gen3-gpio", 261 "renesas,gpio-rcar"; 262 reg = <0 0xe6055400 0 0x50>; 263 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 264 #gpio-cells = <2>; 265 gpio-controller; 266 gpio-ranges = <&pfc 0 192 14>; 267 #interrupt-cells = <2>; 268 interrupt-controller; 269 clocks = <&cpg CPG_MOD 906>; 270 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 271 resets = <&cpg 906>; 272 }; 273 274 avb: ethernet@e6800000 { 275 compatible = "renesas,etheravb-r8a77995", 276 "renesas,etheravb-rcar-gen3"; 277 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 278 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 303 interrupt-names = "ch0", "ch1", "ch2", "ch3", 304 "ch4", "ch5", "ch6", "ch7", 305 "ch8", "ch9", "ch10", "ch11", 306 "ch12", "ch13", "ch14", "ch15", 307 "ch16", "ch17", "ch18", "ch19", 308 "ch20", "ch21", "ch22", "ch23", 309 "ch24"; 310 clocks = <&cpg CPG_MOD 812>; 311 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 312 resets = <&cpg 812>; 313 phy-mode = "rgmii-txid"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 status = "disabled"; 317 }; 318 319 scif2: serial@e6e88000 { 320 compatible = "renesas,scif-r8a77995", 321 "renesas,rcar-gen3-scif", "renesas,scif"; 322 reg = <0 0xe6e88000 0 64>; 323 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&cpg CPG_MOD 310>, 325 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 326 <&scif_clk>; 327 clock-names = "fck", "brg_int", "scif_clk"; 328 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 329 resets = <&cpg 310>; 330 status = "disabled"; 331 }; 332 333 pwm0: pwm@e6e30000 { 334 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 335 reg = <0 0xe6e30000 0 0x8>; 336 #pwm-cells = <2>; 337 clocks = <&cpg CPG_MOD 523>; 338 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 339 resets = <&cpg 523>; 340 status = "disabled"; 341 }; 342 343 pwm1: pwm@e6e31000 { 344 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 345 reg = <0 0xe6e31000 0 0x8>; 346 #pwm-cells = <2>; 347 clocks = <&cpg CPG_MOD 523>; 348 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 349 resets = <&cpg 523>; 350 status = "disabled"; 351 }; 352 353 pwm2: pwm@e6e32000 { 354 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 355 reg = <0 0xe6e32000 0 0x8>; 356 #pwm-cells = <2>; 357 clocks = <&cpg CPG_MOD 523>; 358 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 359 resets = <&cpg 523>; 360 status = "disabled"; 361 }; 362 363 pwm3: pwm@e6e33000 { 364 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 365 reg = <0 0xe6e33000 0 0x8>; 366 #pwm-cells = <2>; 367 clocks = <&cpg CPG_MOD 523>; 368 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 369 resets = <&cpg 523>; 370 status = "disabled"; 371 }; 372 373 ehci0: usb@ee080100 { 374 compatible = "generic-ehci"; 375 reg = <0 0xee080100 0 0x100>; 376 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cpg CPG_MOD 703>; 378 phys = <&usb2_phy0>; 379 phy-names = "usb"; 380 companion = <&ohci0>; 381 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 382 resets = <&cpg 703>; 383 status = "disabled"; 384 }; 385 386 ohci0: usb@ee080000 { 387 compatible = "generic-ohci"; 388 reg = <0 0xee080000 0 0x100>; 389 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cpg CPG_MOD 703>; 391 phys = <&usb2_phy0>; 392 phy-names = "usb"; 393 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 394 resets = <&cpg 703>; 395 status = "disabled"; 396 }; 397 398 usb2_phy0: usb-phy@ee080200 { 399 compatible = "renesas,usb2-phy-r8a77995", 400 "renesas,rcar-gen3-usb2-phy"; 401 reg = <0 0xee080200 0 0x700>; 402 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&cpg CPG_MOD 703>; 404 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 405 resets = <&cpg 703>; 406 #phy-cells = <0>; 407 status = "disabled"; 408 }; 409 }; 410}; 411