1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the r8a77990 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r8a77990"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 /* 1 core only at this point */ 21 a53_0: cpu@0 { 22 compatible = "arm,cortex-a53", "arm,armv8"; 23 reg = <0x0>; 24 device_type = "cpu"; 25 power-domains = <&sysc 5>; 26 next-level-cache = <&L2_CA53>; 27 enable-method = "psci"; 28 }; 29 30 L2_CA53: cache-controller@0 { 31 compatible = "cache"; 32 reg = <0>; 33 power-domains = <&sysc 21>; 34 cache-unified; 35 cache-level = <2>; 36 }; 37 }; 38 39 extal_clk: extal { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 /* This value must be overridden by the board */ 43 clock-frequency = <0>; 44 }; 45 46 psci { 47 compatible = "arm,psci-0.2"; 48 method = "smc"; 49 }; 50 51 soc: soc { 52 compatible = "simple-bus"; 53 interrupt-parent = <&gic>; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 ranges; 57 58 gic: interrupt-controller@f1010000 { 59 compatible = "arm,gic-400"; 60 #interrupt-cells = <3>; 61 #address-cells = <0>; 62 interrupt-controller; 63 reg = <0x0 0xf1010000 0 0x1000>, 64 <0x0 0xf1020000 0 0x20000>, 65 <0x0 0xf1040000 0 0x20000>, 66 <0x0 0xf1060000 0 0x20000>; 67 interrupts = <GIC_PPI 9 68 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 69 clocks = <&cpg CPG_MOD 408>; 70 clock-names = "clk"; 71 power-domains = <&sysc 32>; 72 resets = <&cpg 408>; 73 }; 74 75 timer { 76 compatible = "arm,armv8-timer"; 77 interrupts = <GIC_PPI 13 78 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 14 80 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 11 82 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 83 <GIC_PPI 10 84 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 85 }; 86 87 pmu_a53 { 88 compatible = "arm,cortex-a53-pmu"; 89 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 90 interrupt-affinity = <&a53_0>; 91 }; 92 93 cpg: clock-controller@e6150000 { 94 compatible = "renesas,r8a77990-cpg-mssr"; 95 reg = <0 0xe6150000 0 0x1000>; 96 clocks = <&extal_clk>; 97 clock-names = "extal"; 98 #clock-cells = <2>; 99 #power-domain-cells = <0>; 100 #reset-cells = <1>; 101 }; 102 103 rst: reset-controller@e6160000 { 104 compatible = "renesas,r8a77990-rst"; 105 reg = <0 0xe6160000 0 0x0200>; 106 }; 107 108 prr: chipid@fff00044 { 109 compatible = "renesas,prr"; 110 reg = <0 0xfff00044 0 4>; 111 }; 112 113 sysc: system-controller@e6180000 { 114 compatible = "renesas,r8a77990-sysc"; 115 reg = <0 0xe6180000 0 0x0400>; 116 #power-domain-cells = <1>; 117 }; 118 119 scif2: serial@e6e88000 { 120 compatible = "renesas,scif-r8a77990", 121 "renesas,rcar-gen3-scif", "renesas,scif"; 122 reg = <0 0xe6e88000 0 64>; 123 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&cpg CPG_MOD 310>; 125 clock-names = "fck"; 126 power-domains = <&sysc 32>; 127 resets = <&cpg 310>; 128 status = "disabled"; 129 }; 130 }; 131}; 132