1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77970 SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77970-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/power/r8a77970-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77970"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 a53_0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53", "arm,armv8"; 34 reg = <0>; 35 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 36 power-domains = <&sysc R8A77970_PD_CA53_CPU0>; 37 next-level-cache = <&L2_CA53>; 38 enable-method = "psci"; 39 }; 40 41 a53_1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53", "arm,armv8"; 44 reg = <1>; 45 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 46 power-domains = <&sysc R8A77970_PD_CA53_CPU1>; 47 next-level-cache = <&L2_CA53>; 48 enable-method = "psci"; 49 }; 50 51 L2_CA53: cache-controller { 52 compatible = "cache"; 53 power-domains = <&sysc R8A77970_PD_CA53_SCU>; 54 cache-unified; 55 cache-level = <2>; 56 }; 57 }; 58 59 extal_clk: extal { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 /* This value must be overridden by the board */ 63 clock-frequency = <0>; 64 }; 65 66 extalr_clk: extalr { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 /* This value must be overridden by the board */ 70 clock-frequency = <0>; 71 }; 72 73 pmu_a53 { 74 compatible = "arm,cortex-a53-pmu"; 75 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 76 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-affinity = <&a53_0>, <&a53_1>; 78 }; 79 80 psci { 81 compatible = "arm,psci-1.0", "arm,psci-0.2"; 82 method = "smc"; 83 }; 84 85 /* External CAN clock - to be overridden by boards that provide it */ 86 can_clk: can { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency = <0>; 90 }; 91 92 /* External SCIF clock - to be overridden by boards that provide it */ 93 scif_clk: scif { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <0>; 97 }; 98 99 soc: soc { 100 compatible = "simple-bus"; 101 interrupt-parent = <&gic>; 102 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 107 rwdt: watchdog@e6020000 { 108 compatible = "renesas,r8a77970-wdt", 109 "renesas,rcar-gen3-wdt"; 110 reg = <0 0xe6020000 0 0x0c>; 111 clocks = <&cpg CPG_MOD 402>; 112 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 113 resets = <&cpg 402>; 114 status = "disabled"; 115 }; 116 117 gpio0: gpio@e6050000 { 118 compatible = "renesas,gpio-r8a77970", 119 "renesas,rcar-gen3-gpio"; 120 reg = <0 0xe6050000 0 0x50>; 121 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 122 #gpio-cells = <2>; 123 gpio-controller; 124 gpio-ranges = <&pfc 0 0 22>; 125 #interrupt-cells = <2>; 126 interrupt-controller; 127 clocks = <&cpg CPG_MOD 912>; 128 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 129 resets = <&cpg 912>; 130 }; 131 132 gpio1: gpio@e6051000 { 133 compatible = "renesas,gpio-r8a77970", 134 "renesas,rcar-gen3-gpio"; 135 reg = <0 0xe6051000 0 0x50>; 136 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 137 #gpio-cells = <2>; 138 gpio-controller; 139 gpio-ranges = <&pfc 0 32 28>; 140 #interrupt-cells = <2>; 141 interrupt-controller; 142 clocks = <&cpg CPG_MOD 911>; 143 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 144 resets = <&cpg 911>; 145 }; 146 147 gpio2: gpio@e6052000 { 148 compatible = "renesas,gpio-r8a77970", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6052000 0 0x50>; 151 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 64 17>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 910>; 158 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 159 resets = <&cpg 910>; 160 }; 161 162 gpio3: gpio@e6053000 { 163 compatible = "renesas,gpio-r8a77970", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6053000 0 0x50>; 166 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 96 17>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 909>; 173 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 174 resets = <&cpg 909>; 175 }; 176 177 gpio4: gpio@e6054000 { 178 compatible = "renesas,gpio-r8a77970", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6054000 0 0x50>; 181 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 128 6>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 908>; 188 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 189 resets = <&cpg 908>; 190 }; 191 192 gpio5: gpio@e6055000 { 193 compatible = "renesas,gpio-r8a77970", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6055000 0 0x50>; 196 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 160 15>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 907>; 203 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 204 resets = <&cpg 907>; 205 }; 206 207 pfc: pin-controller@e6060000 { 208 compatible = "renesas,pfc-r8a77970"; 209 reg = <0 0xe6060000 0 0x504>; 210 }; 211 212 cpg: clock-controller@e6150000 { 213 compatible = "renesas,r8a77970-cpg-mssr"; 214 reg = <0 0xe6150000 0 0x1000>; 215 clocks = <&extal_clk>, <&extalr_clk>; 216 clock-names = "extal", "extalr"; 217 #clock-cells = <2>; 218 #power-domain-cells = <0>; 219 #reset-cells = <1>; 220 }; 221 222 rst: reset-controller@e6160000 { 223 compatible = "renesas,r8a77970-rst"; 224 reg = <0 0xe6160000 0 0x200>; 225 }; 226 227 sysc: system-controller@e6180000 { 228 compatible = "renesas,r8a77970-sysc"; 229 reg = <0 0xe6180000 0 0x440>; 230 #power-domain-cells = <1>; 231 }; 232 233 intc_ex: interrupt-controller@e61c0000 { 234 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 235 #interrupt-cells = <2>; 236 interrupt-controller; 237 reg = <0 0xe61c0000 0 0x200>; 238 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 239 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 240 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 241 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 242 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 243 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cpg CPG_MOD 407>; 245 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 246 resets = <&cpg 407>; 247 }; 248 249 i2c0: i2c@e6500000 { 250 compatible = "renesas,i2c-r8a77970", 251 "renesas,rcar-gen3-i2c"; 252 reg = <0 0xe6500000 0 0x40>; 253 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cpg CPG_MOD 931>; 255 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 256 resets = <&cpg 931>; 257 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 258 <&dmac2 0x91>, <&dmac2 0x90>; 259 dma-names = "tx", "rx", "tx", "rx"; 260 i2c-scl-internal-delay-ns = <6>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 status = "disabled"; 264 }; 265 266 i2c1: i2c@e6508000 { 267 compatible = "renesas,i2c-r8a77970", 268 "renesas,rcar-gen3-i2c"; 269 reg = <0 0xe6508000 0 0x40>; 270 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&cpg CPG_MOD 930>; 272 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 273 resets = <&cpg 930>; 274 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 275 <&dmac2 0x93>, <&dmac2 0x92>; 276 dma-names = "tx", "rx", "tx", "rx"; 277 i2c-scl-internal-delay-ns = <6>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 status = "disabled"; 281 }; 282 283 i2c2: i2c@e6510000 { 284 compatible = "renesas,i2c-r8a77970", 285 "renesas,rcar-gen3-i2c"; 286 reg = <0 0xe6510000 0 0x40>; 287 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&cpg CPG_MOD 929>; 289 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 290 resets = <&cpg 929>; 291 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 292 <&dmac2 0x95>, <&dmac2 0x94>; 293 dma-names = "tx", "rx", "tx", "rx"; 294 i2c-scl-internal-delay-ns = <6>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 status = "disabled"; 298 }; 299 300 i2c3: i2c@e66d0000 { 301 compatible = "renesas,i2c-r8a77970", 302 "renesas,rcar-gen3-i2c"; 303 reg = <0 0xe66d0000 0 0x40>; 304 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cpg CPG_MOD 928>; 306 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 307 resets = <&cpg 928>; 308 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 309 <&dmac2 0x97>, <&dmac2 0x96>; 310 dma-names = "tx", "rx", "tx", "rx"; 311 i2c-scl-internal-delay-ns = <6>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 status = "disabled"; 315 }; 316 317 i2c4: i2c@e66d8000 { 318 compatible = "renesas,i2c-r8a77970", 319 "renesas,rcar-gen3-i2c"; 320 reg = <0 0xe66d8000 0 0x40>; 321 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cpg CPG_MOD 927>; 323 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 324 resets = <&cpg 927>; 325 dmas = <&dmac1 0x99>, <&dmac1 0x98>, 326 <&dmac2 0x99>, <&dmac2 0x98>; 327 dma-names = "tx", "rx", "tx", "rx"; 328 i2c-scl-internal-delay-ns = <6>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 status = "disabled"; 332 }; 333 334 hscif0: serial@e6540000 { 335 compatible = "renesas,hscif-r8a77970", 336 "renesas,rcar-gen3-hscif", 337 "renesas,hscif"; 338 reg = <0 0xe6540000 0 96>; 339 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 520>, 341 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 342 <&scif_clk>; 343 clock-names = "fck", "brg_int", "scif_clk"; 344 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 345 <&dmac2 0x31>, <&dmac2 0x30>; 346 dma-names = "tx", "rx", "tx", "rx"; 347 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 348 resets = <&cpg 520>; 349 status = "disabled"; 350 }; 351 352 hscif1: serial@e6550000 { 353 compatible = "renesas,hscif-r8a77970", 354 "renesas,rcar-gen3-hscif", 355 "renesas,hscif"; 356 reg = <0 0xe6550000 0 96>; 357 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cpg CPG_MOD 519>, 359 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 360 <&scif_clk>; 361 clock-names = "fck", "brg_int", "scif_clk"; 362 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 363 <&dmac2 0x33>, <&dmac2 0x32>; 364 dma-names = "tx", "rx", "tx", "rx"; 365 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 366 resets = <&cpg 519>; 367 status = "disabled"; 368 }; 369 370 hscif2: serial@e6560000 { 371 compatible = "renesas,hscif-r8a77970", 372 "renesas,rcar-gen3-hscif", 373 "renesas,hscif"; 374 reg = <0 0xe6560000 0 96>; 375 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cpg CPG_MOD 518>, 377 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 378 <&scif_clk>; 379 clock-names = "fck", "brg_int", "scif_clk"; 380 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 381 <&dmac2 0x35>, <&dmac2 0x34>; 382 dma-names = "tx", "rx", "tx", "rx"; 383 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 384 resets = <&cpg 518>; 385 status = "disabled"; 386 }; 387 388 hscif3: serial@e66a0000 { 389 compatible = "renesas,hscif-r8a77970", 390 "renesas,rcar-gen3-hscif", "renesas,hscif"; 391 reg = <0 0xe66a0000 0 96>; 392 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cpg CPG_MOD 517>, 394 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 395 <&scif_clk>; 396 clock-names = "fck", "brg_int", "scif_clk"; 397 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 398 <&dmac2 0x37>, <&dmac2 0x36>; 399 dma-names = "tx", "rx", "tx", "rx"; 400 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 401 resets = <&cpg 517>; 402 status = "disabled"; 403 }; 404 405 canfd: can@e66c0000 { 406 compatible = "renesas,r8a77970-canfd", 407 "renesas,rcar-gen3-canfd"; 408 reg = <0 0xe66c0000 0 0x8000>; 409 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&cpg CPG_MOD 914>, 412 <&cpg CPG_CORE R8A77970_CLK_CANFD>, 413 <&can_clk>; 414 clock-names = "fck", "canfd", "can_clk"; 415 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; 416 assigned-clock-rates = <40000000>; 417 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 418 resets = <&cpg 914>; 419 status = "disabled"; 420 421 channel0 { 422 status = "disabled"; 423 }; 424 425 channel1 { 426 status = "disabled"; 427 }; 428 }; 429 430 avb: ethernet@e6800000 { 431 compatible = "renesas,etheravb-r8a77970", 432 "renesas,etheravb-rcar-gen3"; 433 reg = <0 0xe6800000 0 0x800>; 434 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 459 interrupt-names = "ch0", "ch1", "ch2", "ch3", 460 "ch4", "ch5", "ch6", "ch7", 461 "ch8", "ch9", "ch10", "ch11", 462 "ch12", "ch13", "ch14", "ch15", 463 "ch16", "ch17", "ch18", "ch19", 464 "ch20", "ch21", "ch22", "ch23", 465 "ch24"; 466 clocks = <&cpg CPG_MOD 812>; 467 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 468 resets = <&cpg 812>; 469 phy-mode = "rgmii"; 470 iommus = <&ipmmu_rt 3>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disabled"; 474 }; 475 476 scif0: serial@e6e60000 { 477 compatible = "renesas,scif-r8a77970", 478 "renesas,rcar-gen3-scif", 479 "renesas,scif"; 480 reg = <0 0xe6e60000 0 64>; 481 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cpg CPG_MOD 207>, 483 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 484 <&scif_clk>; 485 clock-names = "fck", "brg_int", "scif_clk"; 486 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 487 <&dmac2 0x51>, <&dmac2 0x50>; 488 dma-names = "tx", "rx", "tx", "rx"; 489 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 490 resets = <&cpg 207>; 491 status = "disabled"; 492 }; 493 494 scif1: serial@e6e68000 { 495 compatible = "renesas,scif-r8a77970", 496 "renesas,rcar-gen3-scif", 497 "renesas,scif"; 498 reg = <0 0xe6e68000 0 64>; 499 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cpg CPG_MOD 206>, 501 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 502 <&scif_clk>; 503 clock-names = "fck", "brg_int", "scif_clk"; 504 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 505 <&dmac2 0x53>, <&dmac2 0x52>; 506 dma-names = "tx", "rx", "tx", "rx"; 507 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 508 resets = <&cpg 206>; 509 status = "disabled"; 510 }; 511 512 scif3: serial@e6c50000 { 513 compatible = "renesas,scif-r8a77970", 514 "renesas,rcar-gen3-scif", 515 "renesas,scif"; 516 reg = <0 0xe6c50000 0 64>; 517 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cpg CPG_MOD 204>, 519 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 520 <&scif_clk>; 521 clock-names = "fck", "brg_int", "scif_clk"; 522 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 523 <&dmac2 0x57>, <&dmac2 0x56>; 524 dma-names = "tx", "rx", "tx", "rx"; 525 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 526 resets = <&cpg 204>; 527 status = "disabled"; 528 }; 529 530 scif4: serial@e6c40000 { 531 compatible = "renesas,scif-r8a77970", 532 "renesas,rcar-gen3-scif", "renesas,scif"; 533 reg = <0 0xe6c40000 0 64>; 534 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&cpg CPG_MOD 203>, 536 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 537 <&scif_clk>; 538 clock-names = "fck", "brg_int", "scif_clk"; 539 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 540 <&dmac2 0x59>, <&dmac2 0x58>; 541 dma-names = "tx", "rx", "tx", "rx"; 542 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 543 resets = <&cpg 203>; 544 status = "disabled"; 545 }; 546 547 548 vin0: video@e6ef0000 { 549 compatible = "renesas,vin-r8a77970"; 550 reg = <0 0xe6ef0000 0 0x1000>; 551 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cpg CPG_MOD 811>; 553 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 554 resets = <&cpg 811>; 555 renesas,id = <0>; 556 status = "disabled"; 557 558 ports { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 562 port@1 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 566 reg = <1>; 567 568 vin0csi40: endpoint@2 { 569 reg = <2>; 570 remote-endpoint= <&csi40vin0>; 571 }; 572 }; 573 }; 574 }; 575 576 vin1: video@e6ef1000 { 577 compatible = "renesas,vin-r8a77970"; 578 reg = <0 0xe6ef1000 0 0x1000>; 579 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&cpg CPG_MOD 810>; 581 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 582 resets = <&cpg 810>; 583 renesas,id = <1>; 584 status = "disabled"; 585 586 ports { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 590 port@1 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 594 reg = <1>; 595 596 vin1csi40: endpoint@2 { 597 reg = <2>; 598 remote-endpoint= <&csi40vin1>; 599 }; 600 }; 601 }; 602 }; 603 604 vin2: video@e6ef2000 { 605 compatible = "renesas,vin-r8a77970"; 606 reg = <0 0xe6ef2000 0 0x1000>; 607 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&cpg CPG_MOD 809>; 609 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 610 resets = <&cpg 809>; 611 renesas,id = <2>; 612 status = "disabled"; 613 614 ports { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 618 port@1 { 619 #address-cells = <1>; 620 #size-cells = <0>; 621 622 reg = <1>; 623 624 vin2csi40: endpoint@2 { 625 reg = <2>; 626 remote-endpoint= <&csi40vin2>; 627 }; 628 }; 629 }; 630 }; 631 632 vin3: video@e6ef3000 { 633 compatible = "renesas,vin-r8a77970"; 634 reg = <0 0xe6ef3000 0 0x1000>; 635 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&cpg CPG_MOD 808>; 637 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 638 resets = <&cpg 808>; 639 renesas,id = <3>; 640 status = "disabled"; 641 642 ports { 643 #address-cells = <1>; 644 #size-cells = <0>; 645 646 port@1 { 647 #address-cells = <1>; 648 #size-cells = <0>; 649 650 reg = <1>; 651 652 vin3csi40: endpoint@2 { 653 reg = <2>; 654 remote-endpoint= <&csi40vin3>; 655 }; 656 }; 657 }; 658 }; 659 660 dmac1: dma-controller@e7300000 { 661 compatible = "renesas,dmac-r8a77970", 662 "renesas,rcar-dmac"; 663 reg = <0 0xe7300000 0 0x10000>; 664 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 665 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 666 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 667 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 668 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 669 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 670 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 671 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 672 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 673 interrupt-names = "error", 674 "ch0", "ch1", "ch2", "ch3", 675 "ch4", "ch5", "ch6", "ch7"; 676 clocks = <&cpg CPG_MOD 218>; 677 clock-names = "fck"; 678 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 679 resets = <&cpg 218>; 680 #dma-cells = <1>; 681 dma-channels = <8>; 682 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 683 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 684 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 685 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 686 }; 687 688 dmac2: dma-controller@e7310000 { 689 compatible = "renesas,dmac-r8a77970", 690 "renesas,rcar-dmac"; 691 reg = <0 0xe7310000 0 0x10000>; 692 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 693 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 694 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 695 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 696 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 697 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 698 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 699 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 700 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "error", 702 "ch0", "ch1", "ch2", "ch3", 703 "ch4", "ch5", "ch6", "ch7"; 704 clocks = <&cpg CPG_MOD 217>; 705 clock-names = "fck"; 706 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 707 resets = <&cpg 217>; 708 #dma-cells = <1>; 709 dma-channels = <8>; 710 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 711 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 712 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 713 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 714 }; 715 716 ipmmu_ds1: mmu@e7740000 { 717 compatible = "renesas,ipmmu-r8a77970"; 718 reg = <0 0xe7740000 0 0x1000>; 719 renesas,ipmmu-main = <&ipmmu_mm 0>; 720 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 721 #iommu-cells = <1>; 722 }; 723 724 ipmmu_ir: mmu@ff8b0000 { 725 compatible = "renesas,ipmmu-r8a77970"; 726 reg = <0 0xff8b0000 0 0x1000>; 727 renesas,ipmmu-main = <&ipmmu_mm 3>; 728 power-domains = <&sysc R8A77970_PD_A3IR>; 729 #iommu-cells = <1>; 730 }; 731 732 ipmmu_mm: mmu@e67b0000 { 733 compatible = "renesas,ipmmu-r8a77970"; 734 reg = <0 0xe67b0000 0 0x1000>; 735 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 737 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 738 #iommu-cells = <1>; 739 }; 740 741 ipmmu_rt: mmu@ffc80000 { 742 compatible = "renesas,ipmmu-r8a77970"; 743 reg = <0 0xffc80000 0 0x1000>; 744 renesas,ipmmu-main = <&ipmmu_mm 7>; 745 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 746 #iommu-cells = <1>; 747 }; 748 749 ipmmu_vi0: mmu@febd0000 { 750 compatible = "renesas,ipmmu-r8a77970"; 751 reg = <0 0xfebd0000 0 0x1000>; 752 renesas,ipmmu-main = <&ipmmu_mm 9>; 753 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 754 #iommu-cells = <1>; 755 }; 756 757 gic: interrupt-controller@f1010000 { 758 compatible = "arm,gic-400"; 759 #interrupt-cells = <3>; 760 #address-cells = <0>; 761 interrupt-controller; 762 reg = <0 0xf1010000 0 0x1000>, 763 <0 0xf1020000 0 0x20000>, 764 <0 0xf1040000 0 0x20000>, 765 <0 0xf1060000 0 0x20000>; 766 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 767 IRQ_TYPE_LEVEL_HIGH)>; 768 clocks = <&cpg CPG_MOD 408>; 769 clock-names = "clk"; 770 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 771 resets = <&cpg 408>; 772 }; 773 774 vspd0: vsp@fea20000 { 775 compatible = "renesas,vsp2"; 776 reg = <0 0xfea20000 0 0x5000>; 777 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&cpg CPG_MOD 623>; 779 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 780 resets = <&cpg 623>; 781 renesas,fcp = <&fcpvd0>; 782 }; 783 784 fcpvd0: fcp@fea27000 { 785 compatible = "renesas,fcpv"; 786 reg = <0 0xfea27000 0 0x200>; 787 clocks = <&cpg CPG_MOD 603>; 788 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 789 resets = <&cpg 603>; 790 }; 791 792 csi40: csi2@feaa0000 { 793 compatible = "renesas,r8a77970-csi2"; 794 reg = <0 0xfeaa0000 0 0x10000>; 795 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 716>; 797 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 798 resets = <&cpg 716>; 799 status = "disabled"; 800 801 ports { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 805 port@1 { 806 #address-cells = <1>; 807 #size-cells = <0>; 808 809 reg = <1>; 810 811 csi40vin0: endpoint@0 { 812 reg = <0>; 813 remote-endpoint = <&vin0csi40>; 814 }; 815 csi40vin1: endpoint@1 { 816 reg = <1>; 817 remote-endpoint = <&vin1csi40>; 818 }; 819 csi40vin2: endpoint@2 { 820 reg = <2>; 821 remote-endpoint = <&vin2csi40>; 822 }; 823 csi40vin3: endpoint@3 { 824 reg = <3>; 825 remote-endpoint = <&vin3csi40>; 826 }; 827 }; 828 }; 829 }; 830 831 du: display@feb00000 { 832 compatible = "renesas,du-r8a77970"; 833 reg = <0 0xfeb00000 0 0x80000>; 834 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&cpg CPG_MOD 724>; 836 clock-names = "du.0"; 837 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 838 resets = <&cpg 724>; 839 vsps = <&vspd0>; 840 status = "disabled"; 841 842 ports { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 846 port@0 { 847 reg = <0>; 848 du_out_rgb: endpoint { 849 }; 850 }; 851 852 port@1 { 853 reg = <1>; 854 du_out_lvds0: endpoint { 855 remote-endpoint = <&lvds0_in>; 856 }; 857 }; 858 }; 859 }; 860 861 lvds0: lvds-encoder@feb90000 { 862 compatible = "renesas,r8a77970-lvds"; 863 reg = <0 0xfeb90000 0 0x14>; 864 clocks = <&cpg CPG_MOD 727>; 865 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 866 resets = <&cpg 727>; 867 status = "disabled"; 868 869 ports { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 port@0 { 874 reg = <0>; 875 lvds0_in: endpoint { 876 remote-endpoint = 877 <&du_out_lvds0>; 878 }; 879 }; 880 port@1 { 881 reg = <1>; 882 lvds0_out: endpoint { 883 }; 884 }; 885 }; 886 }; 887 888 prr: chipid@fff00044 { 889 compatible = "renesas,prr"; 890 reg = <0 0xfff00044 0 4>; 891 }; 892 }; 893 894 timer { 895 compatible = "arm,armv8-timer"; 896 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 897 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 898 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 899 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 900 }; 901}; 902