1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a7796 SoC 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a7796-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a7796-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a7796"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 i2c6 = &i2c6; 27 i2c7 = &i2c_dvfs; 28 }; 29 30 /* 31 * The external audio clocks are configured as 0 Hz fixed frequency 32 * clocks by default. 33 * Boards that provide audio clocks should override them. 34 */ 35 audio_clk_a: audio_clk_a { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <0>; 39 }; 40 41 audio_clk_b: audio_clk_b { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 audio_clk_c: audio_clk_c { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <0>; 51 }; 52 53 /* External CAN clock - to be overridden by boards that provide it */ 54 can_clk: can { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <0>; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 a57_0: cpu@0 { 65 compatible = "arm,cortex-a57", "arm,armv8"; 66 reg = <0x0>; 67 device_type = "cpu"; 68 power-domains = <&sysc R8A7796_PD_CA57_CPU0>; 69 next-level-cache = <&L2_CA57>; 70 enable-method = "psci"; 71 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; 72 operating-points-v2 = <&cluster0_opp>; 73 #cooling-cells = <2>; 74 }; 75 76 a57_1: cpu@1 { 77 compatible = "arm,cortex-a57","arm,armv8"; 78 reg = <0x1>; 79 device_type = "cpu"; 80 power-domains = <&sysc R8A7796_PD_CA57_CPU1>; 81 next-level-cache = <&L2_CA57>; 82 enable-method = "psci"; 83 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; 84 operating-points-v2 = <&cluster0_opp>; 85 #cooling-cells = <2>; 86 }; 87 88 a53_0: cpu@100 { 89 compatible = "arm,cortex-a53", "arm,armv8"; 90 reg = <0x100>; 91 device_type = "cpu"; 92 power-domains = <&sysc R8A7796_PD_CA53_CPU0>; 93 next-level-cache = <&L2_CA53>; 94 enable-method = "psci"; 95 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; 96 operating-points-v2 = <&cluster1_opp>; 97 }; 98 99 a53_1: cpu@101 { 100 compatible = "arm,cortex-a53","arm,armv8"; 101 reg = <0x101>; 102 device_type = "cpu"; 103 power-domains = <&sysc R8A7796_PD_CA53_CPU1>; 104 next-level-cache = <&L2_CA53>; 105 enable-method = "psci"; 106 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; 107 operating-points-v2 = <&cluster1_opp>; 108 }; 109 110 a53_2: cpu@102 { 111 compatible = "arm,cortex-a53","arm,armv8"; 112 reg = <0x102>; 113 device_type = "cpu"; 114 power-domains = <&sysc R8A7796_PD_CA53_CPU2>; 115 next-level-cache = <&L2_CA53>; 116 enable-method = "psci"; 117 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; 118 operating-points-v2 = <&cluster1_opp>; 119 }; 120 121 a53_3: cpu@103 { 122 compatible = "arm,cortex-a53","arm,armv8"; 123 reg = <0x103>; 124 device_type = "cpu"; 125 power-domains = <&sysc R8A7796_PD_CA53_CPU3>; 126 next-level-cache = <&L2_CA53>; 127 enable-method = "psci"; 128 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; 129 operating-points-v2 = <&cluster1_opp>; 130 }; 131 132 L2_CA57: cache-controller-0 { 133 compatible = "cache"; 134 power-domains = <&sysc R8A7796_PD_CA57_SCU>; 135 cache-unified; 136 cache-level = <2>; 137 }; 138 139 L2_CA53: cache-controller-1 { 140 compatible = "cache"; 141 power-domains = <&sysc R8A7796_PD_CA53_SCU>; 142 cache-unified; 143 cache-level = <2>; 144 }; 145 }; 146 147 extal_clk: extal { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 /* This value must be overridden by the board */ 151 clock-frequency = <0>; 152 }; 153 154 extalr_clk: extalr { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 /* This value must be overridden by the board */ 158 clock-frequency = <0>; 159 }; 160 161 cluster0_opp: opp_table0 { 162 compatible = "operating-points-v2"; 163 opp-shared; 164 165 opp-500000000 { 166 opp-hz = /bits/ 64 <500000000>; 167 opp-microvolt = <820000>; 168 clock-latency-ns = <300000>; 169 }; 170 opp-1000000000 { 171 opp-hz = /bits/ 64 <1000000000>; 172 opp-microvolt = <820000>; 173 clock-latency-ns = <300000>; 174 }; 175 opp-1500000000 { 176 opp-hz = /bits/ 64 <1500000000>; 177 opp-microvolt = <820000>; 178 clock-latency-ns = <300000>; 179 }; 180 opp-1600000000 { 181 opp-hz = /bits/ 64 <1600000000>; 182 opp-microvolt = <900000>; 183 clock-latency-ns = <300000>; 184 turbo-mode; 185 }; 186 opp-1700000000 { 187 opp-hz = /bits/ 64 <1700000000>; 188 opp-microvolt = <900000>; 189 clock-latency-ns = <300000>; 190 turbo-mode; 191 }; 192 opp-1800000000 { 193 opp-hz = /bits/ 64 <1800000000>; 194 opp-microvolt = <960000>; 195 clock-latency-ns = <300000>; 196 turbo-mode; 197 }; 198 }; 199 200 cluster1_opp: opp_table1 { 201 compatible = "operating-points-v2"; 202 opp-shared; 203 204 opp-800000000 { 205 opp-hz = /bits/ 64 <800000000>; 206 opp-microvolt = <820000>; 207 clock-latency-ns = <300000>; 208 }; 209 opp-1000000000 { 210 opp-hz = /bits/ 64 <1000000000>; 211 opp-microvolt = <820000>; 212 clock-latency-ns = <300000>; 213 }; 214 opp-1200000000 { 215 opp-hz = /bits/ 64 <1200000000>; 216 opp-microvolt = <820000>; 217 clock-latency-ns = <300000>; 218 }; 219 opp-1300000000 { 220 opp-hz = /bits/ 64 <1300000000>; 221 opp-microvolt = <820000>; 222 clock-latency-ns = <300000>; 223 turbo-mode; 224 }; 225 }; 226 227 /* External PCIe clock - can be overridden by the board */ 228 pcie_bus_clk: pcie_bus { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <0>; 232 }; 233 234 pmu_a57 { 235 compatible = "arm,cortex-a57-pmu"; 236 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 237 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-affinity = <&a57_0>, <&a57_1>; 239 }; 240 241 pmu_a53 { 242 compatible = "arm,cortex-a53-pmu"; 243 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 244 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 245 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 246 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 247 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 248 }; 249 250 psci { 251 compatible = "arm,psci-1.0", "arm,psci-0.2"; 252 method = "smc"; 253 }; 254 255 /* External SCIF clock - to be overridden by boards that provide it */ 256 scif_clk: scif { 257 compatible = "fixed-clock"; 258 #clock-cells = <0>; 259 clock-frequency = <0>; 260 }; 261 262 soc { 263 compatible = "simple-bus"; 264 interrupt-parent = <&gic>; 265 #address-cells = <2>; 266 #size-cells = <2>; 267 ranges; 268 269 gic: interrupt-controller@f1010000 { 270 compatible = "arm,gic-400"; 271 #interrupt-cells = <3>; 272 #address-cells = <0>; 273 interrupt-controller; 274 reg = <0x0 0xf1010000 0 0x1000>, 275 <0x0 0xf1020000 0 0x20000>, 276 <0x0 0xf1040000 0 0x20000>, 277 <0x0 0xf1060000 0 0x20000>; 278 interrupts = <GIC_PPI 9 279 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 280 clocks = <&cpg CPG_MOD 408>; 281 clock-names = "clk"; 282 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 283 resets = <&cpg 408>; 284 }; 285 286 wdt0: watchdog@e6020000 { 287 compatible = "renesas,r8a7796-wdt", 288 "renesas,rcar-gen3-wdt"; 289 reg = <0 0xe6020000 0 0x0c>; 290 clocks = <&cpg CPG_MOD 402>; 291 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 292 resets = <&cpg 402>; 293 status = "disabled"; 294 }; 295 296 gpio0: gpio@e6050000 { 297 compatible = "renesas,gpio-r8a7796", 298 "renesas,rcar-gen3-gpio"; 299 reg = <0 0xe6050000 0 0x50>; 300 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 301 #gpio-cells = <2>; 302 gpio-controller; 303 gpio-ranges = <&pfc 0 0 16>; 304 #interrupt-cells = <2>; 305 interrupt-controller; 306 clocks = <&cpg CPG_MOD 912>; 307 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 308 resets = <&cpg 912>; 309 }; 310 311 gpio1: gpio@e6051000 { 312 compatible = "renesas,gpio-r8a7796", 313 "renesas,rcar-gen3-gpio"; 314 reg = <0 0xe6051000 0 0x50>; 315 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 316 #gpio-cells = <2>; 317 gpio-controller; 318 gpio-ranges = <&pfc 0 32 29>; 319 #interrupt-cells = <2>; 320 interrupt-controller; 321 clocks = <&cpg CPG_MOD 911>; 322 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 323 resets = <&cpg 911>; 324 }; 325 326 gpio2: gpio@e6052000 { 327 compatible = "renesas,gpio-r8a7796", 328 "renesas,rcar-gen3-gpio"; 329 reg = <0 0xe6052000 0 0x50>; 330 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 331 #gpio-cells = <2>; 332 gpio-controller; 333 gpio-ranges = <&pfc 0 64 15>; 334 #interrupt-cells = <2>; 335 interrupt-controller; 336 clocks = <&cpg CPG_MOD 910>; 337 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 338 resets = <&cpg 910>; 339 }; 340 341 gpio3: gpio@e6053000 { 342 compatible = "renesas,gpio-r8a7796", 343 "renesas,rcar-gen3-gpio"; 344 reg = <0 0xe6053000 0 0x50>; 345 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 346 #gpio-cells = <2>; 347 gpio-controller; 348 gpio-ranges = <&pfc 0 96 16>; 349 #interrupt-cells = <2>; 350 interrupt-controller; 351 clocks = <&cpg CPG_MOD 909>; 352 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 353 resets = <&cpg 909>; 354 }; 355 356 gpio4: gpio@e6054000 { 357 compatible = "renesas,gpio-r8a7796", 358 "renesas,rcar-gen3-gpio"; 359 reg = <0 0xe6054000 0 0x50>; 360 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 361 #gpio-cells = <2>; 362 gpio-controller; 363 gpio-ranges = <&pfc 0 128 18>; 364 #interrupt-cells = <2>; 365 interrupt-controller; 366 clocks = <&cpg CPG_MOD 908>; 367 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 368 resets = <&cpg 908>; 369 }; 370 371 gpio5: gpio@e6055000 { 372 compatible = "renesas,gpio-r8a7796", 373 "renesas,rcar-gen3-gpio"; 374 reg = <0 0xe6055000 0 0x50>; 375 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 376 #gpio-cells = <2>; 377 gpio-controller; 378 gpio-ranges = <&pfc 0 160 26>; 379 #interrupt-cells = <2>; 380 interrupt-controller; 381 clocks = <&cpg CPG_MOD 907>; 382 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 383 resets = <&cpg 907>; 384 }; 385 386 gpio6: gpio@e6055400 { 387 compatible = "renesas,gpio-r8a7796", 388 "renesas,rcar-gen3-gpio"; 389 reg = <0 0xe6055400 0 0x50>; 390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 391 #gpio-cells = <2>; 392 gpio-controller; 393 gpio-ranges = <&pfc 0 192 32>; 394 #interrupt-cells = <2>; 395 interrupt-controller; 396 clocks = <&cpg CPG_MOD 906>; 397 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 398 resets = <&cpg 906>; 399 }; 400 401 gpio7: gpio@e6055800 { 402 compatible = "renesas,gpio-r8a7796", 403 "renesas,rcar-gen3-gpio"; 404 reg = <0 0xe6055800 0 0x50>; 405 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 406 #gpio-cells = <2>; 407 gpio-controller; 408 gpio-ranges = <&pfc 0 224 4>; 409 #interrupt-cells = <2>; 410 interrupt-controller; 411 clocks = <&cpg CPG_MOD 905>; 412 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 413 resets = <&cpg 905>; 414 }; 415 416 pfc: pin-controller@e6060000 { 417 compatible = "renesas,pfc-r8a7796"; 418 reg = <0 0xe6060000 0 0x50c>; 419 }; 420 421 ipmmu_vi0: mmu@febd0000 { 422 compatible = "renesas,ipmmu-r8a7796"; 423 reg = <0 0xfebd0000 0 0x1000>; 424 renesas,ipmmu-main = <&ipmmu_mm 9>; 425 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 426 #iommu-cells = <1>; 427 }; 428 429 ipmmu_vc0: mmu@fe6b0000 { 430 compatible = "renesas,ipmmu-r8a7796"; 431 reg = <0 0xfe6b0000 0 0x1000>; 432 renesas,ipmmu-main = <&ipmmu_mm 8>; 433 power-domains = <&sysc R8A7796_PD_A3VC>; 434 #iommu-cells = <1>; 435 status = "disabled"; 436 }; 437 438 ipmmu_pv0: mmu@fd800000 { 439 compatible = "renesas,ipmmu-r8a7796"; 440 reg = <0 0xfd800000 0 0x1000>; 441 renesas,ipmmu-main = <&ipmmu_mm 5>; 442 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 443 #iommu-cells = <1>; 444 }; 445 446 ipmmu_pv1: mmu@fd950000 { 447 compatible = "renesas,ipmmu-r8a7796"; 448 reg = <0 0xfd950000 0 0x1000>; 449 renesas,ipmmu-main = <&ipmmu_mm 6>; 450 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 451 #iommu-cells = <1>; 452 status = "disabled"; 453 }; 454 455 ipmmu_ir: mmu@ff8b0000 { 456 compatible = "renesas,ipmmu-r8a7796"; 457 reg = <0 0xff8b0000 0 0x1000>; 458 renesas,ipmmu-main = <&ipmmu_mm 3>; 459 power-domains = <&sysc R8A7796_PD_A3IR>; 460 #iommu-cells = <1>; 461 status = "disabled"; 462 }; 463 464 ipmmu_hc: mmu@e6570000 { 465 compatible = "renesas,ipmmu-r8a7796"; 466 reg = <0 0xe6570000 0 0x1000>; 467 renesas,ipmmu-main = <&ipmmu_mm 2>; 468 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 469 #iommu-cells = <1>; 470 status = "disabled"; 471 }; 472 473 ipmmu_rt: mmu@ffc80000 { 474 compatible = "renesas,ipmmu-r8a7796"; 475 reg = <0 0xffc80000 0 0x1000>; 476 renesas,ipmmu-main = <&ipmmu_mm 7>; 477 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 478 #iommu-cells = <1>; 479 status = "disabled"; 480 }; 481 482 ipmmu_mp: mmu@ec670000 { 483 compatible = "renesas,ipmmu-r8a7796"; 484 reg = <0 0xec670000 0 0x1000>; 485 renesas,ipmmu-main = <&ipmmu_mm 4>; 486 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 487 #iommu-cells = <1>; 488 }; 489 490 ipmmu_ds0: mmu@e6740000 { 491 compatible = "renesas,ipmmu-r8a7796"; 492 reg = <0 0xe6740000 0 0x1000>; 493 renesas,ipmmu-main = <&ipmmu_mm 0>; 494 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 495 #iommu-cells = <1>; 496 }; 497 498 ipmmu_ds1: mmu@e7740000 { 499 compatible = "renesas,ipmmu-r8a7796"; 500 reg = <0 0xe7740000 0 0x1000>; 501 renesas,ipmmu-main = <&ipmmu_mm 1>; 502 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 503 #iommu-cells = <1>; 504 }; 505 506 ipmmu_mm: mmu@e67b0000 { 507 compatible = "renesas,ipmmu-r8a7796"; 508 reg = <0 0xe67b0000 0 0x1000>; 509 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 511 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 512 #iommu-cells = <1>; 513 }; 514 515 cpg: clock-controller@e6150000 { 516 compatible = "renesas,r8a7796-cpg-mssr"; 517 reg = <0 0xe6150000 0 0x1000>; 518 clocks = <&extal_clk>, <&extalr_clk>; 519 clock-names = "extal", "extalr"; 520 #clock-cells = <2>; 521 #power-domain-cells = <0>; 522 #reset-cells = <1>; 523 }; 524 525 rst: reset-controller@e6160000 { 526 compatible = "renesas,r8a7796-rst"; 527 reg = <0 0xe6160000 0 0x0200>; 528 }; 529 530 prr: chipid@fff00044 { 531 compatible = "renesas,prr"; 532 reg = <0 0xfff00044 0 4>; 533 }; 534 535 sysc: system-controller@e6180000 { 536 compatible = "renesas,r8a7796-sysc"; 537 reg = <0 0xe6180000 0 0x0400>; 538 #power-domain-cells = <1>; 539 }; 540 541 intc_ex: interrupt-controller@e61c0000 { 542 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; 543 #interrupt-cells = <2>; 544 interrupt-controller; 545 reg = <0 0xe61c0000 0 0x200>; 546 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 547 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 548 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 549 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 550 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 551 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cpg CPG_MOD 407>; 553 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 554 resets = <&cpg 407>; 555 }; 556 557 i2c_dvfs: i2c@e60b0000 { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 compatible = "renesas,iic-r8a7796", 561 "renesas,rcar-gen3-iic", 562 "renesas,rmobile-iic"; 563 reg = <0 0xe60b0000 0 0x425>; 564 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cpg CPG_MOD 926>; 566 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 567 resets = <&cpg 926>; 568 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 569 dma-names = "tx", "rx"; 570 status = "disabled"; 571 }; 572 573 pwm0: pwm@e6e30000 { 574 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; 575 reg = <0 0xe6e30000 0 8>; 576 #pwm-cells = <2>; 577 clocks = <&cpg CPG_MOD 523>; 578 resets = <&cpg 523>; 579 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 580 status = "disabled"; 581 }; 582 583 pwm1: pwm@e6e31000 { 584 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; 585 reg = <0 0xe6e31000 0 8>; 586 #pwm-cells = <2>; 587 clocks = <&cpg CPG_MOD 523>; 588 resets = <&cpg 523>; 589 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 590 status = "disabled"; 591 }; 592 593 pwm2: pwm@e6e32000 { 594 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; 595 reg = <0 0xe6e32000 0 8>; 596 #pwm-cells = <2>; 597 clocks = <&cpg CPG_MOD 523>; 598 resets = <&cpg 523>; 599 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 600 status = "disabled"; 601 }; 602 603 pwm3: pwm@e6e33000 { 604 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; 605 reg = <0 0xe6e33000 0 8>; 606 #pwm-cells = <2>; 607 clocks = <&cpg CPG_MOD 523>; 608 resets = <&cpg 523>; 609 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 610 status = "disabled"; 611 }; 612 613 pwm4: pwm@e6e34000 { 614 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; 615 reg = <0 0xe6e34000 0 8>; 616 #pwm-cells = <2>; 617 clocks = <&cpg CPG_MOD 523>; 618 resets = <&cpg 523>; 619 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 620 status = "disabled"; 621 }; 622 623 pwm5: pwm@e6e35000 { 624 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; 625 reg = <0 0xe6e35000 0 8>; 626 #pwm-cells = <2>; 627 clocks = <&cpg CPG_MOD 523>; 628 resets = <&cpg 523>; 629 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 630 status = "disabled"; 631 }; 632 633 pwm6: pwm@e6e36000 { 634 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; 635 reg = <0 0xe6e36000 0 8>; 636 #pwm-cells = <2>; 637 clocks = <&cpg CPG_MOD 523>; 638 resets = <&cpg 523>; 639 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 640 status = "disabled"; 641 }; 642 643 i2c0: i2c@e6500000 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 compatible = "renesas,i2c-r8a7796", 647 "renesas,rcar-gen3-i2c"; 648 reg = <0 0xe6500000 0 0x40>; 649 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 931>; 651 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 652 resets = <&cpg 931>; 653 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 654 <&dmac2 0x91>, <&dmac2 0x90>; 655 dma-names = "tx", "rx", "tx", "rx"; 656 i2c-scl-internal-delay-ns = <110>; 657 status = "disabled"; 658 }; 659 660 i2c1: i2c@e6508000 { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 compatible = "renesas,i2c-r8a7796", 664 "renesas,rcar-gen3-i2c"; 665 reg = <0 0xe6508000 0 0x40>; 666 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cpg CPG_MOD 930>; 668 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 669 resets = <&cpg 930>; 670 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 671 <&dmac2 0x93>, <&dmac2 0x92>; 672 dma-names = "tx", "rx", "tx", "rx"; 673 i2c-scl-internal-delay-ns = <6>; 674 status = "disabled"; 675 }; 676 677 i2c2: i2c@e6510000 { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 compatible = "renesas,i2c-r8a7796", 681 "renesas,rcar-gen3-i2c"; 682 reg = <0 0xe6510000 0 0x40>; 683 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cpg CPG_MOD 929>; 685 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 686 resets = <&cpg 929>; 687 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 688 <&dmac2 0x95>, <&dmac2 0x94>; 689 dma-names = "tx", "rx", "tx", "rx"; 690 i2c-scl-internal-delay-ns = <6>; 691 status = "disabled"; 692 }; 693 694 i2c3: i2c@e66d0000 { 695 #address-cells = <1>; 696 #size-cells = <0>; 697 compatible = "renesas,i2c-r8a7796", 698 "renesas,rcar-gen3-i2c"; 699 reg = <0 0xe66d0000 0 0x40>; 700 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cpg CPG_MOD 928>; 702 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 703 resets = <&cpg 928>; 704 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 705 dma-names = "tx", "rx"; 706 i2c-scl-internal-delay-ns = <110>; 707 status = "disabled"; 708 }; 709 710 i2c4: i2c@e66d8000 { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 compatible = "renesas,i2c-r8a7796", 714 "renesas,rcar-gen3-i2c"; 715 reg = <0 0xe66d8000 0 0x40>; 716 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cpg CPG_MOD 927>; 718 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 719 resets = <&cpg 927>; 720 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 721 dma-names = "tx", "rx"; 722 i2c-scl-internal-delay-ns = <110>; 723 status = "disabled"; 724 }; 725 726 i2c5: i2c@e66e0000 { 727 #address-cells = <1>; 728 #size-cells = <0>; 729 compatible = "renesas,i2c-r8a7796", 730 "renesas,rcar-gen3-i2c"; 731 reg = <0 0xe66e0000 0 0x40>; 732 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cpg CPG_MOD 919>; 734 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 735 resets = <&cpg 919>; 736 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 737 dma-names = "tx", "rx"; 738 i2c-scl-internal-delay-ns = <110>; 739 status = "disabled"; 740 }; 741 742 i2c6: i2c@e66e8000 { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 compatible = "renesas,i2c-r8a7796", 746 "renesas,rcar-gen3-i2c"; 747 reg = <0 0xe66e8000 0 0x40>; 748 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cpg CPG_MOD 918>; 750 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 751 resets = <&cpg 918>; 752 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 753 dma-names = "tx", "rx"; 754 i2c-scl-internal-delay-ns = <6>; 755 status = "disabled"; 756 }; 757 758 can0: can@e6c30000 { 759 compatible = "renesas,can-r8a7796", 760 "renesas,rcar-gen3-can"; 761 reg = <0 0xe6c30000 0 0x1000>; 762 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&cpg CPG_MOD 916>, 764 <&cpg CPG_CORE R8A7796_CLK_CANFD>, 765 <&can_clk>; 766 clock-names = "clkp1", "clkp2", "can_clk"; 767 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; 768 assigned-clock-rates = <40000000>; 769 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 770 resets = <&cpg 916>; 771 status = "disabled"; 772 }; 773 774 can1: can@e6c38000 { 775 compatible = "renesas,can-r8a7796", 776 "renesas,rcar-gen3-can"; 777 reg = <0 0xe6c38000 0 0x1000>; 778 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&cpg CPG_MOD 915>, 780 <&cpg CPG_CORE R8A7796_CLK_CANFD>, 781 <&can_clk>; 782 clock-names = "clkp1", "clkp2", "can_clk"; 783 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; 784 assigned-clock-rates = <40000000>; 785 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 786 resets = <&cpg 915>; 787 status = "disabled"; 788 }; 789 790 canfd: can@e66c0000 { 791 compatible = "renesas,r8a7796-canfd", 792 "renesas,rcar-gen3-canfd"; 793 reg = <0 0xe66c0000 0 0x8000>; 794 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 914>, 797 <&cpg CPG_CORE R8A7796_CLK_CANFD>, 798 <&can_clk>; 799 clock-names = "fck", "canfd", "can_clk"; 800 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; 801 assigned-clock-rates = <40000000>; 802 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 803 resets = <&cpg 914>; 804 status = "disabled"; 805 806 channel0 { 807 status = "disabled"; 808 }; 809 810 channel1 { 811 status = "disabled"; 812 }; 813 }; 814 815 drif00: rif@e6f40000 { 816 compatible = "renesas,r8a7796-drif", 817 "renesas,rcar-gen3-drif"; 818 reg = <0 0xe6f40000 0 0x64>; 819 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&cpg CPG_MOD 515>; 821 clock-names = "fck"; 822 dmas = <&dmac1 0x20>, <&dmac2 0x20>; 823 dma-names = "rx", "rx"; 824 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 825 resets = <&cpg 515>; 826 renesas,bonding = <&drif01>; 827 status = "disabled"; 828 }; 829 830 drif01: rif@e6f50000 { 831 compatible = "renesas,r8a7796-drif", 832 "renesas,rcar-gen3-drif"; 833 reg = <0 0xe6f50000 0 0x64>; 834 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&cpg CPG_MOD 514>; 836 clock-names = "fck"; 837 dmas = <&dmac1 0x22>, <&dmac2 0x22>; 838 dma-names = "rx", "rx"; 839 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 840 resets = <&cpg 514>; 841 renesas,bonding = <&drif00>; 842 status = "disabled"; 843 }; 844 845 drif10: rif@e6f60000 { 846 compatible = "renesas,r8a7796-drif", 847 "renesas,rcar-gen3-drif"; 848 reg = <0 0xe6f60000 0 0x64>; 849 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&cpg CPG_MOD 513>; 851 clock-names = "fck"; 852 dmas = <&dmac1 0x24>, <&dmac2 0x24>; 853 dma-names = "rx", "rx"; 854 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 855 resets = <&cpg 513>; 856 renesas,bonding = <&drif11>; 857 status = "disabled"; 858 }; 859 860 drif11: rif@e6f70000 { 861 compatible = "renesas,r8a7796-drif", 862 "renesas,rcar-gen3-drif"; 863 reg = <0 0xe6f70000 0 0x64>; 864 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&cpg CPG_MOD 512>; 866 clock-names = "fck"; 867 dmas = <&dmac1 0x26>, <&dmac2 0x26>; 868 dma-names = "rx", "rx"; 869 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 870 resets = <&cpg 512>; 871 renesas,bonding = <&drif10>; 872 status = "disabled"; 873 }; 874 875 drif20: rif@e6f80000 { 876 compatible = "renesas,r8a7796-drif", 877 "renesas,rcar-gen3-drif"; 878 reg = <0 0xe6f80000 0 0x64>; 879 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&cpg CPG_MOD 511>; 881 clock-names = "fck"; 882 dmas = <&dmac1 0x28>, <&dmac2 0x28>; 883 dma-names = "rx", "rx"; 884 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 885 resets = <&cpg 511>; 886 renesas,bonding = <&drif21>; 887 status = "disabled"; 888 }; 889 890 drif21: rif@e6f90000 { 891 compatible = "renesas,r8a7796-drif", 892 "renesas,rcar-gen3-drif"; 893 reg = <0 0xe6f90000 0 0x64>; 894 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&cpg CPG_MOD 510>; 896 clock-names = "fck"; 897 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; 898 dma-names = "rx", "rx"; 899 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 900 resets = <&cpg 510>; 901 renesas,bonding = <&drif20>; 902 status = "disabled"; 903 }; 904 905 drif30: rif@e6fa0000 { 906 compatible = "renesas,r8a7796-drif", 907 "renesas,rcar-gen3-drif"; 908 reg = <0 0xe6fa0000 0 0x64>; 909 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&cpg CPG_MOD 509>; 911 clock-names = "fck"; 912 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; 913 dma-names = "rx", "rx"; 914 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 915 resets = <&cpg 509>; 916 renesas,bonding = <&drif31>; 917 status = "disabled"; 918 }; 919 920 drif31: rif@e6fb0000 { 921 compatible = "renesas,r8a7796-drif", 922 "renesas,rcar-gen3-drif"; 923 reg = <0 0xe6fb0000 0 0x64>; 924 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&cpg CPG_MOD 508>; 926 clock-names = "fck"; 927 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; 928 dma-names = "rx", "rx"; 929 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 930 resets = <&cpg 508>; 931 renesas,bonding = <&drif30>; 932 status = "disabled"; 933 }; 934 935 avb: ethernet@e6800000 { 936 compatible = "renesas,etheravb-r8a7796", 937 "renesas,etheravb-rcar-gen3"; 938 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 939 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 964 interrupt-names = "ch0", "ch1", "ch2", "ch3", 965 "ch4", "ch5", "ch6", "ch7", 966 "ch8", "ch9", "ch10", "ch11", 967 "ch12", "ch13", "ch14", "ch15", 968 "ch16", "ch17", "ch18", "ch19", 969 "ch20", "ch21", "ch22", "ch23", 970 "ch24"; 971 clocks = <&cpg CPG_MOD 812>; 972 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 973 resets = <&cpg 812>; 974 phy-mode = "rgmii"; 975 iommus = <&ipmmu_ds0 16>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 status = "disabled"; 979 }; 980 981 hscif0: serial@e6540000 { 982 compatible = "renesas,hscif-r8a7796", 983 "renesas,rcar-gen3-hscif", 984 "renesas,hscif"; 985 reg = <0 0xe6540000 0 0x60>; 986 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&cpg CPG_MOD 520>, 988 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 989 <&scif_clk>; 990 clock-names = "fck", "brg_int", "scif_clk"; 991 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 992 <&dmac2 0x31>, <&dmac2 0x30>; 993 dma-names = "tx", "rx", "tx", "rx"; 994 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 995 resets = <&cpg 520>; 996 status = "disabled"; 997 }; 998 999 hscif1: serial@e6550000 { 1000 compatible = "renesas,hscif-r8a7796", 1001 "renesas,rcar-gen3-hscif", 1002 "renesas,hscif"; 1003 reg = <0 0xe6550000 0 0x60>; 1004 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&cpg CPG_MOD 519>, 1006 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1007 <&scif_clk>; 1008 clock-names = "fck", "brg_int", "scif_clk"; 1009 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 1010 <&dmac2 0x33>, <&dmac2 0x32>; 1011 dma-names = "tx", "rx", "tx", "rx"; 1012 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1013 resets = <&cpg 519>; 1014 status = "disabled"; 1015 }; 1016 1017 hscif2: serial@e6560000 { 1018 compatible = "renesas,hscif-r8a7796", 1019 "renesas,rcar-gen3-hscif", 1020 "renesas,hscif"; 1021 reg = <0 0xe6560000 0 0x60>; 1022 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cpg CPG_MOD 518>, 1024 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1025 <&scif_clk>; 1026 clock-names = "fck", "brg_int", "scif_clk"; 1027 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 1028 <&dmac2 0x35>, <&dmac2 0x34>; 1029 dma-names = "tx", "rx", "tx", "rx"; 1030 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1031 resets = <&cpg 518>; 1032 status = "disabled"; 1033 }; 1034 1035 hscif3: serial@e66a0000 { 1036 compatible = "renesas,hscif-r8a7796", 1037 "renesas,rcar-gen3-hscif", 1038 "renesas,hscif"; 1039 reg = <0 0xe66a0000 0 0x60>; 1040 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&cpg CPG_MOD 517>, 1042 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1043 <&scif_clk>; 1044 clock-names = "fck", "brg_int", "scif_clk"; 1045 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 1046 dma-names = "tx", "rx"; 1047 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1048 resets = <&cpg 517>; 1049 status = "disabled"; 1050 }; 1051 1052 hscif4: serial@e66b0000 { 1053 compatible = "renesas,hscif-r8a7796", 1054 "renesas,rcar-gen3-hscif", 1055 "renesas,hscif"; 1056 reg = <0 0xe66b0000 0 0x60>; 1057 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&cpg CPG_MOD 516>, 1059 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1060 <&scif_clk>; 1061 clock-names = "fck", "brg_int", "scif_clk"; 1062 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 1063 dma-names = "tx", "rx"; 1064 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1065 resets = <&cpg 516>; 1066 status = "disabled"; 1067 }; 1068 1069 scif0: serial@e6e60000 { 1070 compatible = "renesas,scif-r8a7796", 1071 "renesas,rcar-gen3-scif", "renesas,scif"; 1072 reg = <0 0xe6e60000 0 64>; 1073 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&cpg CPG_MOD 207>, 1075 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1076 <&scif_clk>; 1077 clock-names = "fck", "brg_int", "scif_clk"; 1078 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1079 <&dmac2 0x51>, <&dmac2 0x50>; 1080 dma-names = "tx", "rx", "tx", "rx"; 1081 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1082 resets = <&cpg 207>; 1083 status = "disabled"; 1084 }; 1085 1086 scif1: serial@e6e68000 { 1087 compatible = "renesas,scif-r8a7796", 1088 "renesas,rcar-gen3-scif", "renesas,scif"; 1089 reg = <0 0xe6e68000 0 64>; 1090 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&cpg CPG_MOD 206>, 1092 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1093 <&scif_clk>; 1094 clock-names = "fck", "brg_int", "scif_clk"; 1095 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1096 <&dmac2 0x53>, <&dmac2 0x52>; 1097 dma-names = "tx", "rx", "tx", "rx"; 1098 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1099 resets = <&cpg 206>; 1100 status = "disabled"; 1101 }; 1102 1103 scif2: serial@e6e88000 { 1104 compatible = "renesas,scif-r8a7796", 1105 "renesas,rcar-gen3-scif", "renesas,scif"; 1106 reg = <0 0xe6e88000 0 64>; 1107 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&cpg CPG_MOD 310>, 1109 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1110 <&scif_clk>; 1111 clock-names = "fck", "brg_int", "scif_clk"; 1112 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1113 resets = <&cpg 310>; 1114 status = "disabled"; 1115 }; 1116 1117 scif3: serial@e6c50000 { 1118 compatible = "renesas,scif-r8a7796", 1119 "renesas,rcar-gen3-scif", "renesas,scif"; 1120 reg = <0 0xe6c50000 0 64>; 1121 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&cpg CPG_MOD 204>, 1123 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1124 <&scif_clk>; 1125 clock-names = "fck", "brg_int", "scif_clk"; 1126 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1127 dma-names = "tx", "rx"; 1128 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1129 resets = <&cpg 204>; 1130 status = "disabled"; 1131 }; 1132 1133 scif4: serial@e6c40000 { 1134 compatible = "renesas,scif-r8a7796", 1135 "renesas,rcar-gen3-scif", "renesas,scif"; 1136 reg = <0 0xe6c40000 0 64>; 1137 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&cpg CPG_MOD 203>, 1139 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1140 <&scif_clk>; 1141 clock-names = "fck", "brg_int", "scif_clk"; 1142 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1143 dma-names = "tx", "rx"; 1144 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1145 resets = <&cpg 203>; 1146 status = "disabled"; 1147 }; 1148 1149 scif5: serial@e6f30000 { 1150 compatible = "renesas,scif-r8a7796", 1151 "renesas,rcar-gen3-scif", "renesas,scif"; 1152 reg = <0 0xe6f30000 0 64>; 1153 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&cpg CPG_MOD 202>, 1155 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1156 <&scif_clk>; 1157 clock-names = "fck", "brg_int", "scif_clk"; 1158 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1159 <&dmac2 0x5b>, <&dmac2 0x5a>; 1160 dma-names = "tx", "rx", "tx", "rx"; 1161 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1162 resets = <&cpg 202>; 1163 status = "disabled"; 1164 }; 1165 1166 msiof0: spi@e6e90000 { 1167 compatible = "renesas,msiof-r8a7796", 1168 "renesas,rcar-gen3-msiof"; 1169 reg = <0 0xe6e90000 0 0x0064>; 1170 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&cpg CPG_MOD 211>; 1172 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1173 <&dmac2 0x41>, <&dmac2 0x40>; 1174 dma-names = "tx", "rx", "tx", "rx"; 1175 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1176 resets = <&cpg 211>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 status = "disabled"; 1180 }; 1181 1182 msiof1: spi@e6ea0000 { 1183 compatible = "renesas,msiof-r8a7796", 1184 "renesas,rcar-gen3-msiof"; 1185 reg = <0 0xe6ea0000 0 0x0064>; 1186 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&cpg CPG_MOD 210>; 1188 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1189 <&dmac2 0x43>, <&dmac2 0x42>; 1190 dma-names = "tx", "rx", "tx", "rx"; 1191 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1192 resets = <&cpg 210>; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 status = "disabled"; 1196 }; 1197 1198 msiof2: spi@e6c00000 { 1199 compatible = "renesas,msiof-r8a7796", 1200 "renesas,rcar-gen3-msiof"; 1201 reg = <0 0xe6c00000 0 0x0064>; 1202 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&cpg CPG_MOD 209>; 1204 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1205 dma-names = "tx", "rx"; 1206 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1207 resets = <&cpg 209>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 status = "disabled"; 1211 }; 1212 1213 msiof3: spi@e6c10000 { 1214 compatible = "renesas,msiof-r8a7796", 1215 "renesas,rcar-gen3-msiof"; 1216 reg = <0 0xe6c10000 0 0x0064>; 1217 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&cpg CPG_MOD 208>; 1219 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1220 dma-names = "tx", "rx"; 1221 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1222 resets = <&cpg 208>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 status = "disabled"; 1226 }; 1227 1228 dmac0: dma-controller@e6700000 { 1229 compatible = "renesas,dmac-r8a7796", 1230 "renesas,rcar-dmac"; 1231 reg = <0 0xe6700000 0 0x10000>; 1232 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 1233 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 1234 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 1235 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 1236 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 1237 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 1238 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 1239 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 1240 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 1241 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 1242 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 1243 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 1244 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 1245 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 1246 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 1247 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 1248 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1249 interrupt-names = "error", 1250 "ch0", "ch1", "ch2", "ch3", 1251 "ch4", "ch5", "ch6", "ch7", 1252 "ch8", "ch9", "ch10", "ch11", 1253 "ch12", "ch13", "ch14", "ch15"; 1254 clocks = <&cpg CPG_MOD 219>; 1255 clock-names = "fck"; 1256 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1257 resets = <&cpg 219>; 1258 #dma-cells = <1>; 1259 dma-channels = <16>; 1260 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1261 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1262 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1263 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1264 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1265 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1266 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1267 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1268 }; 1269 1270 dmac1: dma-controller@e7300000 { 1271 compatible = "renesas,dmac-r8a7796", 1272 "renesas,rcar-dmac"; 1273 reg = <0 0xe7300000 0 0x10000>; 1274 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 1275 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 1276 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 1277 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 1278 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 1279 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 1280 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 1281 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 1282 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 1283 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 1284 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 1285 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 1286 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 1287 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 1288 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 1289 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 1290 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 1291 interrupt-names = "error", 1292 "ch0", "ch1", "ch2", "ch3", 1293 "ch4", "ch5", "ch6", "ch7", 1294 "ch8", "ch9", "ch10", "ch11", 1295 "ch12", "ch13", "ch14", "ch15"; 1296 clocks = <&cpg CPG_MOD 218>; 1297 clock-names = "fck"; 1298 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1299 resets = <&cpg 218>; 1300 #dma-cells = <1>; 1301 dma-channels = <16>; 1302 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1303 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1304 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1305 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1306 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1307 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1308 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1309 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1310 }; 1311 1312 dmac2: dma-controller@e7310000 { 1313 compatible = "renesas,dmac-r8a7796", 1314 "renesas,rcar-dmac"; 1315 reg = <0 0xe7310000 0 0x10000>; 1316 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 1317 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 1318 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 1319 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 1320 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 1321 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 1322 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 1323 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 1324 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 1325 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 1326 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 1327 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 1328 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 1329 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 1330 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 1331 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 1332 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1333 interrupt-names = "error", 1334 "ch0", "ch1", "ch2", "ch3", 1335 "ch4", "ch5", "ch6", "ch7", 1336 "ch8", "ch9", "ch10", "ch11", 1337 "ch12", "ch13", "ch14", "ch15"; 1338 clocks = <&cpg CPG_MOD 217>; 1339 clock-names = "fck"; 1340 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1341 resets = <&cpg 217>; 1342 #dma-cells = <1>; 1343 dma-channels = <16>; 1344 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1345 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1346 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1347 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1348 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1349 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1350 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1351 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1352 }; 1353 1354 audma0: dma-controller@ec700000 { 1355 compatible = "renesas,dmac-r8a7796", 1356 "renesas,rcar-dmac"; 1357 reg = <0 0xec700000 0 0x10000>; 1358 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1359 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1360 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1361 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1362 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1363 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1364 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1365 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1366 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1367 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1368 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1369 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1370 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1371 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1372 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1373 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1374 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1375 interrupt-names = "error", 1376 "ch0", "ch1", "ch2", "ch3", 1377 "ch4", "ch5", "ch6", "ch7", 1378 "ch8", "ch9", "ch10", "ch11", 1379 "ch12", "ch13", "ch14", "ch15"; 1380 clocks = <&cpg CPG_MOD 502>; 1381 clock-names = "fck"; 1382 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1383 resets = <&cpg 502>; 1384 #dma-cells = <1>; 1385 dma-channels = <16>; 1386 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1387 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1388 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1389 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1390 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1391 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1392 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1393 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1394 }; 1395 1396 audma1: dma-controller@ec720000 { 1397 compatible = "renesas,dmac-r8a7796", 1398 "renesas,rcar-dmac"; 1399 reg = <0 0xec720000 0 0x10000>; 1400 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1401 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1402 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1403 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1404 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1405 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1406 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 1407 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 1408 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 1409 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 1410 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 1411 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 1412 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 1413 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 1414 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 1415 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 1416 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1417 interrupt-names = "error", 1418 "ch0", "ch1", "ch2", "ch3", 1419 "ch4", "ch5", "ch6", "ch7", 1420 "ch8", "ch9", "ch10", "ch11", 1421 "ch12", "ch13", "ch14", "ch15"; 1422 clocks = <&cpg CPG_MOD 501>; 1423 clock-names = "fck"; 1424 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1425 resets = <&cpg 501>; 1426 #dma-cells = <1>; 1427 dma-channels = <16>; 1428 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1429 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1430 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1431 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1432 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1433 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1434 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1435 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1436 }; 1437 1438 usb_dmac0: dma-controller@e65a0000 { 1439 compatible = "renesas,r8a7796-usb-dmac", 1440 "renesas,usb-dmac"; 1441 reg = <0 0xe65a0000 0 0x100>; 1442 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 1443 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1444 interrupt-names = "ch0", "ch1"; 1445 clocks = <&cpg CPG_MOD 330>; 1446 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1447 resets = <&cpg 330>; 1448 #dma-cells = <1>; 1449 dma-channels = <2>; 1450 }; 1451 1452 usb_dmac1: dma-controller@e65b0000 { 1453 compatible = "renesas,r8a7796-usb-dmac", 1454 "renesas,usb-dmac"; 1455 reg = <0 0xe65b0000 0 0x100>; 1456 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 1457 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1458 interrupt-names = "ch0", "ch1"; 1459 clocks = <&cpg CPG_MOD 331>; 1460 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1461 resets = <&cpg 331>; 1462 #dma-cells = <1>; 1463 dma-channels = <2>; 1464 }; 1465 1466 hsusb: usb@e6590000 { 1467 compatible = "renesas,usbhs-r8a7796", 1468 "renesas,rcar-gen3-usbhs"; 1469 reg = <0 0xe6590000 0 0x100>; 1470 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1471 clocks = <&cpg CPG_MOD 704>; 1472 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 1473 <&usb_dmac1 0>, <&usb_dmac1 1>; 1474 dma-names = "ch0", "ch1", "ch2", "ch3"; 1475 renesas,buswait = <11>; 1476 phys = <&usb2_phy0>; 1477 phy-names = "usb"; 1478 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1479 resets = <&cpg 704>; 1480 status = "disabled"; 1481 }; 1482 1483 usb3_phy0: usb-phy@e65ee000 { 1484 compatible = "renesas,r8a7796-usb3-phy", 1485 "renesas,rcar-gen3-usb3-phy"; 1486 reg = <0 0xe65ee000 0 0x90>; 1487 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 1488 <&usb_extal_clk>; 1489 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 1490 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1491 resets = <&cpg 328>; 1492 #phy-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 xhci0: usb@ee000000 { 1497 compatible = "renesas,xhci-r8a7796", 1498 "renesas,rcar-gen3-xhci"; 1499 reg = <0 0xee000000 0 0xc00>; 1500 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1501 clocks = <&cpg CPG_MOD 328>; 1502 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1503 resets = <&cpg 328>; 1504 status = "disabled"; 1505 }; 1506 1507 usb3_peri0: usb@ee020000 { 1508 compatible = "renesas,r8a7796-usb3-peri", 1509 "renesas,rcar-gen3-usb3-peri"; 1510 reg = <0 0xee020000 0 0x400>; 1511 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1512 clocks = <&cpg CPG_MOD 328>; 1513 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1514 resets = <&cpg 328>; 1515 status = "disabled"; 1516 }; 1517 1518 ohci0: usb@ee080000 { 1519 compatible = "generic-ohci"; 1520 reg = <0 0xee080000 0 0x100>; 1521 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1522 clocks = <&cpg CPG_MOD 703>; 1523 phys = <&usb2_phy0>; 1524 phy-names = "usb"; 1525 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1526 resets = <&cpg 703>; 1527 status = "disabled"; 1528 }; 1529 1530 ehci0: usb@ee080100 { 1531 compatible = "generic-ehci"; 1532 reg = <0 0xee080100 0 0x100>; 1533 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1534 clocks = <&cpg CPG_MOD 703>; 1535 phys = <&usb2_phy0>; 1536 phy-names = "usb"; 1537 companion= <&ohci0>; 1538 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1539 resets = <&cpg 703>; 1540 status = "disabled"; 1541 }; 1542 1543 usb2_phy0: usb-phy@ee080200 { 1544 compatible = "renesas,usb2-phy-r8a7796", 1545 "renesas,rcar-gen3-usb2-phy"; 1546 reg = <0 0xee080200 0 0x700>; 1547 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&cpg CPG_MOD 703>; 1549 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1550 resets = <&cpg 703>; 1551 #phy-cells = <0>; 1552 status = "disabled"; 1553 }; 1554 1555 ohci1: usb@ee0a0000 { 1556 compatible = "generic-ohci"; 1557 reg = <0 0xee0a0000 0 0x100>; 1558 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1559 clocks = <&cpg CPG_MOD 702>; 1560 phys = <&usb2_phy1>; 1561 phy-names = "usb"; 1562 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1563 resets = <&cpg 702>; 1564 status = "disabled"; 1565 }; 1566 1567 ehci1: usb@ee0a0100 { 1568 compatible = "generic-ehci"; 1569 reg = <0 0xee0a0100 0 0x100>; 1570 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1571 clocks = <&cpg CPG_MOD 702>; 1572 phys = <&usb2_phy1>; 1573 phy-names = "usb"; 1574 companion= <&ohci1>; 1575 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1576 resets = <&cpg 702>; 1577 status = "disabled"; 1578 }; 1579 1580 usb2_phy1: usb-phy@ee0a0200 { 1581 compatible = "renesas,usb2-phy-r8a7796", 1582 "renesas,rcar-gen3-usb2-phy"; 1583 reg = <0 0xee0a0200 0 0x700>; 1584 clocks = <&cpg CPG_MOD 702>; 1585 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1586 resets = <&cpg 702>; 1587 #phy-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 rpc: rpc@0xee200000 { 1592 compatible = "renesas,rpc-r8a7796", "renesas,rpc"; 1593 reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; 1594 clocks = <&cpg CPG_MOD 917>; 1595 bank-width = <2>; 1596 status = "disabled"; 1597 }; 1598 1599 sdhi0: sd@ee100000 { 1600 compatible = "renesas,sdhi-r8a7796", 1601 "renesas,rcar-gen3-sdhi"; 1602 reg = <0 0xee100000 0 0x2000>; 1603 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1604 clocks = <&cpg CPG_MOD 314>; 1605 max-frequency = <200000000>; 1606 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1607 resets = <&cpg 314>; 1608 status = "disabled"; 1609 }; 1610 1611 sdhi1: sd@ee120000 { 1612 compatible = "renesas,sdhi-r8a7796", 1613 "renesas,rcar-gen3-sdhi"; 1614 reg = <0 0xee120000 0 0x2000>; 1615 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1616 clocks = <&cpg CPG_MOD 313>; 1617 max-frequency = <200000000>; 1618 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1619 resets = <&cpg 313>; 1620 status = "disabled"; 1621 }; 1622 1623 sdhi2: sd@ee140000 { 1624 compatible = "renesas,sdhi-r8a7796", 1625 "renesas,rcar-gen3-sdhi"; 1626 reg = <0 0xee140000 0 0x2000>; 1627 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1628 clocks = <&cpg CPG_MOD 312>; 1629 max-frequency = <200000000>; 1630 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1631 resets = <&cpg 312>; 1632 status = "disabled"; 1633 }; 1634 1635 sdhi3: sd@ee160000 { 1636 compatible = "renesas,sdhi-r8a7796", 1637 "renesas,rcar-gen3-sdhi"; 1638 reg = <0 0xee160000 0 0x2000>; 1639 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1640 clocks = <&cpg CPG_MOD 311>; 1641 max-frequency = <200000000>; 1642 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1643 resets = <&cpg 311>; 1644 status = "disabled"; 1645 }; 1646 1647 tsc: thermal@e6198000 { 1648 compatible = "renesas,r8a7796-thermal"; 1649 reg = <0 0xe6198000 0 0x100>, 1650 <0 0xe61a0000 0 0x100>, 1651 <0 0xe61a8000 0 0x100>; 1652 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1655 clocks = <&cpg CPG_MOD 522>; 1656 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1657 resets = <&cpg 522>; 1658 #thermal-sensor-cells = <1>; 1659 status = "okay"; 1660 }; 1661 1662 rcar_sound: sound@ec500000 { 1663 /* 1664 * #sound-dai-cells is required 1665 * 1666 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1667 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1668 */ 1669 /* 1670 * #clock-cells is required for audio_clkout0/1/2/3 1671 * 1672 * clkout : #clock-cells = <0>; <&rcar_sound>; 1673 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1674 */ 1675 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; 1676 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1677 <0 0xec5a0000 0 0x100>, /* ADG */ 1678 <0 0xec540000 0 0x1000>, /* SSIU */ 1679 <0 0xec541000 0 0x280>, /* SSI */ 1680 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1681 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1682 1683 clocks = <&cpg CPG_MOD 1005>, 1684 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1685 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1686 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1687 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1688 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1689 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1690 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1691 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1692 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1693 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1694 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1695 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1696 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1697 <&audio_clk_a>, <&audio_clk_b>, 1698 <&audio_clk_c>, 1699 <&cpg CPG_CORE R8A7796_CLK_S0D4>; 1700 clock-names = "ssi-all", 1701 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1702 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1703 "ssi.1", "ssi.0", 1704 "src.9", "src.8", "src.7", "src.6", 1705 "src.5", "src.4", "src.3", "src.2", 1706 "src.1", "src.0", 1707 "mix.1", "mix.0", 1708 "ctu.1", "ctu.0", 1709 "dvc.0", "dvc.1", 1710 "clk_a", "clk_b", "clk_c", "clk_i"; 1711 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1712 resets = <&cpg 1005>, 1713 <&cpg 1006>, <&cpg 1007>, 1714 <&cpg 1008>, <&cpg 1009>, 1715 <&cpg 1010>, <&cpg 1011>, 1716 <&cpg 1012>, <&cpg 1013>, 1717 <&cpg 1014>, <&cpg 1015>; 1718 reset-names = "ssi-all", 1719 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1720 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1721 "ssi.1", "ssi.0"; 1722 status = "disabled"; 1723 1724 rcar_sound,dvc { 1725 dvc0: dvc-0 { 1726 dmas = <&audma1 0xbc>; 1727 dma-names = "tx"; 1728 }; 1729 dvc1: dvc-1 { 1730 dmas = <&audma1 0xbe>; 1731 dma-names = "tx"; 1732 }; 1733 }; 1734 1735 rcar_sound,mix { 1736 mix0: mix-0 { }; 1737 mix1: mix-1 { }; 1738 }; 1739 1740 rcar_sound,ctu { 1741 ctu00: ctu-0 { }; 1742 ctu01: ctu-1 { }; 1743 ctu02: ctu-2 { }; 1744 ctu03: ctu-3 { }; 1745 ctu10: ctu-4 { }; 1746 ctu11: ctu-5 { }; 1747 ctu12: ctu-6 { }; 1748 ctu13: ctu-7 { }; 1749 }; 1750 1751 rcar_sound,src { 1752 src0: src-0 { 1753 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1754 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1755 dma-names = "rx", "tx"; 1756 }; 1757 src1: src-1 { 1758 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1759 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1760 dma-names = "rx", "tx"; 1761 }; 1762 src2: src-2 { 1763 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1764 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1765 dma-names = "rx", "tx"; 1766 }; 1767 src3: src-3 { 1768 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1769 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1770 dma-names = "rx", "tx"; 1771 }; 1772 src4: src-4 { 1773 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1774 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1775 dma-names = "rx", "tx"; 1776 }; 1777 src5: src-5 { 1778 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1779 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1780 dma-names = "rx", "tx"; 1781 }; 1782 src6: src-6 { 1783 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1784 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1785 dma-names = "rx", "tx"; 1786 }; 1787 src7: src-7 { 1788 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1789 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1790 dma-names = "rx", "tx"; 1791 }; 1792 src8: src-8 { 1793 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1794 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1795 dma-names = "rx", "tx"; 1796 }; 1797 src9: src-9 { 1798 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1799 dmas = <&audma0 0x97>, <&audma1 0xba>; 1800 dma-names = "rx", "tx"; 1801 }; 1802 }; 1803 1804 rcar_sound,ssi { 1805 ssi0: ssi-0 { 1806 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1807 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1808 dma-names = "rx", "tx", "rxu", "txu"; 1809 }; 1810 ssi1: ssi-1 { 1811 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1812 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1813 dma-names = "rx", "tx", "rxu", "txu"; 1814 }; 1815 ssi2: ssi-2 { 1816 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1817 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1818 dma-names = "rx", "tx", "rxu", "txu"; 1819 }; 1820 ssi3: ssi-3 { 1821 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1822 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1823 dma-names = "rx", "tx", "rxu", "txu"; 1824 }; 1825 ssi4: ssi-4 { 1826 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1827 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1828 dma-names = "rx", "tx", "rxu", "txu"; 1829 }; 1830 ssi5: ssi-5 { 1831 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1832 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1833 dma-names = "rx", "tx", "rxu", "txu"; 1834 }; 1835 ssi6: ssi-6 { 1836 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1837 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1838 dma-names = "rx", "tx", "rxu", "txu"; 1839 }; 1840 ssi7: ssi-7 { 1841 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1842 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1843 dma-names = "rx", "tx", "rxu", "txu"; 1844 }; 1845 ssi8: ssi-8 { 1846 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1847 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1848 dma-names = "rx", "tx", "rxu", "txu"; 1849 }; 1850 ssi9: ssi-9 { 1851 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1852 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1853 dma-names = "rx", "tx", "rxu", "txu"; 1854 }; 1855 }; 1856 }; 1857 1858 pciec0: pcie@fe000000 { 1859 reg = <0 0xfe000000 0 0x80000>; 1860 /* placeholder */ 1861 }; 1862 1863 pciec1: pcie@ee800000 { 1864 reg = <0 0xee800000 0 0x80000>; 1865 /* placeholder */ 1866 }; 1867 1868 fdp1@fe940000 { 1869 compatible = "renesas,fdp1"; 1870 reg = <0 0xfe940000 0 0x2400>; 1871 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1872 clocks = <&cpg CPG_MOD 119>; 1873 power-domains = <&sysc R8A7796_PD_A3VC>; 1874 resets = <&cpg 119>; 1875 renesas,fcp = <&fcpf0>; 1876 }; 1877 1878 fcpf0: fcp@fe950000 { 1879 compatible = "renesas,fcpf"; 1880 reg = <0 0xfe950000 0 0x200>; 1881 clocks = <&cpg CPG_MOD 615>; 1882 power-domains = <&sysc R8A7796_PD_A3VC>; 1883 resets = <&cpg 615>; 1884 }; 1885 1886 vspb: vsp@fe960000 { 1887 compatible = "renesas,vsp2"; 1888 reg = <0 0xfe960000 0 0x8000>; 1889 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1890 clocks = <&cpg CPG_MOD 626>; 1891 power-domains = <&sysc R8A7796_PD_A3VC>; 1892 resets = <&cpg 626>; 1893 1894 renesas,fcp = <&fcpvb0>; 1895 }; 1896 1897 fcpvb0: fcp@fe96f000 { 1898 compatible = "renesas,fcpv"; 1899 reg = <0 0xfe96f000 0 0x200>; 1900 clocks = <&cpg CPG_MOD 607>; 1901 power-domains = <&sysc R8A7796_PD_A3VC>; 1902 resets = <&cpg 607>; 1903 }; 1904 1905 vspi0: vsp@fe9a0000 { 1906 compatible = "renesas,vsp2"; 1907 reg = <0 0xfe9a0000 0 0x8000>; 1908 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1909 clocks = <&cpg CPG_MOD 631>; 1910 power-domains = <&sysc R8A7796_PD_A3VC>; 1911 resets = <&cpg 631>; 1912 1913 renesas,fcp = <&fcpvi0>; 1914 }; 1915 1916 fcpvi0: fcp@fe9af000 { 1917 compatible = "renesas,fcpv"; 1918 reg = <0 0xfe9af000 0 0x200>; 1919 clocks = <&cpg CPG_MOD 611>; 1920 power-domains = <&sysc R8A7796_PD_A3VC>; 1921 resets = <&cpg 611>; 1922 iommus = <&ipmmu_vc0 19>; 1923 }; 1924 1925 vspd0: vsp@fea20000 { 1926 compatible = "renesas,vsp2"; 1927 reg = <0 0xfea20000 0 0x8000>; 1928 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1929 clocks = <&cpg CPG_MOD 623>; 1930 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1931 resets = <&cpg 623>; 1932 1933 renesas,fcp = <&fcpvd0>; 1934 }; 1935 1936 fcpvd0: fcp@fea27000 { 1937 compatible = "renesas,fcpv"; 1938 reg = <0 0xfea27000 0 0x200>; 1939 clocks = <&cpg CPG_MOD 603>; 1940 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1941 resets = <&cpg 603>; 1942 iommus = <&ipmmu_vi0 8>; 1943 }; 1944 1945 vspd1: vsp@fea28000 { 1946 compatible = "renesas,vsp2"; 1947 reg = <0 0xfea28000 0 0x8000>; 1948 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1949 clocks = <&cpg CPG_MOD 622>; 1950 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1951 resets = <&cpg 622>; 1952 1953 renesas,fcp = <&fcpvd1>; 1954 }; 1955 1956 fcpvd1: fcp@fea2f000 { 1957 compatible = "renesas,fcpv"; 1958 reg = <0 0xfea2f000 0 0x200>; 1959 clocks = <&cpg CPG_MOD 602>; 1960 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1961 resets = <&cpg 602>; 1962 iommus = <&ipmmu_vi0 9>; 1963 }; 1964 1965 vspd2: vsp@fea30000 { 1966 compatible = "renesas,vsp2"; 1967 reg = <0 0xfea30000 0 0x8000>; 1968 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1969 clocks = <&cpg CPG_MOD 621>; 1970 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1971 resets = <&cpg 621>; 1972 1973 renesas,fcp = <&fcpvd2>; 1974 }; 1975 1976 fcpvd2: fcp@fea37000 { 1977 compatible = "renesas,fcpv"; 1978 reg = <0 0xfea37000 0 0x200>; 1979 clocks = <&cpg CPG_MOD 601>; 1980 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1981 resets = <&cpg 601>; 1982 iommus = <&ipmmu_vi0 10>; 1983 }; 1984 1985 hdmi0: hdmi@fead0000 { 1986 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi"; 1987 reg = <0 0xfead0000 0 0x10000>; 1988 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 1989 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>; 1990 clock-names = "iahb", "isfr"; 1991 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1992 resets = <&cpg 729>; 1993 status = "disabled"; 1994 1995 ports { 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 port@0 { 1999 reg = <0>; 2000 dw_hdmi0_in: endpoint { 2001 remote-endpoint = <&du_out_hdmi0>; 2002 }; 2003 }; 2004 port@1 { 2005 reg = <1>; 2006 }; 2007 }; 2008 }; 2009 2010 du: display@feb00000 { 2011 compatible = "renesas,du-r8a7796"; 2012 reg = <0 0xfeb00000 0 0x70000>, 2013 <0 0xfeb90000 0 0x14>; 2014 reg-names = "du", "lvds.0"; 2015 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2016 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2018 clocks = <&cpg CPG_MOD 724>, 2019 <&cpg CPG_MOD 723>, 2020 <&cpg CPG_MOD 722>, 2021 <&cpg CPG_MOD 727>; 2022 clock-names = "du.0", "du.1", "du.2", "lvds.0"; 2023 status = "disabled"; 2024 2025 vsps = <&vspd0 &vspd1 &vspd2>; 2026 2027 ports { 2028 #address-cells = <1>; 2029 #size-cells = <0>; 2030 2031 port@0 { 2032 reg = <0>; 2033 du_out_rgb: endpoint { 2034 }; 2035 }; 2036 port@1 { 2037 reg = <1>; 2038 du_out_hdmi0: endpoint { 2039 remote-endpoint = <&dw_hdmi0_in>; 2040 }; 2041 }; 2042 port@2 { 2043 reg = <2>; 2044 du_out_lvds0: endpoint { 2045 }; 2046 }; 2047 }; 2048 }; 2049 2050 imr-lx4@fe860000 { 2051 compatible = "renesas,r8a7796-imr-lx4", 2052 "renesas,imr-lx4"; 2053 reg = <0 0xfe860000 0 0x2000>; 2054 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 2055 clocks = <&cpg CPG_MOD 823>; 2056 power-domains = <&sysc R8A7796_PD_A3VC>; 2057 resets = <&cpg 823>; 2058 }; 2059 2060 imr-lx4@fe870000 { 2061 compatible = "renesas,r8a7796-imr-lx4", 2062 "renesas,imr-lx4"; 2063 reg = <0 0xfe870000 0 0x2000>; 2064 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 2065 clocks = <&cpg CPG_MOD 822>; 2066 power-domains = <&sysc R8A7796_PD_A3VC>; 2067 resets = <&cpg 822>; 2068 }; 2069 }; 2070 2071 timer { 2072 compatible = "arm,armv8-timer"; 2073 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2074 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2075 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2076 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2077 }; 2078 2079 thermal-zones { 2080 sensor_thermal1: sensor-thermal1 { 2081 polling-delay-passive = <250>; 2082 polling-delay = <1000>; 2083 thermal-sensors = <&tsc 0>; 2084 2085 trips { 2086 sensor1_passive: sensor1-passive { 2087 temperature = <95000>; 2088 hysteresis = <2000>; 2089 type = "passive"; 2090 }; 2091 sensor1_crit: sensor1-crit { 2092 temperature = <120000>; 2093 hysteresis = <2000>; 2094 type = "critical"; 2095 }; 2096 }; 2097 2098 cooling-maps { 2099 map0 { 2100 trip = <&sensor1_passive>; 2101 cooling-device = <&a57_0 5 5>; 2102 }; 2103 }; 2104 }; 2105 2106 sensor_thermal2: sensor-thermal2 { 2107 polling-delay-passive = <250>; 2108 polling-delay = <1000>; 2109 thermal-sensors = <&tsc 1>; 2110 2111 trips { 2112 sensor2_passive: sensor2-passive { 2113 temperature = <95000>; 2114 hysteresis = <2000>; 2115 type = "passive"; 2116 }; 2117 sensor2_crit: sensor2-crit { 2118 temperature = <120000>; 2119 hysteresis = <2000>; 2120 type = "critical"; 2121 }; 2122 }; 2123 2124 cooling-maps { 2125 map0 { 2126 trip = <&sensor2_passive>; 2127 cooling-device = <&a57_0 5 5>; 2128 }; 2129 }; 2130 }; 2131 2132 sensor_thermal3: sensor-thermal3 { 2133 polling-delay-passive = <250>; 2134 polling-delay = <1000>; 2135 thermal-sensors = <&tsc 2>; 2136 2137 trips { 2138 sensor3_passive: sensor3-passive { 2139 temperature = <95000>; 2140 hysteresis = <2000>; 2141 type = "passive"; 2142 }; 2143 sensor3_crit: sensor3-crit { 2144 temperature = <120000>; 2145 hysteresis = <2000>; 2146 type = "critical"; 2147 }; 2148 }; 2149 2150 cooling-maps { 2151 map0 { 2152 trip = <&sensor3_passive>; 2153 cooling-device = <&a57_0 5 5>; 2154 }; 2155 }; 2156 }; 2157 }; 2158 2159 /* External USB clocks - can be overridden by the board */ 2160 usb3s0_clk: usb3s0 { 2161 compatible = "fixed-clock"; 2162 #clock-cells = <0>; 2163 clock-frequency = <0>; 2164 }; 2165 2166 usb_extal_clk: usb_extal { 2167 compatible = "fixed-clock"; 2168 #clock-cells = <0>; 2169 clock-frequency = <0>; 2170 }; 2171}; 2172