1/* 2 * Device Tree Source for the r8a7795 SoC 3 * 4 * Copyright (C) 2015 Renesas Electronics Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9#include <dt-bindings/clock/r8a7795-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a7795-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a7795"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c_dvfs; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0", "arm,psci-0.2"; 33 method = "smc"; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 a57_0: cpu@0 { 41 compatible = "arm,cortex-a57", "arm,armv8"; 42 reg = <0x0>; 43 device_type = "cpu"; 44 power-domains = <&sysc R8A7795_PD_CA57_CPU0>; 45 next-level-cache = <&L2_CA57>; 46 enable-method = "psci"; 47 }; 48 49 a57_1: cpu@1 { 50 compatible = "arm,cortex-a57","arm,armv8"; 51 reg = <0x1>; 52 device_type = "cpu"; 53 power-domains = <&sysc R8A7795_PD_CA57_CPU1>; 54 next-level-cache = <&L2_CA57>; 55 enable-method = "psci"; 56 }; 57 58 a57_2: cpu@2 { 59 compatible = "arm,cortex-a57","arm,armv8"; 60 reg = <0x2>; 61 device_type = "cpu"; 62 power-domains = <&sysc R8A7795_PD_CA57_CPU2>; 63 next-level-cache = <&L2_CA57>; 64 enable-method = "psci"; 65 }; 66 67 a57_3: cpu@3 { 68 compatible = "arm,cortex-a57","arm,armv8"; 69 reg = <0x3>; 70 device_type = "cpu"; 71 power-domains = <&sysc R8A7795_PD_CA57_CPU3>; 72 next-level-cache = <&L2_CA57>; 73 enable-method = "psci"; 74 }; 75 76 a53_0: cpu@100 { 77 compatible = "arm,cortex-a53", "arm,armv8"; 78 reg = <0x100>; 79 device_type = "cpu"; 80 power-domains = <&sysc R8A7795_PD_CA53_CPU0>; 81 next-level-cache = <&L2_CA53>; 82 enable-method = "psci"; 83 }; 84 85 a53_1: cpu@101 { 86 compatible = "arm,cortex-a53","arm,armv8"; 87 reg = <0x101>; 88 device_type = "cpu"; 89 power-domains = <&sysc R8A7795_PD_CA53_CPU1>; 90 next-level-cache = <&L2_CA53>; 91 enable-method = "psci"; 92 }; 93 94 a53_2: cpu@102 { 95 compatible = "arm,cortex-a53","arm,armv8"; 96 reg = <0x102>; 97 device_type = "cpu"; 98 power-domains = <&sysc R8A7795_PD_CA53_CPU2>; 99 next-level-cache = <&L2_CA53>; 100 enable-method = "psci"; 101 }; 102 103 a53_3: cpu@103 { 104 compatible = "arm,cortex-a53","arm,armv8"; 105 reg = <0x103>; 106 device_type = "cpu"; 107 power-domains = <&sysc R8A7795_PD_CA53_CPU3>; 108 next-level-cache = <&L2_CA53>; 109 enable-method = "psci"; 110 }; 111 112 L2_CA57: cache-controller-0 { 113 compatible = "cache"; 114 power-domains = <&sysc R8A7795_PD_CA57_SCU>; 115 cache-unified; 116 cache-level = <2>; 117 }; 118 119 L2_CA53: cache-controller-1 { 120 compatible = "cache"; 121 power-domains = <&sysc R8A7795_PD_CA53_SCU>; 122 cache-unified; 123 cache-level = <2>; 124 }; 125 }; 126 127 extal_clk: extal { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 /* This value must be overridden by the board */ 131 clock-frequency = <0>; 132 }; 133 134 extalr_clk: extalr { 135 compatible = "fixed-clock"; 136 #clock-cells = <0>; 137 /* This value must be overridden by the board */ 138 clock-frequency = <0>; 139 }; 140 141 /* 142 * The external audio clocks are configured as 0 Hz fixed frequency 143 * clocks by default. 144 * Boards that provide audio clocks should override them. 145 */ 146 audio_clk_a: audio_clk_a { 147 compatible = "fixed-clock"; 148 #clock-cells = <0>; 149 clock-frequency = <0>; 150 }; 151 152 audio_clk_b: audio_clk_b { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-frequency = <0>; 156 }; 157 158 audio_clk_c: audio_clk_c { 159 compatible = "fixed-clock"; 160 #clock-cells = <0>; 161 clock-frequency = <0>; 162 }; 163 164 /* External CAN clock - to be overridden by boards that provide it */ 165 can_clk: can { 166 compatible = "fixed-clock"; 167 #clock-cells = <0>; 168 clock-frequency = <0>; 169 }; 170 171 /* External SCIF clock - to be overridden by boards that provide it */ 172 scif_clk: scif { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <0>; 176 }; 177 178 /* External PCIe clock - can be overridden by the board */ 179 pcie_bus_clk: pcie_bus { 180 compatible = "fixed-clock"; 181 #clock-cells = <0>; 182 clock-frequency = <0>; 183 }; 184 185 soc: soc { 186 compatible = "simple-bus"; 187 interrupt-parent = <&gic>; 188 189 #address-cells = <2>; 190 #size-cells = <2>; 191 ranges; 192 193 gic: interrupt-controller@f1010000 { 194 compatible = "arm,gic-400"; 195 #interrupt-cells = <3>; 196 #address-cells = <0>; 197 interrupt-controller; 198 reg = <0x0 0xf1010000 0 0x1000>, 199 <0x0 0xf1020000 0 0x20000>, 200 <0x0 0xf1040000 0 0x20000>, 201 <0x0 0xf1060000 0 0x20000>; 202 interrupts = <GIC_PPI 9 203 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 204 clocks = <&cpg CPG_MOD 408>; 205 clock-names = "clk"; 206 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 207 resets = <&cpg 408>; 208 }; 209 210 wdt0: watchdog@e6020000 { 211 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; 212 reg = <0 0xe6020000 0 0x0c>; 213 clocks = <&cpg CPG_MOD 402>; 214 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 215 resets = <&cpg 402>; 216 status = "disabled"; 217 }; 218 219 gpio0: gpio@e6050000 { 220 compatible = "renesas,gpio-r8a7795", 221 "renesas,gpio-rcar"; 222 reg = <0 0xe6050000 0 0x50>; 223 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 224 #gpio-cells = <2>; 225 gpio-controller; 226 gpio-ranges = <&pfc 0 0 16>; 227 #interrupt-cells = <2>; 228 interrupt-controller; 229 clocks = <&cpg CPG_MOD 912>; 230 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 231 resets = <&cpg 912>; 232 }; 233 234 gpio1: gpio@e6051000 { 235 compatible = "renesas,gpio-r8a7795", 236 "renesas,gpio-rcar"; 237 reg = <0 0xe6051000 0 0x50>; 238 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 239 #gpio-cells = <2>; 240 gpio-controller; 241 gpio-ranges = <&pfc 0 32 28>; 242 #interrupt-cells = <2>; 243 interrupt-controller; 244 clocks = <&cpg CPG_MOD 911>; 245 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 246 resets = <&cpg 911>; 247 }; 248 249 gpio2: gpio@e6052000 { 250 compatible = "renesas,gpio-r8a7795", 251 "renesas,gpio-rcar"; 252 reg = <0 0xe6052000 0 0x50>; 253 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 254 #gpio-cells = <2>; 255 gpio-controller; 256 gpio-ranges = <&pfc 0 64 15>; 257 #interrupt-cells = <2>; 258 interrupt-controller; 259 clocks = <&cpg CPG_MOD 910>; 260 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 261 resets = <&cpg 910>; 262 }; 263 264 gpio3: gpio@e6053000 { 265 compatible = "renesas,gpio-r8a7795", 266 "renesas,gpio-rcar"; 267 reg = <0 0xe6053000 0 0x50>; 268 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 269 #gpio-cells = <2>; 270 gpio-controller; 271 gpio-ranges = <&pfc 0 96 16>; 272 #interrupt-cells = <2>; 273 interrupt-controller; 274 clocks = <&cpg CPG_MOD 909>; 275 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 276 resets = <&cpg 909>; 277 }; 278 279 gpio4: gpio@e6054000 { 280 compatible = "renesas,gpio-r8a7795", 281 "renesas,gpio-rcar"; 282 reg = <0 0xe6054000 0 0x50>; 283 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 284 #gpio-cells = <2>; 285 gpio-controller; 286 gpio-ranges = <&pfc 0 128 18>; 287 #interrupt-cells = <2>; 288 interrupt-controller; 289 clocks = <&cpg CPG_MOD 908>; 290 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 291 resets = <&cpg 908>; 292 }; 293 294 gpio5: gpio@e6055000 { 295 compatible = "renesas,gpio-r8a7795", 296 "renesas,gpio-rcar"; 297 reg = <0 0xe6055000 0 0x50>; 298 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 299 #gpio-cells = <2>; 300 gpio-controller; 301 gpio-ranges = <&pfc 0 160 26>; 302 #interrupt-cells = <2>; 303 interrupt-controller; 304 clocks = <&cpg CPG_MOD 907>; 305 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 306 resets = <&cpg 907>; 307 }; 308 309 gpio6: gpio@e6055400 { 310 compatible = "renesas,gpio-r8a7795", 311 "renesas,gpio-rcar"; 312 reg = <0 0xe6055400 0 0x50>; 313 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 314 #gpio-cells = <2>; 315 gpio-controller; 316 gpio-ranges = <&pfc 0 192 32>; 317 #interrupt-cells = <2>; 318 interrupt-controller; 319 clocks = <&cpg CPG_MOD 906>; 320 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 321 resets = <&cpg 906>; 322 }; 323 324 gpio7: gpio@e6055800 { 325 compatible = "renesas,gpio-r8a7795", 326 "renesas,gpio-rcar"; 327 reg = <0 0xe6055800 0 0x50>; 328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 329 #gpio-cells = <2>; 330 gpio-controller; 331 gpio-ranges = <&pfc 0 224 4>; 332 #interrupt-cells = <2>; 333 interrupt-controller; 334 clocks = <&cpg CPG_MOD 905>; 335 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 336 resets = <&cpg 905>; 337 }; 338 339 pmu_a57 { 340 compatible = "arm,cortex-a57-pmu"; 341 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 345 interrupt-affinity = <&a57_0>, 346 <&a57_1>, 347 <&a57_2>, 348 <&a57_3>; 349 }; 350 351 pmu_a53 { 352 compatible = "arm,cortex-a53-pmu"; 353 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-affinity = <&a53_0>, 358 <&a53_1>, 359 <&a53_2>, 360 <&a53_3>; 361 }; 362 363 timer { 364 compatible = "arm,armv8-timer"; 365 interrupts = <GIC_PPI 13 366 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 367 <GIC_PPI 14 368 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 369 <GIC_PPI 11 370 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 371 <GIC_PPI 10 372 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 373 }; 374 375 cpg: clock-controller@e6150000 { 376 compatible = "renesas,r8a7795-cpg-mssr"; 377 reg = <0 0xe6150000 0 0x1000>; 378 clocks = <&extal_clk>, <&extalr_clk>; 379 clock-names = "extal", "extalr"; 380 #clock-cells = <2>; 381 #power-domain-cells = <0>; 382 #reset-cells = <1>; 383 }; 384 385 rst: reset-controller@e6160000 { 386 compatible = "renesas,r8a7795-rst"; 387 reg = <0 0xe6160000 0 0x0200>; 388 }; 389 390 prr: chipid@fff00044 { 391 compatible = "renesas,prr"; 392 reg = <0 0xfff00044 0 4>; 393 }; 394 395 sysc: system-controller@e6180000 { 396 compatible = "renesas,r8a7795-sysc"; 397 reg = <0 0xe6180000 0 0x0400>; 398 #power-domain-cells = <1>; 399 }; 400 401 pfc: pin-controller@e6060000 { 402 compatible = "renesas,pfc-r8a7795"; 403 reg = <0 0xe6060000 0 0x50c>; 404 }; 405 406 intc_ex: interrupt-controller@e61c0000 { 407 compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; 408 #interrupt-cells = <2>; 409 interrupt-controller; 410 reg = <0 0xe61c0000 0 0x200>; 411 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 412 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 413 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 414 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 415 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 416 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&cpg CPG_MOD 407>; 418 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 419 resets = <&cpg 407>; 420 }; 421 422 dmac0: dma-controller@e6700000 { 423 compatible = "renesas,dmac-r8a7795", 424 "renesas,rcar-dmac"; 425 reg = <0 0xe6700000 0 0x10000>; 426 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 427 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 428 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 429 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 430 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 431 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 432 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 433 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 434 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 435 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 436 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 437 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 438 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 439 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 440 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 441 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 442 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 443 interrupt-names = "error", 444 "ch0", "ch1", "ch2", "ch3", 445 "ch4", "ch5", "ch6", "ch7", 446 "ch8", "ch9", "ch10", "ch11", 447 "ch12", "ch13", "ch14", "ch15"; 448 clocks = <&cpg CPG_MOD 219>; 449 clock-names = "fck"; 450 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 451 resets = <&cpg 219>; 452 #dma-cells = <1>; 453 dma-channels = <16>; 454 }; 455 456 dmac1: dma-controller@e7300000 { 457 compatible = "renesas,dmac-r8a7795", 458 "renesas,rcar-dmac"; 459 reg = <0 0xe7300000 0 0x10000>; 460 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 461 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 462 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 463 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 464 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 465 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 466 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 467 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 468 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 469 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 470 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 471 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 472 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 473 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 474 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 475 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 476 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-names = "error", 478 "ch0", "ch1", "ch2", "ch3", 479 "ch4", "ch5", "ch6", "ch7", 480 "ch8", "ch9", "ch10", "ch11", 481 "ch12", "ch13", "ch14", "ch15"; 482 clocks = <&cpg CPG_MOD 218>; 483 clock-names = "fck"; 484 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 485 resets = <&cpg 218>; 486 #dma-cells = <1>; 487 dma-channels = <16>; 488 }; 489 490 dmac2: dma-controller@e7310000 { 491 compatible = "renesas,dmac-r8a7795", 492 "renesas,rcar-dmac"; 493 reg = <0 0xe7310000 0 0x10000>; 494 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 495 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 496 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 497 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 498 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 499 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 500 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 501 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 502 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 503 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 504 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 505 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 506 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 507 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 508 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 509 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 510 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 511 interrupt-names = "error", 512 "ch0", "ch1", "ch2", "ch3", 513 "ch4", "ch5", "ch6", "ch7", 514 "ch8", "ch9", "ch10", "ch11", 515 "ch12", "ch13", "ch14", "ch15"; 516 clocks = <&cpg CPG_MOD 217>; 517 clock-names = "fck"; 518 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 519 resets = <&cpg 217>; 520 #dma-cells = <1>; 521 dma-channels = <16>; 522 }; 523 524 audma0: dma-controller@ec700000 { 525 compatible = "renesas,dmac-r8a7795", 526 "renesas,rcar-dmac"; 527 reg = <0 0xec700000 0 0x10000>; 528 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 529 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 530 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 531 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 532 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 533 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 534 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 535 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 536 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 537 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 538 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 539 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 540 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 541 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 542 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 543 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 544 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 545 interrupt-names = "error", 546 "ch0", "ch1", "ch2", "ch3", 547 "ch4", "ch5", "ch6", "ch7", 548 "ch8", "ch9", "ch10", "ch11", 549 "ch12", "ch13", "ch14", "ch15"; 550 clocks = <&cpg CPG_MOD 502>; 551 clock-names = "fck"; 552 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 553 resets = <&cpg 502>; 554 #dma-cells = <1>; 555 dma-channels = <16>; 556 }; 557 558 audma1: dma-controller@ec720000 { 559 compatible = "renesas,dmac-r8a7795", 560 "renesas,rcar-dmac"; 561 reg = <0 0xec720000 0 0x10000>; 562 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 563 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 564 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 565 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 566 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 567 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 568 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 569 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 570 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 571 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 572 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 573 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 574 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 575 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 576 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 577 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 578 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 579 interrupt-names = "error", 580 "ch0", "ch1", "ch2", "ch3", 581 "ch4", "ch5", "ch6", "ch7", 582 "ch8", "ch9", "ch10", "ch11", 583 "ch12", "ch13", "ch14", "ch15"; 584 clocks = <&cpg CPG_MOD 501>; 585 clock-names = "fck"; 586 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 587 resets = <&cpg 501>; 588 #dma-cells = <1>; 589 dma-channels = <16>; 590 }; 591 592 avb: ethernet@e6800000 { 593 compatible = "renesas,etheravb-r8a7795", 594 "renesas,etheravb-rcar-gen3"; 595 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 596 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "ch0", "ch1", "ch2", "ch3", 622 "ch4", "ch5", "ch6", "ch7", 623 "ch8", "ch9", "ch10", "ch11", 624 "ch12", "ch13", "ch14", "ch15", 625 "ch16", "ch17", "ch18", "ch19", 626 "ch20", "ch21", "ch22", "ch23", 627 "ch24"; 628 clocks = <&cpg CPG_MOD 812>; 629 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 630 resets = <&cpg 812>; 631 phy-mode = "rgmii-txid"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 status = "disabled"; 635 }; 636 637 can0: can@e6c30000 { 638 compatible = "renesas,can-r8a7795", 639 "renesas,rcar-gen3-can"; 640 reg = <0 0xe6c30000 0 0x1000>; 641 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cpg CPG_MOD 916>, 643 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 644 <&can_clk>; 645 clock-names = "clkp1", "clkp2", "can_clk"; 646 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 647 assigned-clock-rates = <40000000>; 648 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 649 resets = <&cpg 916>; 650 status = "disabled"; 651 }; 652 653 can1: can@e6c38000 { 654 compatible = "renesas,can-r8a7795", 655 "renesas,rcar-gen3-can"; 656 reg = <0 0xe6c38000 0 0x1000>; 657 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cpg CPG_MOD 915>, 659 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 660 <&can_clk>; 661 clock-names = "clkp1", "clkp2", "can_clk"; 662 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 663 assigned-clock-rates = <40000000>; 664 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 665 resets = <&cpg 915>; 666 status = "disabled"; 667 }; 668 669 canfd: can@e66c0000 { 670 compatible = "renesas,r8a7795-canfd", 671 "renesas,rcar-gen3-canfd"; 672 reg = <0 0xe66c0000 0 0x8000>; 673 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&cpg CPG_MOD 914>, 676 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 677 <&can_clk>; 678 clock-names = "fck", "canfd", "can_clk"; 679 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 680 assigned-clock-rates = <40000000>; 681 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 682 resets = <&cpg 914>; 683 status = "disabled"; 684 685 channel0 { 686 status = "disabled"; 687 }; 688 689 channel1 { 690 status = "disabled"; 691 }; 692 }; 693 694 drif00: rif@e6f40000 { 695 compatible = "renesas,r8a7795-drif", 696 "renesas,rcar-gen3-drif"; 697 reg = <0 0xe6f40000 0 0x64>; 698 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cpg CPG_MOD 515>; 700 clock-names = "fck"; 701 dmas = <&dmac1 0x20>, <&dmac2 0x20>; 702 dma-names = "rx", "rx"; 703 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 704 resets = <&cpg 515>; 705 renesas,bonding = <&drif01>; 706 status = "disabled"; 707 }; 708 709 drif01: rif@e6f50000 { 710 compatible = "renesas,r8a7795-drif", 711 "renesas,rcar-gen3-drif"; 712 reg = <0 0xe6f50000 0 0x64>; 713 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cpg CPG_MOD 514>; 715 clock-names = "fck"; 716 dmas = <&dmac1 0x22>, <&dmac2 0x22>; 717 dma-names = "rx", "rx"; 718 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 719 resets = <&cpg 514>; 720 renesas,bonding = <&drif00>; 721 status = "disabled"; 722 }; 723 724 drif10: rif@e6f60000 { 725 compatible = "renesas,r8a7795-drif", 726 "renesas,rcar-gen3-drif"; 727 reg = <0 0xe6f60000 0 0x64>; 728 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&cpg CPG_MOD 513>; 730 clock-names = "fck"; 731 dmas = <&dmac1 0x24>, <&dmac2 0x24>; 732 dma-names = "rx", "rx"; 733 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 734 resets = <&cpg 513>; 735 renesas,bonding = <&drif11>; 736 status = "disabled"; 737 }; 738 739 drif11: rif@e6f70000 { 740 compatible = "renesas,r8a7795-drif", 741 "renesas,rcar-gen3-drif"; 742 reg = <0 0xe6f70000 0 0x64>; 743 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&cpg CPG_MOD 512>; 745 clock-names = "fck"; 746 dmas = <&dmac1 0x26>, <&dmac2 0x26>; 747 dma-names = "rx", "rx"; 748 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 749 resets = <&cpg 512>; 750 renesas,bonding = <&drif10>; 751 status = "disabled"; 752 }; 753 754 drif20: rif@e6f80000 { 755 compatible = "renesas,r8a7795-drif", 756 "renesas,rcar-gen3-drif"; 757 reg = <0 0xe6f80000 0 0x64>; 758 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cpg CPG_MOD 511>; 760 clock-names = "fck"; 761 dmas = <&dmac1 0x28>, <&dmac2 0x28>; 762 dma-names = "rx", "rx"; 763 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 764 resets = <&cpg 511>; 765 renesas,bonding = <&drif21>; 766 status = "disabled"; 767 }; 768 769 drif21: rif@e6f90000 { 770 compatible = "renesas,r8a7795-drif", 771 "renesas,rcar-gen3-drif"; 772 reg = <0 0xe6f90000 0 0x64>; 773 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&cpg CPG_MOD 510>; 775 clock-names = "fck"; 776 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; 777 dma-names = "rx", "rx"; 778 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 779 resets = <&cpg 510>; 780 renesas,bonding = <&drif20>; 781 status = "disabled"; 782 }; 783 784 drif30: rif@e6fa0000 { 785 compatible = "renesas,r8a7795-drif", 786 "renesas,rcar-gen3-drif"; 787 reg = <0 0xe6fa0000 0 0x64>; 788 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&cpg CPG_MOD 509>; 790 clock-names = "fck"; 791 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; 792 dma-names = "rx", "rx"; 793 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 794 resets = <&cpg 509>; 795 renesas,bonding = <&drif31>; 796 status = "disabled"; 797 }; 798 799 drif31: rif@e6fb0000 { 800 compatible = "renesas,r8a7795-drif", 801 "renesas,rcar-gen3-drif"; 802 reg = <0 0xe6fb0000 0 0x64>; 803 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&cpg CPG_MOD 508>; 805 clock-names = "fck"; 806 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; 807 dma-names = "rx", "rx"; 808 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 809 resets = <&cpg 508>; 810 renesas,bonding = <&drif30>; 811 status = "disabled"; 812 }; 813 814 hscif0: serial@e6540000 { 815 compatible = "renesas,hscif-r8a7795", 816 "renesas,rcar-gen3-hscif", 817 "renesas,hscif"; 818 reg = <0 0xe6540000 0 96>; 819 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&cpg CPG_MOD 520>, 821 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 822 <&scif_clk>; 823 clock-names = "fck", "brg_int", "scif_clk"; 824 dmas = <&dmac1 0x31>, <&dmac1 0x30>; 825 dma-names = "tx", "rx"; 826 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 827 resets = <&cpg 520>; 828 status = "disabled"; 829 }; 830 831 hscif1: serial@e6550000 { 832 compatible = "renesas,hscif-r8a7795", 833 "renesas,rcar-gen3-hscif", 834 "renesas,hscif"; 835 reg = <0 0xe6550000 0 96>; 836 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&cpg CPG_MOD 519>, 838 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 839 <&scif_clk>; 840 clock-names = "fck", "brg_int", "scif_clk"; 841 dmas = <&dmac1 0x33>, <&dmac1 0x32>; 842 dma-names = "tx", "rx"; 843 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 844 resets = <&cpg 519>; 845 status = "disabled"; 846 }; 847 848 hscif2: serial@e6560000 { 849 compatible = "renesas,hscif-r8a7795", 850 "renesas,rcar-gen3-hscif", 851 "renesas,hscif"; 852 reg = <0 0xe6560000 0 96>; 853 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&cpg CPG_MOD 518>, 855 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 856 <&scif_clk>; 857 clock-names = "fck", "brg_int", "scif_clk"; 858 dmas = <&dmac1 0x35>, <&dmac1 0x34>; 859 dma-names = "tx", "rx"; 860 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 861 resets = <&cpg 518>; 862 status = "disabled"; 863 }; 864 865 hscif3: serial@e66a0000 { 866 compatible = "renesas,hscif-r8a7795", 867 "renesas,rcar-gen3-hscif", 868 "renesas,hscif"; 869 reg = <0 0xe66a0000 0 96>; 870 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&cpg CPG_MOD 517>, 872 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 873 <&scif_clk>; 874 clock-names = "fck", "brg_int", "scif_clk"; 875 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 876 dma-names = "tx", "rx"; 877 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 878 resets = <&cpg 517>; 879 status = "disabled"; 880 }; 881 882 hscif4: serial@e66b0000 { 883 compatible = "renesas,hscif-r8a7795", 884 "renesas,rcar-gen3-hscif", 885 "renesas,hscif"; 886 reg = <0 0xe66b0000 0 96>; 887 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&cpg CPG_MOD 516>, 889 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 890 <&scif_clk>; 891 clock-names = "fck", "brg_int", "scif_clk"; 892 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 893 dma-names = "tx", "rx"; 894 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 895 resets = <&cpg 516>; 896 status = "disabled"; 897 }; 898 899 msiof0: spi@e6e90000 { 900 compatible = "renesas,msiof-r8a7795", 901 "renesas,rcar-gen3-msiof"; 902 reg = <0 0xe6e90000 0 0x0064>; 903 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&cpg CPG_MOD 211>; 905 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 906 <&dmac2 0x41>, <&dmac2 0x40>; 907 dma-names = "tx", "rx", "tx", "rx"; 908 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 909 resets = <&cpg 211>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 status = "disabled"; 913 }; 914 915 msiof1: spi@e6ea0000 { 916 compatible = "renesas,msiof-r8a7795", 917 "renesas,rcar-gen3-msiof"; 918 reg = <0 0xe6ea0000 0 0x0064>; 919 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&cpg CPG_MOD 210>; 921 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 922 <&dmac2 0x43>, <&dmac2 0x42>; 923 dma-names = "tx", "rx", "tx", "rx"; 924 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 925 resets = <&cpg 210>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "disabled"; 929 }; 930 931 msiof2: spi@e6c00000 { 932 compatible = "renesas,msiof-r8a7795", 933 "renesas,rcar-gen3-msiof"; 934 reg = <0 0xe6c00000 0 0x0064>; 935 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&cpg CPG_MOD 209>; 937 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 938 dma-names = "tx", "rx"; 939 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 940 resets = <&cpg 209>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 }; 945 946 msiof3: spi@e6c10000 { 947 compatible = "renesas,msiof-r8a7795", 948 "renesas,rcar-gen3-msiof"; 949 reg = <0 0xe6c10000 0 0x0064>; 950 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&cpg CPG_MOD 208>; 952 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 953 dma-names = "tx", "rx"; 954 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 955 resets = <&cpg 208>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 status = "disabled"; 959 }; 960 961 scif0: serial@e6e60000 { 962 compatible = "renesas,scif-r8a7795", 963 "renesas,rcar-gen3-scif", "renesas,scif"; 964 reg = <0 0xe6e60000 0 64>; 965 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&cpg CPG_MOD 207>, 967 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 968 <&scif_clk>; 969 clock-names = "fck", "brg_int", "scif_clk"; 970 dmas = <&dmac1 0x51>, <&dmac1 0x50>; 971 dma-names = "tx", "rx"; 972 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 973 resets = <&cpg 207>; 974 status = "disabled"; 975 }; 976 977 scif1: serial@e6e68000 { 978 compatible = "renesas,scif-r8a7795", 979 "renesas,rcar-gen3-scif", "renesas,scif"; 980 reg = <0 0xe6e68000 0 64>; 981 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&cpg CPG_MOD 206>, 983 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 984 <&scif_clk>; 985 clock-names = "fck", "brg_int", "scif_clk"; 986 dmas = <&dmac1 0x53>, <&dmac1 0x52>; 987 dma-names = "tx", "rx"; 988 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 989 resets = <&cpg 206>; 990 status = "disabled"; 991 }; 992 993 scif2: serial@e6e88000 { 994 compatible = "renesas,scif-r8a7795", 995 "renesas,rcar-gen3-scif", "renesas,scif"; 996 reg = <0 0xe6e88000 0 64>; 997 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&cpg CPG_MOD 310>, 999 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1000 <&scif_clk>; 1001 clock-names = "fck", "brg_int", "scif_clk"; 1002 dmas = <&dmac1 0x13>, <&dmac1 0x12>; 1003 dma-names = "tx", "rx"; 1004 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1005 resets = <&cpg 310>; 1006 status = "disabled"; 1007 }; 1008 1009 scif3: serial@e6c50000 { 1010 compatible = "renesas,scif-r8a7795", 1011 "renesas,rcar-gen3-scif", "renesas,scif"; 1012 reg = <0 0xe6c50000 0 64>; 1013 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&cpg CPG_MOD 204>, 1015 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1016 <&scif_clk>; 1017 clock-names = "fck", "brg_int", "scif_clk"; 1018 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1019 dma-names = "tx", "rx"; 1020 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1021 resets = <&cpg 204>; 1022 status = "disabled"; 1023 }; 1024 1025 scif4: serial@e6c40000 { 1026 compatible = "renesas,scif-r8a7795", 1027 "renesas,rcar-gen3-scif", "renesas,scif"; 1028 reg = <0 0xe6c40000 0 64>; 1029 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&cpg CPG_MOD 203>, 1031 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1032 <&scif_clk>; 1033 clock-names = "fck", "brg_int", "scif_clk"; 1034 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1035 dma-names = "tx", "rx"; 1036 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1037 resets = <&cpg 203>; 1038 status = "disabled"; 1039 }; 1040 1041 scif5: serial@e6f30000 { 1042 compatible = "renesas,scif-r8a7795", 1043 "renesas,rcar-gen3-scif", "renesas,scif"; 1044 reg = <0 0xe6f30000 0 64>; 1045 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&cpg CPG_MOD 202>, 1047 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1048 <&scif_clk>; 1049 clock-names = "fck", "brg_int", "scif_clk"; 1050 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; 1051 dma-names = "tx", "rx"; 1052 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1053 resets = <&cpg 202>; 1054 status = "disabled"; 1055 }; 1056 1057 i2c_dvfs: i2c@e60b0000 { 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 compatible = "renesas,iic-r8a7795", 1061 "renesas,rcar-gen3-iic", 1062 "renesas,rmobile-iic"; 1063 reg = <0 0xe60b0000 0 0x425>; 1064 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cpg CPG_MOD 926>; 1066 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1067 resets = <&cpg 926>; 1068 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 1069 dma-names = "tx", "rx"; 1070 status = "disabled"; 1071 }; 1072 1073 i2c0: i2c@e6500000 { 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 compatible = "renesas,i2c-r8a7795", 1077 "renesas,rcar-gen3-i2c"; 1078 reg = <0 0xe6500000 0 0x40>; 1079 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&cpg CPG_MOD 931>; 1081 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1082 resets = <&cpg 931>; 1083 dmas = <&dmac1 0x91>, <&dmac1 0x90>; 1084 dma-names = "tx", "rx"; 1085 i2c-scl-internal-delay-ns = <110>; 1086 status = "disabled"; 1087 }; 1088 1089 i2c1: i2c@e6508000 { 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 compatible = "renesas,i2c-r8a7795", 1093 "renesas,rcar-gen3-i2c"; 1094 reg = <0 0xe6508000 0 0x40>; 1095 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&cpg CPG_MOD 930>; 1097 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1098 resets = <&cpg 930>; 1099 dmas = <&dmac1 0x93>, <&dmac1 0x92>; 1100 dma-names = "tx", "rx"; 1101 i2c-scl-internal-delay-ns = <6>; 1102 status = "disabled"; 1103 }; 1104 1105 i2c2: i2c@e6510000 { 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 compatible = "renesas,i2c-r8a7795", 1109 "renesas,rcar-gen3-i2c"; 1110 reg = <0 0xe6510000 0 0x40>; 1111 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&cpg CPG_MOD 929>; 1113 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1114 resets = <&cpg 929>; 1115 dmas = <&dmac1 0x95>, <&dmac1 0x94>; 1116 dma-names = "tx", "rx"; 1117 i2c-scl-internal-delay-ns = <6>; 1118 status = "disabled"; 1119 }; 1120 1121 i2c3: i2c@e66d0000 { 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 compatible = "renesas,i2c-r8a7795", 1125 "renesas,rcar-gen3-i2c"; 1126 reg = <0 0xe66d0000 0 0x40>; 1127 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&cpg CPG_MOD 928>; 1129 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1130 resets = <&cpg 928>; 1131 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 1132 dma-names = "tx", "rx"; 1133 i2c-scl-internal-delay-ns = <110>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c4: i2c@e66d8000 { 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 compatible = "renesas,i2c-r8a7795", 1141 "renesas,rcar-gen3-i2c"; 1142 reg = <0 0xe66d8000 0 0x40>; 1143 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cpg CPG_MOD 927>; 1145 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1146 resets = <&cpg 927>; 1147 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 1148 dma-names = "tx", "rx"; 1149 i2c-scl-internal-delay-ns = <110>; 1150 status = "disabled"; 1151 }; 1152 1153 i2c5: i2c@e66e0000 { 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 compatible = "renesas,i2c-r8a7795", 1157 "renesas,rcar-gen3-i2c"; 1158 reg = <0 0xe66e0000 0 0x40>; 1159 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&cpg CPG_MOD 919>; 1161 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1162 resets = <&cpg 919>; 1163 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 1164 dma-names = "tx", "rx"; 1165 i2c-scl-internal-delay-ns = <110>; 1166 status = "disabled"; 1167 }; 1168 1169 i2c6: i2c@e66e8000 { 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 compatible = "renesas,i2c-r8a7795", 1173 "renesas,rcar-gen3-i2c"; 1174 reg = <0 0xe66e8000 0 0x40>; 1175 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&cpg CPG_MOD 918>; 1177 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1178 resets = <&cpg 918>; 1179 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 1180 dma-names = "tx", "rx"; 1181 i2c-scl-internal-delay-ns = <6>; 1182 status = "disabled"; 1183 }; 1184 1185 pwm0: pwm@e6e30000 { 1186 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1187 reg = <0 0xe6e30000 0 0x8>; 1188 clocks = <&cpg CPG_MOD 523>; 1189 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1190 resets = <&cpg 523>; 1191 #pwm-cells = <2>; 1192 status = "disabled"; 1193 }; 1194 1195 pwm1: pwm@e6e31000 { 1196 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1197 reg = <0 0xe6e31000 0 0x8>; 1198 clocks = <&cpg CPG_MOD 523>; 1199 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1200 resets = <&cpg 523>; 1201 #pwm-cells = <2>; 1202 status = "disabled"; 1203 }; 1204 1205 pwm2: pwm@e6e32000 { 1206 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1207 reg = <0 0xe6e32000 0 0x8>; 1208 clocks = <&cpg CPG_MOD 523>; 1209 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1210 resets = <&cpg 523>; 1211 #pwm-cells = <2>; 1212 status = "disabled"; 1213 }; 1214 1215 pwm3: pwm@e6e33000 { 1216 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1217 reg = <0 0xe6e33000 0 0x8>; 1218 clocks = <&cpg CPG_MOD 523>; 1219 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1220 resets = <&cpg 523>; 1221 #pwm-cells = <2>; 1222 status = "disabled"; 1223 }; 1224 1225 pwm4: pwm@e6e34000 { 1226 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1227 reg = <0 0xe6e34000 0 0x8>; 1228 clocks = <&cpg CPG_MOD 523>; 1229 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1230 resets = <&cpg 523>; 1231 #pwm-cells = <2>; 1232 status = "disabled"; 1233 }; 1234 1235 pwm5: pwm@e6e35000 { 1236 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1237 reg = <0 0xe6e35000 0 0x8>; 1238 clocks = <&cpg CPG_MOD 523>; 1239 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1240 resets = <&cpg 523>; 1241 #pwm-cells = <2>; 1242 status = "disabled"; 1243 }; 1244 1245 pwm6: pwm@e6e36000 { 1246 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1247 reg = <0 0xe6e36000 0 0x8>; 1248 clocks = <&cpg CPG_MOD 523>; 1249 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1250 resets = <&cpg 523>; 1251 #pwm-cells = <2>; 1252 status = "disabled"; 1253 }; 1254 1255 rcar_sound: sound@ec500000 { 1256 /* 1257 * #sound-dai-cells is required 1258 * 1259 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1260 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1261 */ 1262 /* 1263 * #clock-cells is required for audio_clkout0/1/2/3 1264 * 1265 * clkout : #clock-cells = <0>; <&rcar_sound>; 1266 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1267 */ 1268 compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; 1269 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1270 <0 0xec5a0000 0 0x100>, /* ADG */ 1271 <0 0xec540000 0 0x1000>, /* SSIU */ 1272 <0 0xec541000 0 0x280>, /* SSI */ 1273 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1274 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1275 1276 clocks = <&cpg CPG_MOD 1005>, 1277 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1278 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1279 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1280 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1281 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1282 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1283 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1284 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1285 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1286 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1287 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1288 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1289 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1290 <&audio_clk_a>, <&audio_clk_b>, 1291 <&audio_clk_c>, 1292 <&cpg CPG_CORE R8A7795_CLK_S0D4>; 1293 clock-names = "ssi-all", 1294 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1295 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1296 "ssi.1", "ssi.0", 1297 "src.9", "src.8", "src.7", "src.6", 1298 "src.5", "src.4", "src.3", "src.2", 1299 "src.1", "src.0", 1300 "mix.1", "mix.0", 1301 "ctu.1", "ctu.0", 1302 "dvc.0", "dvc.1", 1303 "clk_a", "clk_b", "clk_c", "clk_i"; 1304 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1305 resets = <&cpg 1005>, 1306 <&cpg 1006>, <&cpg 1007>, 1307 <&cpg 1008>, <&cpg 1009>, 1308 <&cpg 1010>, <&cpg 1011>, 1309 <&cpg 1012>, <&cpg 1013>, 1310 <&cpg 1014>, <&cpg 1015>; 1311 reset-names = "ssi-all", 1312 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1313 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1314 "ssi.1", "ssi.0"; 1315 status = "disabled"; 1316 1317 rcar_sound,dvc { 1318 dvc0: dvc-0 { 1319 dmas = <&audma1 0xbc>; 1320 dma-names = "tx"; 1321 }; 1322 dvc1: dvc-1 { 1323 dmas = <&audma1 0xbe>; 1324 dma-names = "tx"; 1325 }; 1326 }; 1327 1328 rcar_sound,mix { 1329 mix0: mix-0 { }; 1330 mix1: mix-1 { }; 1331 }; 1332 1333 rcar_sound,ctu { 1334 ctu00: ctu-0 { }; 1335 ctu01: ctu-1 { }; 1336 ctu02: ctu-2 { }; 1337 ctu03: ctu-3 { }; 1338 ctu10: ctu-4 { }; 1339 ctu11: ctu-5 { }; 1340 ctu12: ctu-6 { }; 1341 ctu13: ctu-7 { }; 1342 }; 1343 1344 rcar_sound,src { 1345 src0: src-0 { 1346 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1347 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1348 dma-names = "rx", "tx"; 1349 }; 1350 src1: src-1 { 1351 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1352 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1353 dma-names = "rx", "tx"; 1354 }; 1355 src2: src-2 { 1356 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1357 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1358 dma-names = "rx", "tx"; 1359 }; 1360 src3: src-3 { 1361 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1362 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1363 dma-names = "rx", "tx"; 1364 }; 1365 src4: src-4 { 1366 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1367 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1368 dma-names = "rx", "tx"; 1369 }; 1370 src5: src-5 { 1371 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1372 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1373 dma-names = "rx", "tx"; 1374 }; 1375 src6: src-6 { 1376 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1377 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1378 dma-names = "rx", "tx"; 1379 }; 1380 src7: src-7 { 1381 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1382 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1383 dma-names = "rx", "tx"; 1384 }; 1385 src8: src-8 { 1386 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1387 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1388 dma-names = "rx", "tx"; 1389 }; 1390 src9: src-9 { 1391 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1392 dmas = <&audma0 0x97>, <&audma1 0xba>; 1393 dma-names = "rx", "tx"; 1394 }; 1395 }; 1396 1397 rcar_sound,ssi { 1398 ssi0: ssi-0 { 1399 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1400 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1401 dma-names = "rx", "tx", "rxu", "txu"; 1402 }; 1403 ssi1: ssi-1 { 1404 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1405 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1406 dma-names = "rx", "tx", "rxu", "txu"; 1407 }; 1408 ssi2: ssi-2 { 1409 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1410 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1411 dma-names = "rx", "tx", "rxu", "txu"; 1412 }; 1413 ssi3: ssi-3 { 1414 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1415 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1416 dma-names = "rx", "tx", "rxu", "txu"; 1417 }; 1418 ssi4: ssi-4 { 1419 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1420 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1421 dma-names = "rx", "tx", "rxu", "txu"; 1422 }; 1423 ssi5: ssi-5 { 1424 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1425 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1426 dma-names = "rx", "tx", "rxu", "txu"; 1427 }; 1428 ssi6: ssi-6 { 1429 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1430 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1431 dma-names = "rx", "tx", "rxu", "txu"; 1432 }; 1433 ssi7: ssi-7 { 1434 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1435 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1436 dma-names = "rx", "tx", "rxu", "txu"; 1437 }; 1438 ssi8: ssi-8 { 1439 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1440 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1441 dma-names = "rx", "tx", "rxu", "txu"; 1442 }; 1443 ssi9: ssi-9 { 1444 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1445 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1446 dma-names = "rx", "tx", "rxu", "txu"; 1447 }; 1448 }; 1449 }; 1450 1451 sata: sata@ee300000 { 1452 compatible = "renesas,sata-r8a7795", 1453 "renesas,rcar-gen3-sata"; 1454 reg = <0 0xee300000 0 0x200000>; 1455 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1456 clocks = <&cpg CPG_MOD 815>; 1457 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1458 resets = <&cpg 815>; 1459 status = "disabled"; 1460 }; 1461 1462 xhci0: usb@ee000000 { 1463 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; 1464 reg = <0 0xee000000 0 0xc00>; 1465 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1466 clocks = <&cpg CPG_MOD 328>; 1467 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1468 resets = <&cpg 328>; 1469 status = "disabled"; 1470 }; 1471 1472 usb_dmac0: dma-controller@e65a0000 { 1473 compatible = "renesas,r8a7795-usb-dmac", 1474 "renesas,usb-dmac"; 1475 reg = <0 0xe65a0000 0 0x100>; 1476 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 1477 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1478 interrupt-names = "ch0", "ch1"; 1479 clocks = <&cpg CPG_MOD 330>; 1480 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1481 resets = <&cpg 330>; 1482 #dma-cells = <1>; 1483 dma-channels = <2>; 1484 }; 1485 1486 usb_dmac1: dma-controller@e65b0000 { 1487 compatible = "renesas,r8a7795-usb-dmac", 1488 "renesas,usb-dmac"; 1489 reg = <0 0xe65b0000 0 0x100>; 1490 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 1491 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1492 interrupt-names = "ch0", "ch1"; 1493 clocks = <&cpg CPG_MOD 331>; 1494 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1495 resets = <&cpg 331>; 1496 #dma-cells = <1>; 1497 dma-channels = <2>; 1498 }; 1499 1500 usb_dmac2: dma-controller@e6460000 { 1501 compatible = "renesas,r8a7795-usb-dmac", 1502 "renesas,usb-dmac"; 1503 reg = <0 0xe6460000 0 0x100>; 1504 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 1505 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1506 interrupt-names = "ch0", "ch1"; 1507 clocks = <&cpg CPG_MOD 326>; 1508 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1509 resets = <&cpg 326>; 1510 #dma-cells = <1>; 1511 dma-channels = <2>; 1512 }; 1513 1514 usb_dmac3: dma-controller@e6470000 { 1515 compatible = "renesas,r8a7795-usb-dmac", 1516 "renesas,usb-dmac"; 1517 reg = <0 0xe6470000 0 0x100>; 1518 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 1519 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1520 interrupt-names = "ch0", "ch1"; 1521 clocks = <&cpg CPG_MOD 329>; 1522 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1523 resets = <&cpg 329>; 1524 #dma-cells = <1>; 1525 dma-channels = <2>; 1526 }; 1527 1528 sdhi0: sd@ee100000 { 1529 compatible = "renesas,sdhi-r8a7795"; 1530 reg = <0 0xee100000 0 0x2000>; 1531 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1532 clocks = <&cpg CPG_MOD 314>; 1533 max-frequency = <200000000>; 1534 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1535 resets = <&cpg 314>; 1536 status = "disabled"; 1537 }; 1538 1539 sdhi1: sd@ee120000 { 1540 compatible = "renesas,sdhi-r8a7795"; 1541 reg = <0 0xee120000 0 0x2000>; 1542 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&cpg CPG_MOD 313>; 1544 max-frequency = <200000000>; 1545 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1546 resets = <&cpg 313>; 1547 status = "disabled"; 1548 }; 1549 1550 sdhi2: sd@ee140000 { 1551 compatible = "renesas,sdhi-r8a7795"; 1552 reg = <0 0xee140000 0 0x2000>; 1553 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&cpg CPG_MOD 312>; 1555 max-frequency = <200000000>; 1556 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1557 resets = <&cpg 312>; 1558 status = "disabled"; 1559 }; 1560 1561 sdhi3: sd@ee160000 { 1562 compatible = "renesas,sdhi-r8a7795"; 1563 reg = <0 0xee160000 0 0x2000>; 1564 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&cpg CPG_MOD 311>; 1566 max-frequency = <200000000>; 1567 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1568 resets = <&cpg 311>; 1569 status = "disabled"; 1570 }; 1571 1572 usb2_phy0: usb-phy@ee080200 { 1573 compatible = "renesas,usb2-phy-r8a7795", 1574 "renesas,rcar-gen3-usb2-phy"; 1575 reg = <0 0xee080200 0 0x700>; 1576 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1577 clocks = <&cpg CPG_MOD 703>; 1578 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1579 resets = <&cpg 703>; 1580 #phy-cells = <0>; 1581 status = "disabled"; 1582 }; 1583 1584 usb2_phy1: usb-phy@ee0a0200 { 1585 compatible = "renesas,usb2-phy-r8a7795", 1586 "renesas,rcar-gen3-usb2-phy"; 1587 reg = <0 0xee0a0200 0 0x700>; 1588 clocks = <&cpg CPG_MOD 702>; 1589 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1590 resets = <&cpg 702>; 1591 #phy-cells = <0>; 1592 status = "disabled"; 1593 }; 1594 1595 usb2_phy2: usb-phy@ee0c0200 { 1596 compatible = "renesas,usb2-phy-r8a7795", 1597 "renesas,rcar-gen3-usb2-phy"; 1598 reg = <0 0xee0c0200 0 0x700>; 1599 clocks = <&cpg CPG_MOD 701>; 1600 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1601 resets = <&cpg 701>; 1602 #phy-cells = <0>; 1603 status = "disabled"; 1604 }; 1605 1606 usb2_phy3: usb-phy@ee0e0200 { 1607 compatible = "renesas,usb2-phy-r8a7795", 1608 "renesas,rcar-gen3-usb2-phy"; 1609 reg = <0 0xee0e0200 0 0x700>; 1610 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1611 clocks = <&cpg CPG_MOD 700>; 1612 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1613 resets = <&cpg 700>; 1614 #phy-cells = <0>; 1615 status = "disabled"; 1616 }; 1617 1618 ehci0: usb@ee080100 { 1619 compatible = "generic-ehci"; 1620 reg = <0 0xee080100 0 0x100>; 1621 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1622 clocks = <&cpg CPG_MOD 703>; 1623 phys = <&usb2_phy0>; 1624 phy-names = "usb"; 1625 companion = <&ohci0>; 1626 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1627 resets = <&cpg 703>; 1628 status = "disabled"; 1629 }; 1630 1631 ehci1: usb@ee0a0100 { 1632 compatible = "generic-ehci"; 1633 reg = <0 0xee0a0100 0 0x100>; 1634 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&cpg CPG_MOD 702>; 1636 phys = <&usb2_phy1>; 1637 phy-names = "usb"; 1638 companion = <&ohci1>; 1639 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1640 resets = <&cpg 702>; 1641 status = "disabled"; 1642 }; 1643 1644 ehci2: usb@ee0c0100 { 1645 compatible = "generic-ehci"; 1646 reg = <0 0xee0c0100 0 0x100>; 1647 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&cpg CPG_MOD 701>; 1649 phys = <&usb2_phy2>; 1650 phy-names = "usb"; 1651 companion = <&ohci2>; 1652 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1653 resets = <&cpg 701>; 1654 status = "disabled"; 1655 }; 1656 1657 ehci3: usb@ee0e0100 { 1658 compatible = "generic-ehci"; 1659 reg = <0 0xee0e0100 0 0x100>; 1660 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1661 clocks = <&cpg CPG_MOD 700>; 1662 phys = <&usb2_phy3>; 1663 phy-names = "usb"; 1664 companion = <&ohci3>; 1665 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1666 resets = <&cpg 700>; 1667 status = "disabled"; 1668 }; 1669 1670 ohci0: usb@ee080000 { 1671 compatible = "generic-ohci"; 1672 reg = <0 0xee080000 0 0x100>; 1673 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1674 clocks = <&cpg CPG_MOD 703>; 1675 phys = <&usb2_phy0>; 1676 phy-names = "usb"; 1677 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1678 resets = <&cpg 703>; 1679 status = "disabled"; 1680 }; 1681 1682 ohci1: usb@ee0a0000 { 1683 compatible = "generic-ohci"; 1684 reg = <0 0xee0a0000 0 0x100>; 1685 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1686 clocks = <&cpg CPG_MOD 702>; 1687 phys = <&usb2_phy1>; 1688 phy-names = "usb"; 1689 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1690 resets = <&cpg 702>; 1691 status = "disabled"; 1692 }; 1693 1694 ohci2: usb@ee0c0000 { 1695 compatible = "generic-ohci"; 1696 reg = <0 0xee0c0000 0 0x100>; 1697 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1698 clocks = <&cpg CPG_MOD 701>; 1699 phys = <&usb2_phy2>; 1700 phy-names = "usb"; 1701 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1702 resets = <&cpg 701>; 1703 status = "disabled"; 1704 }; 1705 1706 ohci3: usb@ee0e0000 { 1707 compatible = "generic-ohci"; 1708 reg = <0 0xee0e0000 0 0x100>; 1709 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1710 clocks = <&cpg CPG_MOD 700>; 1711 phys = <&usb2_phy3>; 1712 phy-names = "usb"; 1713 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1714 resets = <&cpg 700>; 1715 status = "disabled"; 1716 }; 1717 1718 hsusb: usb@e6590000 { 1719 compatible = "renesas,usbhs-r8a7795", 1720 "renesas,rcar-gen3-usbhs"; 1721 reg = <0 0xe6590000 0 0x100>; 1722 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1723 clocks = <&cpg CPG_MOD 704>; 1724 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 1725 <&usb_dmac1 0>, <&usb_dmac1 1>; 1726 dma-names = "ch0", "ch1", "ch2", "ch3"; 1727 renesas,buswait = <11>; 1728 phys = <&usb2_phy0>; 1729 phy-names = "usb"; 1730 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1731 resets = <&cpg 704>; 1732 status = "disabled"; 1733 }; 1734 1735 hsusb3: usb@e659c000 { 1736 compatible = "renesas,usbhs-r8a7795", 1737 "renesas,rcar-gen3-usbhs"; 1738 reg = <0 0xe659c000 0 0x100>; 1739 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1740 clocks = <&cpg CPG_MOD 705>; 1741 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, 1742 <&usb_dmac3 0>, <&usb_dmac3 1>; 1743 dma-names = "ch0", "ch1", "ch2", "ch3"; 1744 renesas,buswait = <11>; 1745 phys = <&usb2_phy3>; 1746 phy-names = "usb"; 1747 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1748 resets = <&cpg 705>; 1749 status = "disabled"; 1750 }; 1751 1752 pciec0: pcie@fe000000 { 1753 compatible = "renesas,pcie-r8a7795", 1754 "renesas,pcie-rcar-gen3"; 1755 reg = <0 0xfe000000 0 0x80000>; 1756 #address-cells = <3>; 1757 #size-cells = <2>; 1758 bus-range = <0x00 0xff>; 1759 device_type = "pci"; 1760 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1761 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1762 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1763 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1764 /* Map all possible DDR as inbound ranges */ 1765 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1766 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1769 #interrupt-cells = <1>; 1770 interrupt-map-mask = <0 0 0 0>; 1771 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1772 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1773 clock-names = "pcie", "pcie_bus"; 1774 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1775 resets = <&cpg 319>; 1776 status = "disabled"; 1777 }; 1778 1779 pciec1: pcie@ee800000 { 1780 compatible = "renesas,pcie-r8a7795", 1781 "renesas,pcie-rcar-gen3"; 1782 reg = <0 0xee800000 0 0x80000>; 1783 #address-cells = <3>; 1784 #size-cells = <2>; 1785 bus-range = <0x00 0xff>; 1786 device_type = "pci"; 1787 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 1788 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 1789 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 1790 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 1791 /* Map all possible DDR as inbound ranges */ 1792 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1793 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1796 #interrupt-cells = <1>; 1797 interrupt-map-mask = <0 0 0 0>; 1798 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1799 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 1800 clock-names = "pcie", "pcie_bus"; 1801 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1802 resets = <&cpg 318>; 1803 status = "disabled"; 1804 }; 1805 1806 imr-lx4@fe860000 { 1807 compatible = "renesas,r8a7795-imr-lx4", 1808 "renesas,imr-lx4"; 1809 reg = <0 0xfe860000 0 0x2000>; 1810 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1811 clocks = <&cpg CPG_MOD 823>; 1812 power-domains = <&sysc R8A7795_PD_A3VC>; 1813 resets = <&cpg 823>; 1814 }; 1815 1816 imr-lx4@fe870000 { 1817 compatible = "renesas,r8a7795-imr-lx4", 1818 "renesas,imr-lx4"; 1819 reg = <0 0xfe870000 0 0x2000>; 1820 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&cpg CPG_MOD 822>; 1822 power-domains = <&sysc R8A7795_PD_A3VC>; 1823 resets = <&cpg 822>; 1824 }; 1825 1826 imr-lx4@fe880000 { 1827 compatible = "renesas,r8a7795-imr-lx4", 1828 "renesas,imr-lx4"; 1829 reg = <0 0xfe880000 0 0x2000>; 1830 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1831 clocks = <&cpg CPG_MOD 821>; 1832 power-domains = <&sysc R8A7795_PD_A3VC>; 1833 resets = <&cpg 821>; 1834 }; 1835 1836 imr-lx4@fe890000 { 1837 compatible = "renesas,r8a7795-imr-lx4", 1838 "renesas,imr-lx4"; 1839 reg = <0 0xfe890000 0 0x2000>; 1840 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1841 clocks = <&cpg CPG_MOD 820>; 1842 power-domains = <&sysc R8A7795_PD_A3VC>; 1843 resets = <&cpg 820>; 1844 }; 1845 1846 vspbc: vsp@fe920000 { 1847 compatible = "renesas,vsp2"; 1848 reg = <0 0xfe920000 0 0x8000>; 1849 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1850 clocks = <&cpg CPG_MOD 624>; 1851 power-domains = <&sysc R8A7795_PD_A3VP>; 1852 resets = <&cpg 624>; 1853 1854 renesas,fcp = <&fcpvb1>; 1855 }; 1856 1857 fcpvb1: fcp@fe92f000 { 1858 compatible = "renesas,fcpv"; 1859 reg = <0 0xfe92f000 0 0x200>; 1860 clocks = <&cpg CPG_MOD 606>; 1861 power-domains = <&sysc R8A7795_PD_A3VP>; 1862 resets = <&cpg 606>; 1863 }; 1864 1865 fcpf0: fcp@fe950000 { 1866 compatible = "renesas,fcpf"; 1867 reg = <0 0xfe950000 0 0x200>; 1868 clocks = <&cpg CPG_MOD 615>; 1869 power-domains = <&sysc R8A7795_PD_A3VP>; 1870 resets = <&cpg 615>; 1871 }; 1872 1873 fcpf1: fcp@fe951000 { 1874 compatible = "renesas,fcpf"; 1875 reg = <0 0xfe951000 0 0x200>; 1876 clocks = <&cpg CPG_MOD 614>; 1877 power-domains = <&sysc R8A7795_PD_A3VP>; 1878 resets = <&cpg 614>; 1879 }; 1880 1881 vspbd: vsp@fe960000 { 1882 compatible = "renesas,vsp2"; 1883 reg = <0 0xfe960000 0 0x8000>; 1884 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1885 clocks = <&cpg CPG_MOD 626>; 1886 power-domains = <&sysc R8A7795_PD_A3VP>; 1887 resets = <&cpg 626>; 1888 1889 renesas,fcp = <&fcpvb0>; 1890 }; 1891 1892 fcpvb0: fcp@fe96f000 { 1893 compatible = "renesas,fcpv"; 1894 reg = <0 0xfe96f000 0 0x200>; 1895 clocks = <&cpg CPG_MOD 607>; 1896 power-domains = <&sysc R8A7795_PD_A3VP>; 1897 resets = <&cpg 607>; 1898 }; 1899 1900 vspi0: vsp@fe9a0000 { 1901 compatible = "renesas,vsp2"; 1902 reg = <0 0xfe9a0000 0 0x8000>; 1903 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1904 clocks = <&cpg CPG_MOD 631>; 1905 power-domains = <&sysc R8A7795_PD_A3VP>; 1906 resets = <&cpg 631>; 1907 1908 renesas,fcp = <&fcpvi0>; 1909 }; 1910 1911 fcpvi0: fcp@fe9af000 { 1912 compatible = "renesas,fcpv"; 1913 reg = <0 0xfe9af000 0 0x200>; 1914 clocks = <&cpg CPG_MOD 611>; 1915 power-domains = <&sysc R8A7795_PD_A3VP>; 1916 resets = <&cpg 611>; 1917 }; 1918 1919 vspi1: vsp@fe9b0000 { 1920 compatible = "renesas,vsp2"; 1921 reg = <0 0xfe9b0000 0 0x8000>; 1922 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 1923 clocks = <&cpg CPG_MOD 630>; 1924 power-domains = <&sysc R8A7795_PD_A3VP>; 1925 resets = <&cpg 630>; 1926 1927 renesas,fcp = <&fcpvi1>; 1928 }; 1929 1930 fcpvi1: fcp@fe9bf000 { 1931 compatible = "renesas,fcpv"; 1932 reg = <0 0xfe9bf000 0 0x200>; 1933 clocks = <&cpg CPG_MOD 610>; 1934 power-domains = <&sysc R8A7795_PD_A3VP>; 1935 resets = <&cpg 610>; 1936 }; 1937 1938 vspd0: vsp@fea20000 { 1939 compatible = "renesas,vsp2"; 1940 reg = <0 0xfea20000 0 0x4000>; 1941 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1942 clocks = <&cpg CPG_MOD 623>; 1943 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1944 resets = <&cpg 623>; 1945 1946 renesas,fcp = <&fcpvd0>; 1947 }; 1948 1949 fcpvd0: fcp@fea27000 { 1950 compatible = "renesas,fcpv"; 1951 reg = <0 0xfea27000 0 0x200>; 1952 clocks = <&cpg CPG_MOD 603>; 1953 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1954 resets = <&cpg 603>; 1955 }; 1956 1957 vspd1: vsp@fea28000 { 1958 compatible = "renesas,vsp2"; 1959 reg = <0 0xfea28000 0 0x4000>; 1960 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1961 clocks = <&cpg CPG_MOD 622>; 1962 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1963 resets = <&cpg 622>; 1964 1965 renesas,fcp = <&fcpvd1>; 1966 }; 1967 1968 fcpvd1: fcp@fea2f000 { 1969 compatible = "renesas,fcpv"; 1970 reg = <0 0xfea2f000 0 0x200>; 1971 clocks = <&cpg CPG_MOD 602>; 1972 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1973 resets = <&cpg 602>; 1974 }; 1975 1976 vspd2: vsp@fea30000 { 1977 compatible = "renesas,vsp2"; 1978 reg = <0 0xfea30000 0 0x4000>; 1979 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1980 clocks = <&cpg CPG_MOD 621>; 1981 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1982 resets = <&cpg 621>; 1983 1984 renesas,fcp = <&fcpvd2>; 1985 }; 1986 1987 fcpvd2: fcp@fea37000 { 1988 compatible = "renesas,fcpv"; 1989 reg = <0 0xfea37000 0 0x200>; 1990 clocks = <&cpg CPG_MOD 601>; 1991 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1992 resets = <&cpg 601>; 1993 }; 1994 1995 fdp1@fe940000 { 1996 compatible = "renesas,fdp1"; 1997 reg = <0 0xfe940000 0 0x2400>; 1998 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1999 clocks = <&cpg CPG_MOD 119>; 2000 power-domains = <&sysc R8A7795_PD_A3VP>; 2001 resets = <&cpg 119>; 2002 renesas,fcp = <&fcpf0>; 2003 }; 2004 2005 fdp1@fe944000 { 2006 compatible = "renesas,fdp1"; 2007 reg = <0 0xfe944000 0 0x2400>; 2008 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2009 clocks = <&cpg CPG_MOD 118>; 2010 power-domains = <&sysc R8A7795_PD_A3VP>; 2011 resets = <&cpg 118>; 2012 renesas,fcp = <&fcpf1>; 2013 }; 2014 2015 hdmi0: hdmi0@fead0000 { 2016 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 2017 reg = <0 0xfead0000 0 0x10000>; 2018 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2019 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; 2020 clock-names = "iahb", "isfr"; 2021 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2022 resets = <&cpg 729>; 2023 status = "disabled"; 2024 2025 ports { 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 port@0 { 2029 reg = <0>; 2030 dw_hdmi0_in: endpoint { 2031 remote-endpoint = <&du_out_hdmi0>; 2032 }; 2033 }; 2034 port@1 { 2035 reg = <1>; 2036 }; 2037 }; 2038 }; 2039 2040 hdmi1: hdmi1@feae0000 { 2041 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 2042 reg = <0 0xfeae0000 0 0x10000>; 2043 interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; 2044 clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; 2045 clock-names = "iahb", "isfr"; 2046 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2047 resets = <&cpg 728>; 2048 status = "disabled"; 2049 2050 ports { 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 port@0 { 2054 reg = <0>; 2055 dw_hdmi1_in: endpoint { 2056 remote-endpoint = <&du_out_hdmi1>; 2057 }; 2058 }; 2059 port@1 { 2060 reg = <1>; 2061 }; 2062 }; 2063 }; 2064 2065 du: display@feb00000 { 2066 compatible = "renesas,du-r8a7795"; 2067 reg = <0 0xfeb00000 0 0x80000>, 2068 <0 0xfeb90000 0 0x14>; 2069 reg-names = "du", "lvds.0"; 2070 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 2074 clocks = <&cpg CPG_MOD 724>, 2075 <&cpg CPG_MOD 723>, 2076 <&cpg CPG_MOD 722>, 2077 <&cpg CPG_MOD 721>, 2078 <&cpg CPG_MOD 727>; 2079 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; 2080 vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>; 2081 status = "disabled"; 2082 2083 ports { 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 2087 port@0 { 2088 reg = <0>; 2089 du_out_rgb: endpoint { 2090 }; 2091 }; 2092 port@1 { 2093 reg = <1>; 2094 du_out_hdmi0: endpoint { 2095 remote-endpoint = <&dw_hdmi0_in>; 2096 }; 2097 }; 2098 port@2 { 2099 reg = <2>; 2100 du_out_hdmi1: endpoint { 2101 remote-endpoint = <&dw_hdmi1_in>; 2102 }; 2103 }; 2104 port@3 { 2105 reg = <3>; 2106 du_out_lvds0: endpoint { 2107 }; 2108 }; 2109 }; 2110 }; 2111 2112 tsc: thermal@e6198000 { 2113 compatible = "renesas,r8a7795-thermal"; 2114 reg = <0 0xe6198000 0 0x68>, 2115 <0 0xe61a0000 0 0x5c>, 2116 <0 0xe61a8000 0 0x5c>; 2117 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 2120 clocks = <&cpg CPG_MOD 522>; 2121 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2122 resets = <&cpg 522>; 2123 #thermal-sensor-cells = <1>; 2124 status = "okay"; 2125 }; 2126 2127 thermal-zones { 2128 sensor_thermal1: sensor-thermal1 { 2129 polling-delay-passive = <250>; 2130 polling-delay = <1000>; 2131 thermal-sensors = <&tsc 0>; 2132 2133 trips { 2134 sensor1_crit: sensor1-crit { 2135 temperature = <120000>; 2136 hysteresis = <2000>; 2137 type = "critical"; 2138 }; 2139 }; 2140 }; 2141 2142 sensor_thermal2: sensor-thermal2 { 2143 polling-delay-passive = <250>; 2144 polling-delay = <1000>; 2145 thermal-sensors = <&tsc 1>; 2146 2147 trips { 2148 sensor2_crit: sensor2-crit { 2149 temperature = <120000>; 2150 hysteresis = <2000>; 2151 type = "critical"; 2152 }; 2153 }; 2154 }; 2155 2156 sensor_thermal3: sensor-thermal3 { 2157 polling-delay-passive = <250>; 2158 polling-delay = <1000>; 2159 thermal-sensors = <&tsc 2>; 2160 2161 trips { 2162 sensor3_crit: sensor3-crit { 2163 temperature = <120000>; 2164 hysteresis = <2000>; 2165 type = "critical"; 2166 }; 2167 }; 2168 }; 2169 }; 2170 }; 2171}; 2172