1*9a26fc5aSMarek Vasut/* 2*9a26fc5aSMarek Vasut * Device Tree Source for the Alt board 3*9a26fc5aSMarek Vasut * 4*9a26fc5aSMarek Vasut * Copyright (C) 2014 Renesas Electronics Corporation 5*9a26fc5aSMarek Vasut * 6*9a26fc5aSMarek Vasut * SPDX-License-Identifier: GPL-2.0 7*9a26fc5aSMarek Vasut */ 8*9a26fc5aSMarek Vasut 9*9a26fc5aSMarek Vasut/dts-v1/; 10*9a26fc5aSMarek Vasut#include "r8a7794.dtsi" 11*9a26fc5aSMarek Vasut#include <dt-bindings/gpio/gpio.h> 12*9a26fc5aSMarek Vasut 13*9a26fc5aSMarek Vasut/ { 14*9a26fc5aSMarek Vasut model = "Alt"; 15*9a26fc5aSMarek Vasut compatible = "renesas,alt", "renesas,r8a7794"; 16*9a26fc5aSMarek Vasut 17*9a26fc5aSMarek Vasut aliases { 18*9a26fc5aSMarek Vasut serial0 = &scif2; 19*9a26fc5aSMarek Vasut i2c10 = &gpioi2c4; 20*9a26fc5aSMarek Vasut i2c12 = &i2cexio4; 21*9a26fc5aSMarek Vasut }; 22*9a26fc5aSMarek Vasut 23*9a26fc5aSMarek Vasut chosen { 24*9a26fc5aSMarek Vasut bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; 25*9a26fc5aSMarek Vasut stdout-path = "serial0:115200n8"; 26*9a26fc5aSMarek Vasut }; 27*9a26fc5aSMarek Vasut 28*9a26fc5aSMarek Vasut memory@40000000 { 29*9a26fc5aSMarek Vasut device_type = "memory"; 30*9a26fc5aSMarek Vasut reg = <0 0x40000000 0 0x40000000>; 31*9a26fc5aSMarek Vasut }; 32*9a26fc5aSMarek Vasut 33*9a26fc5aSMarek Vasut d3_3v: regulator-d3-3v { 34*9a26fc5aSMarek Vasut compatible = "regulator-fixed"; 35*9a26fc5aSMarek Vasut regulator-name = "D3.3V"; 36*9a26fc5aSMarek Vasut regulator-min-microvolt = <3300000>; 37*9a26fc5aSMarek Vasut regulator-max-microvolt = <3300000>; 38*9a26fc5aSMarek Vasut regulator-boot-on; 39*9a26fc5aSMarek Vasut regulator-always-on; 40*9a26fc5aSMarek Vasut }; 41*9a26fc5aSMarek Vasut 42*9a26fc5aSMarek Vasut vcc_sdhi0: regulator-vcc-sdhi0 { 43*9a26fc5aSMarek Vasut compatible = "regulator-fixed"; 44*9a26fc5aSMarek Vasut 45*9a26fc5aSMarek Vasut regulator-name = "SDHI0 Vcc"; 46*9a26fc5aSMarek Vasut regulator-min-microvolt = <3300000>; 47*9a26fc5aSMarek Vasut regulator-max-microvolt = <3300000>; 48*9a26fc5aSMarek Vasut 49*9a26fc5aSMarek Vasut gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; 50*9a26fc5aSMarek Vasut enable-active-high; 51*9a26fc5aSMarek Vasut }; 52*9a26fc5aSMarek Vasut 53*9a26fc5aSMarek Vasut vccq_sdhi0: regulator-vccq-sdhi0 { 54*9a26fc5aSMarek Vasut compatible = "regulator-gpio"; 55*9a26fc5aSMarek Vasut 56*9a26fc5aSMarek Vasut regulator-name = "SDHI0 VccQ"; 57*9a26fc5aSMarek Vasut regulator-min-microvolt = <1800000>; 58*9a26fc5aSMarek Vasut regulator-max-microvolt = <3300000>; 59*9a26fc5aSMarek Vasut 60*9a26fc5aSMarek Vasut gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; 61*9a26fc5aSMarek Vasut gpios-states = <1>; 62*9a26fc5aSMarek Vasut states = <3300000 1 63*9a26fc5aSMarek Vasut 1800000 0>; 64*9a26fc5aSMarek Vasut }; 65*9a26fc5aSMarek Vasut 66*9a26fc5aSMarek Vasut vcc_sdhi1: regulator-vcc-sdhi1 { 67*9a26fc5aSMarek Vasut compatible = "regulator-fixed"; 68*9a26fc5aSMarek Vasut 69*9a26fc5aSMarek Vasut regulator-name = "SDHI1 Vcc"; 70*9a26fc5aSMarek Vasut regulator-min-microvolt = <3300000>; 71*9a26fc5aSMarek Vasut regulator-max-microvolt = <3300000>; 72*9a26fc5aSMarek Vasut 73*9a26fc5aSMarek Vasut gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; 74*9a26fc5aSMarek Vasut enable-active-high; 75*9a26fc5aSMarek Vasut }; 76*9a26fc5aSMarek Vasut 77*9a26fc5aSMarek Vasut vccq_sdhi1: regulator-vccq-sdhi1 { 78*9a26fc5aSMarek Vasut compatible = "regulator-gpio"; 79*9a26fc5aSMarek Vasut 80*9a26fc5aSMarek Vasut regulator-name = "SDHI1 VccQ"; 81*9a26fc5aSMarek Vasut regulator-min-microvolt = <1800000>; 82*9a26fc5aSMarek Vasut regulator-max-microvolt = <3300000>; 83*9a26fc5aSMarek Vasut 84*9a26fc5aSMarek Vasut gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 85*9a26fc5aSMarek Vasut gpios-states = <1>; 86*9a26fc5aSMarek Vasut states = <3300000 1 87*9a26fc5aSMarek Vasut 1800000 0>; 88*9a26fc5aSMarek Vasut }; 89*9a26fc5aSMarek Vasut 90*9a26fc5aSMarek Vasut lbsc { 91*9a26fc5aSMarek Vasut #address-cells = <1>; 92*9a26fc5aSMarek Vasut #size-cells = <1>; 93*9a26fc5aSMarek Vasut }; 94*9a26fc5aSMarek Vasut 95*9a26fc5aSMarek Vasut vga-encoder { 96*9a26fc5aSMarek Vasut compatible = "adi,adv7123"; 97*9a26fc5aSMarek Vasut 98*9a26fc5aSMarek Vasut ports { 99*9a26fc5aSMarek Vasut #address-cells = <1>; 100*9a26fc5aSMarek Vasut #size-cells = <0>; 101*9a26fc5aSMarek Vasut 102*9a26fc5aSMarek Vasut port@0 { 103*9a26fc5aSMarek Vasut reg = <0>; 104*9a26fc5aSMarek Vasut adv7123_in: endpoint { 105*9a26fc5aSMarek Vasut remote-endpoint = <&du_out_rgb1>; 106*9a26fc5aSMarek Vasut }; 107*9a26fc5aSMarek Vasut }; 108*9a26fc5aSMarek Vasut port@1 { 109*9a26fc5aSMarek Vasut reg = <1>; 110*9a26fc5aSMarek Vasut adv7123_out: endpoint { 111*9a26fc5aSMarek Vasut remote-endpoint = <&vga_in>; 112*9a26fc5aSMarek Vasut }; 113*9a26fc5aSMarek Vasut }; 114*9a26fc5aSMarek Vasut }; 115*9a26fc5aSMarek Vasut }; 116*9a26fc5aSMarek Vasut 117*9a26fc5aSMarek Vasut vga { 118*9a26fc5aSMarek Vasut compatible = "vga-connector"; 119*9a26fc5aSMarek Vasut 120*9a26fc5aSMarek Vasut port { 121*9a26fc5aSMarek Vasut vga_in: endpoint { 122*9a26fc5aSMarek Vasut remote-endpoint = <&adv7123_out>; 123*9a26fc5aSMarek Vasut }; 124*9a26fc5aSMarek Vasut }; 125*9a26fc5aSMarek Vasut }; 126*9a26fc5aSMarek Vasut 127*9a26fc5aSMarek Vasut x2_clk: x2-clock { 128*9a26fc5aSMarek Vasut compatible = "fixed-clock"; 129*9a26fc5aSMarek Vasut #clock-cells = <0>; 130*9a26fc5aSMarek Vasut clock-frequency = <74250000>; 131*9a26fc5aSMarek Vasut }; 132*9a26fc5aSMarek Vasut 133*9a26fc5aSMarek Vasut x13_clk: x13-clock { 134*9a26fc5aSMarek Vasut compatible = "fixed-clock"; 135*9a26fc5aSMarek Vasut #clock-cells = <0>; 136*9a26fc5aSMarek Vasut clock-frequency = <148500000>; 137*9a26fc5aSMarek Vasut }; 138*9a26fc5aSMarek Vasut 139*9a26fc5aSMarek Vasut gpioi2c4: i2c-10 { 140*9a26fc5aSMarek Vasut #address-cells = <1>; 141*9a26fc5aSMarek Vasut #size-cells = <0>; 142*9a26fc5aSMarek Vasut compatible = "i2c-gpio"; 143*9a26fc5aSMarek Vasut status = "disabled"; 144*9a26fc5aSMarek Vasut gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */ 145*9a26fc5aSMarek Vasut &gpio4 8 GPIO_ACTIVE_HIGH /* scl */ 146*9a26fc5aSMarek Vasut >; 147*9a26fc5aSMarek Vasut i2c-gpio,delay-us = <5>; 148*9a26fc5aSMarek Vasut }; 149*9a26fc5aSMarek Vasut 150*9a26fc5aSMarek Vasut /* 151*9a26fc5aSMarek Vasut * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA). 152*9a26fc5aSMarek Vasut * A fallback to GPIO is provided. 153*9a26fc5aSMarek Vasut */ 154*9a26fc5aSMarek Vasut i2cexio4: i2c-14 { 155*9a26fc5aSMarek Vasut compatible = "i2c-demux-pinctrl"; 156*9a26fc5aSMarek Vasut i2c-parent = <&i2c4>, <&gpioi2c4>; 157*9a26fc5aSMarek Vasut i2c-bus-name = "i2c-exio4"; 158*9a26fc5aSMarek Vasut #address-cells = <1>; 159*9a26fc5aSMarek Vasut #size-cells = <0>; 160*9a26fc5aSMarek Vasut }; 161*9a26fc5aSMarek Vasut}; 162*9a26fc5aSMarek Vasut 163*9a26fc5aSMarek Vasut&du { 164*9a26fc5aSMarek Vasut pinctrl-0 = <&du_pins>; 165*9a26fc5aSMarek Vasut pinctrl-names = "default"; 166*9a26fc5aSMarek Vasut status = "okay"; 167*9a26fc5aSMarek Vasut 168*9a26fc5aSMarek Vasut clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 169*9a26fc5aSMarek Vasut <&x13_clk>, <&x2_clk>; 170*9a26fc5aSMarek Vasut clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; 171*9a26fc5aSMarek Vasut 172*9a26fc5aSMarek Vasut ports { 173*9a26fc5aSMarek Vasut port@1 { 174*9a26fc5aSMarek Vasut endpoint { 175*9a26fc5aSMarek Vasut remote-endpoint = <&adv7123_in>; 176*9a26fc5aSMarek Vasut }; 177*9a26fc5aSMarek Vasut }; 178*9a26fc5aSMarek Vasut }; 179*9a26fc5aSMarek Vasut}; 180*9a26fc5aSMarek Vasut 181*9a26fc5aSMarek Vasut&extal_clk { 182*9a26fc5aSMarek Vasut clock-frequency = <20000000>; 183*9a26fc5aSMarek Vasut}; 184*9a26fc5aSMarek Vasut 185*9a26fc5aSMarek Vasut&pfc { 186*9a26fc5aSMarek Vasut pinctrl-0 = <&scif_clk_pins>; 187*9a26fc5aSMarek Vasut pinctrl-names = "default"; 188*9a26fc5aSMarek Vasut 189*9a26fc5aSMarek Vasut du_pins: du { 190*9a26fc5aSMarek Vasut groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; 191*9a26fc5aSMarek Vasut function = "du1"; 192*9a26fc5aSMarek Vasut }; 193*9a26fc5aSMarek Vasut 194*9a26fc5aSMarek Vasut scif2_pins: scif2 { 195*9a26fc5aSMarek Vasut groups = "scif2_data"; 196*9a26fc5aSMarek Vasut function = "scif2"; 197*9a26fc5aSMarek Vasut }; 198*9a26fc5aSMarek Vasut 199*9a26fc5aSMarek Vasut scif_clk_pins: scif_clk { 200*9a26fc5aSMarek Vasut groups = "scif_clk"; 201*9a26fc5aSMarek Vasut function = "scif_clk"; 202*9a26fc5aSMarek Vasut }; 203*9a26fc5aSMarek Vasut 204*9a26fc5aSMarek Vasut ether_pins: ether { 205*9a26fc5aSMarek Vasut groups = "eth_link", "eth_mdio", "eth_rmii"; 206*9a26fc5aSMarek Vasut function = "eth"; 207*9a26fc5aSMarek Vasut }; 208*9a26fc5aSMarek Vasut 209*9a26fc5aSMarek Vasut phy1_pins: phy1 { 210*9a26fc5aSMarek Vasut groups = "intc_irq8"; 211*9a26fc5aSMarek Vasut function = "intc"; 212*9a26fc5aSMarek Vasut }; 213*9a26fc5aSMarek Vasut 214*9a26fc5aSMarek Vasut i2c1_pins: i2c1 { 215*9a26fc5aSMarek Vasut groups = "i2c1"; 216*9a26fc5aSMarek Vasut function = "i2c1"; 217*9a26fc5aSMarek Vasut }; 218*9a26fc5aSMarek Vasut 219*9a26fc5aSMarek Vasut i2c4_pins: i2c4 { 220*9a26fc5aSMarek Vasut groups = "i2c4"; 221*9a26fc5aSMarek Vasut function = "i2c4"; 222*9a26fc5aSMarek Vasut }; 223*9a26fc5aSMarek Vasut 224*9a26fc5aSMarek Vasut vin0_pins: vin0 { 225*9a26fc5aSMarek Vasut groups = "vin0_data8", "vin0_clk"; 226*9a26fc5aSMarek Vasut function = "vin0"; 227*9a26fc5aSMarek Vasut }; 228*9a26fc5aSMarek Vasut 229*9a26fc5aSMarek Vasut mmcif0_pins: mmcif0 { 230*9a26fc5aSMarek Vasut groups = "mmc_data8", "mmc_ctrl"; 231*9a26fc5aSMarek Vasut function = "mmc"; 232*9a26fc5aSMarek Vasut }; 233*9a26fc5aSMarek Vasut 234*9a26fc5aSMarek Vasut sdhi0_pins: sd0 { 235*9a26fc5aSMarek Vasut groups = "sdhi0_data4", "sdhi0_ctrl"; 236*9a26fc5aSMarek Vasut function = "sdhi0"; 237*9a26fc5aSMarek Vasut power-source = <3300>; 238*9a26fc5aSMarek Vasut }; 239*9a26fc5aSMarek Vasut 240*9a26fc5aSMarek Vasut sdhi0_pins_uhs: sd0_uhs { 241*9a26fc5aSMarek Vasut groups = "sdhi0_data4", "sdhi0_ctrl"; 242*9a26fc5aSMarek Vasut function = "sdhi0"; 243*9a26fc5aSMarek Vasut power-source = <1800>; 244*9a26fc5aSMarek Vasut }; 245*9a26fc5aSMarek Vasut 246*9a26fc5aSMarek Vasut sdhi1_pins: sd1 { 247*9a26fc5aSMarek Vasut groups = "sdhi1_data4", "sdhi1_ctrl"; 248*9a26fc5aSMarek Vasut function = "sdhi1"; 249*9a26fc5aSMarek Vasut power-source = <3300>; 250*9a26fc5aSMarek Vasut }; 251*9a26fc5aSMarek Vasut 252*9a26fc5aSMarek Vasut sdhi1_pins_uhs: sd1_uhs { 253*9a26fc5aSMarek Vasut groups = "sdhi1_data4", "sdhi1_ctrl"; 254*9a26fc5aSMarek Vasut function = "sdhi1"; 255*9a26fc5aSMarek Vasut power-source = <1800>; 256*9a26fc5aSMarek Vasut }; 257*9a26fc5aSMarek Vasut}; 258*9a26fc5aSMarek Vasut 259*9a26fc5aSMarek Vasut&cmt0 { 260*9a26fc5aSMarek Vasut status = "okay"; 261*9a26fc5aSMarek Vasut}; 262*9a26fc5aSMarek Vasut 263*9a26fc5aSMarek Vasut&pfc { 264*9a26fc5aSMarek Vasut qspi_pins: qspi { 265*9a26fc5aSMarek Vasut groups = "qspi_ctrl", "qspi_data4"; 266*9a26fc5aSMarek Vasut function = "qspi"; 267*9a26fc5aSMarek Vasut }; 268*9a26fc5aSMarek Vasut}; 269*9a26fc5aSMarek Vasut 270*9a26fc5aSMarek Vasutðer { 271*9a26fc5aSMarek Vasut pinctrl-0 = <ðer_pins &phy1_pins>; 272*9a26fc5aSMarek Vasut pinctrl-names = "default"; 273*9a26fc5aSMarek Vasut 274*9a26fc5aSMarek Vasut phy-handle = <&phy1>; 275*9a26fc5aSMarek Vasut renesas,ether-link-active-low; 276*9a26fc5aSMarek Vasut status = "okay"; 277*9a26fc5aSMarek Vasut 278*9a26fc5aSMarek Vasut phy1: ethernet-phy@1 { 279*9a26fc5aSMarek Vasut reg = <1>; 280*9a26fc5aSMarek Vasut interrupt-parent = <&irqc0>; 281*9a26fc5aSMarek Vasut interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 282*9a26fc5aSMarek Vasut micrel,led-mode = <1>; 283*9a26fc5aSMarek Vasut }; 284*9a26fc5aSMarek Vasut}; 285*9a26fc5aSMarek Vasut 286*9a26fc5aSMarek Vasut&mmcif0 { 287*9a26fc5aSMarek Vasut pinctrl-0 = <&mmcif0_pins>; 288*9a26fc5aSMarek Vasut pinctrl-names = "default"; 289*9a26fc5aSMarek Vasut 290*9a26fc5aSMarek Vasut vmmc-supply = <&d3_3v>; 291*9a26fc5aSMarek Vasut vqmmc-supply = <&d3_3v>; 292*9a26fc5aSMarek Vasut bus-width = <8>; 293*9a26fc5aSMarek Vasut non-removable; 294*9a26fc5aSMarek Vasut status = "okay"; 295*9a26fc5aSMarek Vasut}; 296*9a26fc5aSMarek Vasut 297*9a26fc5aSMarek Vasut&sdhi0 { 298*9a26fc5aSMarek Vasut pinctrl-0 = <&sdhi0_pins>; 299*9a26fc5aSMarek Vasut pinctrl-1 = <&sdhi0_pins_uhs>; 300*9a26fc5aSMarek Vasut pinctrl-names = "default", "state_uhs"; 301*9a26fc5aSMarek Vasut 302*9a26fc5aSMarek Vasut vmmc-supply = <&vcc_sdhi0>; 303*9a26fc5aSMarek Vasut vqmmc-supply = <&vccq_sdhi0>; 304*9a26fc5aSMarek Vasut cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; 305*9a26fc5aSMarek Vasut wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; 306*9a26fc5aSMarek Vasut sd-uhs-sdr50; 307*9a26fc5aSMarek Vasut sd-uhs-sdr104; 308*9a26fc5aSMarek Vasut status = "okay"; 309*9a26fc5aSMarek Vasut}; 310*9a26fc5aSMarek Vasut 311*9a26fc5aSMarek Vasut&sdhi1 { 312*9a26fc5aSMarek Vasut pinctrl-0 = <&sdhi1_pins>; 313*9a26fc5aSMarek Vasut pinctrl-1 = <&sdhi1_pins_uhs>; 314*9a26fc5aSMarek Vasut pinctrl-names = "default", "state_uhs"; 315*9a26fc5aSMarek Vasut 316*9a26fc5aSMarek Vasut vmmc-supply = <&vcc_sdhi1>; 317*9a26fc5aSMarek Vasut vqmmc-supply = <&vccq_sdhi1>; 318*9a26fc5aSMarek Vasut cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; 319*9a26fc5aSMarek Vasut wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; 320*9a26fc5aSMarek Vasut sd-uhs-sdr50; 321*9a26fc5aSMarek Vasut status = "okay"; 322*9a26fc5aSMarek Vasut}; 323*9a26fc5aSMarek Vasut 324*9a26fc5aSMarek Vasut&i2c1 { 325*9a26fc5aSMarek Vasut pinctrl-0 = <&i2c1_pins>; 326*9a26fc5aSMarek Vasut pinctrl-names = "default"; 327*9a26fc5aSMarek Vasut 328*9a26fc5aSMarek Vasut status = "okay"; 329*9a26fc5aSMarek Vasut clock-frequency = <400000>; 330*9a26fc5aSMarek Vasut 331*9a26fc5aSMarek Vasut composite-in@20 { 332*9a26fc5aSMarek Vasut compatible = "adi,adv7180"; 333*9a26fc5aSMarek Vasut reg = <0x20>; 334*9a26fc5aSMarek Vasut remote = <&vin0>; 335*9a26fc5aSMarek Vasut 336*9a26fc5aSMarek Vasut port { 337*9a26fc5aSMarek Vasut adv7180: endpoint { 338*9a26fc5aSMarek Vasut bus-width = <8>; 339*9a26fc5aSMarek Vasut remote-endpoint = <&vin0ep>; 340*9a26fc5aSMarek Vasut }; 341*9a26fc5aSMarek Vasut }; 342*9a26fc5aSMarek Vasut }; 343*9a26fc5aSMarek Vasut}; 344*9a26fc5aSMarek Vasut 345*9a26fc5aSMarek Vasut&i2c4 { 346*9a26fc5aSMarek Vasut pinctrl-0 = <&i2c4_pins>; 347*9a26fc5aSMarek Vasut pinctrl-names = "i2c-exio4"; 348*9a26fc5aSMarek Vasut}; 349*9a26fc5aSMarek Vasut 350*9a26fc5aSMarek Vasut&vin0 { 351*9a26fc5aSMarek Vasut status = "okay"; 352*9a26fc5aSMarek Vasut pinctrl-0 = <&vin0_pins>; 353*9a26fc5aSMarek Vasut pinctrl-names = "default"; 354*9a26fc5aSMarek Vasut 355*9a26fc5aSMarek Vasut port { 356*9a26fc5aSMarek Vasut #address-cells = <1>; 357*9a26fc5aSMarek Vasut #size-cells = <0>; 358*9a26fc5aSMarek Vasut 359*9a26fc5aSMarek Vasut vin0ep: endpoint { 360*9a26fc5aSMarek Vasut remote-endpoint = <&adv7180>; 361*9a26fc5aSMarek Vasut bus-width = <8>; 362*9a26fc5aSMarek Vasut }; 363*9a26fc5aSMarek Vasut }; 364*9a26fc5aSMarek Vasut}; 365*9a26fc5aSMarek Vasut 366*9a26fc5aSMarek Vasut&scif2 { 367*9a26fc5aSMarek Vasut pinctrl-0 = <&scif2_pins>; 368*9a26fc5aSMarek Vasut pinctrl-names = "default"; 369*9a26fc5aSMarek Vasut 370*9a26fc5aSMarek Vasut status = "okay"; 371*9a26fc5aSMarek Vasut}; 372*9a26fc5aSMarek Vasut 373*9a26fc5aSMarek Vasut&scif_clk { 374*9a26fc5aSMarek Vasut clock-frequency = <14745600>; 375*9a26fc5aSMarek Vasut}; 376*9a26fc5aSMarek Vasut 377*9a26fc5aSMarek Vasut&qspi { 378*9a26fc5aSMarek Vasut pinctrl-0 = <&qspi_pins>; 379*9a26fc5aSMarek Vasut pinctrl-names = "default"; 380*9a26fc5aSMarek Vasut 381*9a26fc5aSMarek Vasut status = "okay"; 382*9a26fc5aSMarek Vasut 383*9a26fc5aSMarek Vasut flash@0 { 384*9a26fc5aSMarek Vasut compatible = "spansion,s25fl512s", "jedec,spi-nor"; 385*9a26fc5aSMarek Vasut reg = <0>; 386*9a26fc5aSMarek Vasut spi-max-frequency = <30000000>; 387*9a26fc5aSMarek Vasut spi-tx-bus-width = <4>; 388*9a26fc5aSMarek Vasut spi-rx-bus-width = <4>; 389*9a26fc5aSMarek Vasut spi-cpol; 390*9a26fc5aSMarek Vasut spi-cpha; 391*9a26fc5aSMarek Vasut m25p,fast-read; 392*9a26fc5aSMarek Vasut 393*9a26fc5aSMarek Vasut partitions { 394*9a26fc5aSMarek Vasut compatible = "fixed-partitions"; 395*9a26fc5aSMarek Vasut #address-cells = <1>; 396*9a26fc5aSMarek Vasut #size-cells = <1>; 397*9a26fc5aSMarek Vasut 398*9a26fc5aSMarek Vasut partition@0 { 399*9a26fc5aSMarek Vasut label = "loader"; 400*9a26fc5aSMarek Vasut reg = <0x00000000 0x00040000>; 401*9a26fc5aSMarek Vasut read-only; 402*9a26fc5aSMarek Vasut }; 403*9a26fc5aSMarek Vasut partition@40000 { 404*9a26fc5aSMarek Vasut label = "system"; 405*9a26fc5aSMarek Vasut reg = <0x00040000 0x00040000>; 406*9a26fc5aSMarek Vasut read-only; 407*9a26fc5aSMarek Vasut }; 408*9a26fc5aSMarek Vasut partition@80000 { 409*9a26fc5aSMarek Vasut label = "user"; 410*9a26fc5aSMarek Vasut reg = <0x00080000 0x03f80000>; 411*9a26fc5aSMarek Vasut }; 412*9a26fc5aSMarek Vasut }; 413*9a26fc5aSMarek Vasut }; 414*9a26fc5aSMarek Vasut}; 415