183d290c5STom Rini// SPDX-License-Identifier: GPL-2.0 2a3fb9ff3SMarek Vasut/* 3a3fb9ff3SMarek Vasut * Device Tree Source for the r8a7792 SoC 4a3fb9ff3SMarek Vasut * 5a3fb9ff3SMarek Vasut * Copyright (C) 2016 Cogent Embedded Inc. 6a3fb9ff3SMarek Vasut */ 7a3fb9ff3SMarek Vasut 8a3fb9ff3SMarek Vasut#include <dt-bindings/clock/r8a7792-cpg-mssr.h> 9a3fb9ff3SMarek Vasut#include <dt-bindings/interrupt-controller/irq.h> 10a3fb9ff3SMarek Vasut#include <dt-bindings/interrupt-controller/arm-gic.h> 11a3fb9ff3SMarek Vasut#include <dt-bindings/power/r8a7792-sysc.h> 12a3fb9ff3SMarek Vasut 13a3fb9ff3SMarek Vasut/ { 14a3fb9ff3SMarek Vasut compatible = "renesas,r8a7792"; 15a3fb9ff3SMarek Vasut #address-cells = <2>; 16a3fb9ff3SMarek Vasut #size-cells = <2>; 17a3fb9ff3SMarek Vasut 18a3fb9ff3SMarek Vasut aliases { 19a3fb9ff3SMarek Vasut i2c0 = &i2c0; 20a3fb9ff3SMarek Vasut i2c1 = &i2c1; 21a3fb9ff3SMarek Vasut i2c2 = &i2c2; 22a3fb9ff3SMarek Vasut i2c3 = &i2c3; 23a3fb9ff3SMarek Vasut i2c4 = &i2c4; 24a3fb9ff3SMarek Vasut i2c5 = &i2c5; 25a3fb9ff3SMarek Vasut spi0 = &qspi; 26a3fb9ff3SMarek Vasut spi1 = &msiof0; 27a3fb9ff3SMarek Vasut spi2 = &msiof1; 28a3fb9ff3SMarek Vasut vin0 = &vin0; 29a3fb9ff3SMarek Vasut vin1 = &vin1; 30a3fb9ff3SMarek Vasut vin2 = &vin2; 31a3fb9ff3SMarek Vasut vin3 = &vin3; 32a3fb9ff3SMarek Vasut vin4 = &vin4; 33a3fb9ff3SMarek Vasut vin5 = &vin5; 34a3fb9ff3SMarek Vasut }; 35a3fb9ff3SMarek Vasut 36*252c8b45SMarek Vasut /* External CAN clock */ 37*252c8b45SMarek Vasut can_clk: can { 38*252c8b45SMarek Vasut compatible = "fixed-clock"; 39*252c8b45SMarek Vasut #clock-cells = <0>; 40*252c8b45SMarek Vasut /* This value must be overridden by the board. */ 41*252c8b45SMarek Vasut clock-frequency = <0>; 42*252c8b45SMarek Vasut }; 43*252c8b45SMarek Vasut 44a3fb9ff3SMarek Vasut cpus { 45a3fb9ff3SMarek Vasut #address-cells = <1>; 46a3fb9ff3SMarek Vasut #size-cells = <0>; 47a3fb9ff3SMarek Vasut enable-method = "renesas,apmu"; 48a3fb9ff3SMarek Vasut 49a3fb9ff3SMarek Vasut cpu0: cpu@0 { 50a3fb9ff3SMarek Vasut device_type = "cpu"; 51a3fb9ff3SMarek Vasut compatible = "arm,cortex-a15"; 52a3fb9ff3SMarek Vasut reg = <0>; 53a3fb9ff3SMarek Vasut clock-frequency = <1000000000>; 54a3fb9ff3SMarek Vasut clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 55a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 56a3fb9ff3SMarek Vasut next-level-cache = <&L2_CA15>; 57a3fb9ff3SMarek Vasut }; 58a3fb9ff3SMarek Vasut 59a3fb9ff3SMarek Vasut cpu1: cpu@1 { 60a3fb9ff3SMarek Vasut device_type = "cpu"; 61a3fb9ff3SMarek Vasut compatible = "arm,cortex-a15"; 62a3fb9ff3SMarek Vasut reg = <1>; 63a3fb9ff3SMarek Vasut clock-frequency = <1000000000>; 64a3fb9ff3SMarek Vasut clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 65a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 66a3fb9ff3SMarek Vasut next-level-cache = <&L2_CA15>; 67a3fb9ff3SMarek Vasut }; 68a3fb9ff3SMarek Vasut 69a3fb9ff3SMarek Vasut L2_CA15: cache-controller-0 { 70a3fb9ff3SMarek Vasut compatible = "cache"; 71a3fb9ff3SMarek Vasut cache-unified; 72a3fb9ff3SMarek Vasut cache-level = <2>; 73a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_CA15_SCU>; 74a3fb9ff3SMarek Vasut }; 75a3fb9ff3SMarek Vasut }; 76a3fb9ff3SMarek Vasut 77*252c8b45SMarek Vasut /* External root clock */ 78*252c8b45SMarek Vasut extal_clk: extal { 79*252c8b45SMarek Vasut compatible = "fixed-clock"; 80*252c8b45SMarek Vasut #clock-cells = <0>; 81*252c8b45SMarek Vasut /* This value must be overridden by the board. */ 82*252c8b45SMarek Vasut clock-frequency = <0>; 83*252c8b45SMarek Vasut }; 84*252c8b45SMarek Vasut 85*252c8b45SMarek Vasut /* External SCIF clock */ 86*252c8b45SMarek Vasut scif_clk: scif { 87*252c8b45SMarek Vasut compatible = "fixed-clock"; 88*252c8b45SMarek Vasut #clock-cells = <0>; 89*252c8b45SMarek Vasut /* This value must be overridden by the board. */ 90*252c8b45SMarek Vasut clock-frequency = <0>; 91*252c8b45SMarek Vasut }; 92*252c8b45SMarek Vasut 93a3fb9ff3SMarek Vasut soc { 94a3fb9ff3SMarek Vasut compatible = "simple-bus"; 95a3fb9ff3SMarek Vasut interrupt-parent = <&gic>; 96a3fb9ff3SMarek Vasut 97a3fb9ff3SMarek Vasut #address-cells = <2>; 98a3fb9ff3SMarek Vasut #size-cells = <2>; 99a3fb9ff3SMarek Vasut ranges; 100a3fb9ff3SMarek Vasut 101a3fb9ff3SMarek Vasut gpio0: gpio@e6050000 { 102a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 103a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 104a3fb9ff3SMarek Vasut reg = <0 0xe6050000 0 0x50>; 105a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 106a3fb9ff3SMarek Vasut #gpio-cells = <2>; 107a3fb9ff3SMarek Vasut gpio-controller; 108a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 0 29>; 109a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 110a3fb9ff3SMarek Vasut interrupt-controller; 111a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 912>; 112a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 113a3fb9ff3SMarek Vasut resets = <&cpg 912>; 114a3fb9ff3SMarek Vasut }; 115a3fb9ff3SMarek Vasut 116a3fb9ff3SMarek Vasut gpio1: gpio@e6051000 { 117a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 118a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 119a3fb9ff3SMarek Vasut reg = <0 0xe6051000 0 0x50>; 120a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 121a3fb9ff3SMarek Vasut #gpio-cells = <2>; 122a3fb9ff3SMarek Vasut gpio-controller; 123a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 32 23>; 124a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 125a3fb9ff3SMarek Vasut interrupt-controller; 126a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 911>; 127a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 128a3fb9ff3SMarek Vasut resets = <&cpg 911>; 129a3fb9ff3SMarek Vasut }; 130a3fb9ff3SMarek Vasut 131a3fb9ff3SMarek Vasut gpio2: gpio@e6052000 { 132a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 133a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 134a3fb9ff3SMarek Vasut reg = <0 0xe6052000 0 0x50>; 135a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 136a3fb9ff3SMarek Vasut #gpio-cells = <2>; 137a3fb9ff3SMarek Vasut gpio-controller; 138a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 64 32>; 139a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 140a3fb9ff3SMarek Vasut interrupt-controller; 141a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 910>; 142a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 143a3fb9ff3SMarek Vasut resets = <&cpg 910>; 144a3fb9ff3SMarek Vasut }; 145a3fb9ff3SMarek Vasut 146a3fb9ff3SMarek Vasut gpio3: gpio@e6053000 { 147a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 148a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 149a3fb9ff3SMarek Vasut reg = <0 0xe6053000 0 0x50>; 150a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 151a3fb9ff3SMarek Vasut #gpio-cells = <2>; 152a3fb9ff3SMarek Vasut gpio-controller; 153a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 96 28>; 154a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 155a3fb9ff3SMarek Vasut interrupt-controller; 156a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 909>; 157a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 158a3fb9ff3SMarek Vasut resets = <&cpg 909>; 159a3fb9ff3SMarek Vasut }; 160a3fb9ff3SMarek Vasut 161a3fb9ff3SMarek Vasut gpio4: gpio@e6054000 { 162a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 163a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 164a3fb9ff3SMarek Vasut reg = <0 0xe6054000 0 0x50>; 165a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 166a3fb9ff3SMarek Vasut #gpio-cells = <2>; 167a3fb9ff3SMarek Vasut gpio-controller; 168a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 128 17>; 169a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 170a3fb9ff3SMarek Vasut interrupt-controller; 171a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 908>; 172a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 173a3fb9ff3SMarek Vasut resets = <&cpg 908>; 174a3fb9ff3SMarek Vasut }; 175a3fb9ff3SMarek Vasut 176a3fb9ff3SMarek Vasut gpio5: gpio@e6055000 { 177a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 178a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 179a3fb9ff3SMarek Vasut reg = <0 0xe6055000 0 0x50>; 180a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 181a3fb9ff3SMarek Vasut #gpio-cells = <2>; 182a3fb9ff3SMarek Vasut gpio-controller; 183a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 160 17>; 184a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 185a3fb9ff3SMarek Vasut interrupt-controller; 186a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 907>; 187a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 188a3fb9ff3SMarek Vasut resets = <&cpg 907>; 189a3fb9ff3SMarek Vasut }; 190a3fb9ff3SMarek Vasut 191a3fb9ff3SMarek Vasut gpio6: gpio@e6055100 { 192a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 193a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 194a3fb9ff3SMarek Vasut reg = <0 0xe6055100 0 0x50>; 195a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 196a3fb9ff3SMarek Vasut #gpio-cells = <2>; 197a3fb9ff3SMarek Vasut gpio-controller; 198a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 192 17>; 199a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 200a3fb9ff3SMarek Vasut interrupt-controller; 201a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 905>; 202a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 203a3fb9ff3SMarek Vasut resets = <&cpg 905>; 204a3fb9ff3SMarek Vasut }; 205a3fb9ff3SMarek Vasut 206a3fb9ff3SMarek Vasut gpio7: gpio@e6055200 { 207a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 208a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 209a3fb9ff3SMarek Vasut reg = <0 0xe6055200 0 0x50>; 210a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 211a3fb9ff3SMarek Vasut #gpio-cells = <2>; 212a3fb9ff3SMarek Vasut gpio-controller; 213a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 224 17>; 214a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 215a3fb9ff3SMarek Vasut interrupt-controller; 216a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 904>; 217a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 218a3fb9ff3SMarek Vasut resets = <&cpg 904>; 219a3fb9ff3SMarek Vasut }; 220a3fb9ff3SMarek Vasut 221a3fb9ff3SMarek Vasut gpio8: gpio@e6055300 { 222a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 223a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 224a3fb9ff3SMarek Vasut reg = <0 0xe6055300 0 0x50>; 225a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 226a3fb9ff3SMarek Vasut #gpio-cells = <2>; 227a3fb9ff3SMarek Vasut gpio-controller; 228a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 256 17>; 229a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 230a3fb9ff3SMarek Vasut interrupt-controller; 231a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 921>; 232a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 233a3fb9ff3SMarek Vasut resets = <&cpg 921>; 234a3fb9ff3SMarek Vasut }; 235a3fb9ff3SMarek Vasut 236a3fb9ff3SMarek Vasut gpio9: gpio@e6055400 { 237a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 238a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 239a3fb9ff3SMarek Vasut reg = <0 0xe6055400 0 0x50>; 240a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 241a3fb9ff3SMarek Vasut #gpio-cells = <2>; 242a3fb9ff3SMarek Vasut gpio-controller; 243a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 288 17>; 244a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 245a3fb9ff3SMarek Vasut interrupt-controller; 246a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 919>; 247a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 248a3fb9ff3SMarek Vasut resets = <&cpg 919>; 249a3fb9ff3SMarek Vasut }; 250a3fb9ff3SMarek Vasut 251a3fb9ff3SMarek Vasut gpio10: gpio@e6055500 { 252a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 253a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 254a3fb9ff3SMarek Vasut reg = <0 0xe6055500 0 0x50>; 255a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 256a3fb9ff3SMarek Vasut #gpio-cells = <2>; 257a3fb9ff3SMarek Vasut gpio-controller; 258a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 320 32>; 259a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 260a3fb9ff3SMarek Vasut interrupt-controller; 261a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 914>; 262a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 263a3fb9ff3SMarek Vasut resets = <&cpg 914>; 264a3fb9ff3SMarek Vasut }; 265a3fb9ff3SMarek Vasut 266a3fb9ff3SMarek Vasut gpio11: gpio@e6055600 { 267a3fb9ff3SMarek Vasut compatible = "renesas,gpio-r8a7792", 268a3fb9ff3SMarek Vasut "renesas,rcar-gen2-gpio"; 269a3fb9ff3SMarek Vasut reg = <0 0xe6055600 0 0x50>; 270a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 271a3fb9ff3SMarek Vasut #gpio-cells = <2>; 272a3fb9ff3SMarek Vasut gpio-controller; 273a3fb9ff3SMarek Vasut gpio-ranges = <&pfc 0 352 30>; 274a3fb9ff3SMarek Vasut #interrupt-cells = <2>; 275a3fb9ff3SMarek Vasut interrupt-controller; 276a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 913>; 277a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 278a3fb9ff3SMarek Vasut resets = <&cpg 913>; 279a3fb9ff3SMarek Vasut }; 280a3fb9ff3SMarek Vasut 281*252c8b45SMarek Vasut pfc: pin-controller@e6060000 { 282*252c8b45SMarek Vasut compatible = "renesas,pfc-r8a7792"; 283*252c8b45SMarek Vasut reg = <0 0xe6060000 0 0x144>; 284*252c8b45SMarek Vasut }; 285*252c8b45SMarek Vasut 286*252c8b45SMarek Vasut cpg: clock-controller@e6150000 { 287*252c8b45SMarek Vasut compatible = "renesas,r8a7792-cpg-mssr"; 288*252c8b45SMarek Vasut reg = <0 0xe6150000 0 0x1000>; 289*252c8b45SMarek Vasut clocks = <&extal_clk>; 290*252c8b45SMarek Vasut clock-names = "extal"; 291*252c8b45SMarek Vasut #clock-cells = <2>; 292*252c8b45SMarek Vasut #power-domain-cells = <0>; 293*252c8b45SMarek Vasut #reset-cells = <1>; 294*252c8b45SMarek Vasut }; 295*252c8b45SMarek Vasut 296*252c8b45SMarek Vasut apmu@e6152000 { 297*252c8b45SMarek Vasut compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 298*252c8b45SMarek Vasut reg = <0 0xe6152000 0 0x188>; 299*252c8b45SMarek Vasut cpus = <&cpu0 &cpu1>; 300*252c8b45SMarek Vasut }; 301*252c8b45SMarek Vasut 302*252c8b45SMarek Vasut rst: reset-controller@e6160000 { 303*252c8b45SMarek Vasut compatible = "renesas,r8a7792-rst"; 304*252c8b45SMarek Vasut reg = <0 0xe6160000 0 0x0100>; 305*252c8b45SMarek Vasut }; 306*252c8b45SMarek Vasut 307*252c8b45SMarek Vasut sysc: system-controller@e6180000 { 308*252c8b45SMarek Vasut compatible = "renesas,r8a7792-sysc"; 309*252c8b45SMarek Vasut reg = <0 0xe6180000 0 0x0200>; 310*252c8b45SMarek Vasut #power-domain-cells = <1>; 311*252c8b45SMarek Vasut }; 312*252c8b45SMarek Vasut 313*252c8b45SMarek Vasut irqc: interrupt-controller@e61c0000 { 314*252c8b45SMarek Vasut compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 315*252c8b45SMarek Vasut #interrupt-cells = <2>; 316*252c8b45SMarek Vasut interrupt-controller; 317*252c8b45SMarek Vasut reg = <0 0xe61c0000 0 0x200>; 318*252c8b45SMarek Vasut interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 319*252c8b45SMarek Vasut <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 320*252c8b45SMarek Vasut <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 321*252c8b45SMarek Vasut <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 322*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 407>; 323*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 324*252c8b45SMarek Vasut resets = <&cpg 407>; 325*252c8b45SMarek Vasut }; 326*252c8b45SMarek Vasut 327*252c8b45SMarek Vasut icram0: sram@e63a0000 { 328*252c8b45SMarek Vasut compatible = "mmio-sram"; 329*252c8b45SMarek Vasut reg = <0 0xe63a0000 0 0x12000>; 330*252c8b45SMarek Vasut }; 331*252c8b45SMarek Vasut 332*252c8b45SMarek Vasut icram1: sram@e63c0000 { 333*252c8b45SMarek Vasut compatible = "mmio-sram"; 334*252c8b45SMarek Vasut reg = <0 0xe63c0000 0 0x1000>; 335*252c8b45SMarek Vasut #address-cells = <1>; 336*252c8b45SMarek Vasut #size-cells = <1>; 337*252c8b45SMarek Vasut ranges = <0 0 0xe63c0000 0x1000>; 338*252c8b45SMarek Vasut 339*252c8b45SMarek Vasut smp-sram@0 { 340*252c8b45SMarek Vasut compatible = "renesas,smp-sram"; 341*252c8b45SMarek Vasut reg = <0 0x10>; 342*252c8b45SMarek Vasut }; 343*252c8b45SMarek Vasut }; 344*252c8b45SMarek Vasut 345*252c8b45SMarek Vasut /* I2C doesn't need pinmux */ 346*252c8b45SMarek Vasut i2c0: i2c@e6508000 { 347*252c8b45SMarek Vasut compatible = "renesas,i2c-r8a7792", 348*252c8b45SMarek Vasut "renesas,rcar-gen2-i2c"; 349*252c8b45SMarek Vasut reg = <0 0xe6508000 0 0x40>; 350*252c8b45SMarek Vasut interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 351*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 931>; 352*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 353*252c8b45SMarek Vasut resets = <&cpg 931>; 354*252c8b45SMarek Vasut i2c-scl-internal-delay-ns = <6>; 355*252c8b45SMarek Vasut #address-cells = <1>; 356*252c8b45SMarek Vasut #size-cells = <0>; 357*252c8b45SMarek Vasut status = "disabled"; 358*252c8b45SMarek Vasut }; 359*252c8b45SMarek Vasut 360*252c8b45SMarek Vasut i2c1: i2c@e6518000 { 361*252c8b45SMarek Vasut compatible = "renesas,i2c-r8a7792", 362*252c8b45SMarek Vasut "renesas,rcar-gen2-i2c"; 363*252c8b45SMarek Vasut reg = <0 0xe6518000 0 0x40>; 364*252c8b45SMarek Vasut interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 365*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 930>; 366*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 367*252c8b45SMarek Vasut resets = <&cpg 930>; 368*252c8b45SMarek Vasut i2c-scl-internal-delay-ns = <6>; 369*252c8b45SMarek Vasut #address-cells = <1>; 370*252c8b45SMarek Vasut #size-cells = <0>; 371*252c8b45SMarek Vasut status = "disabled"; 372*252c8b45SMarek Vasut }; 373*252c8b45SMarek Vasut 374*252c8b45SMarek Vasut i2c2: i2c@e6530000 { 375*252c8b45SMarek Vasut compatible = "renesas,i2c-r8a7792", 376*252c8b45SMarek Vasut "renesas,rcar-gen2-i2c"; 377*252c8b45SMarek Vasut reg = <0 0xe6530000 0 0x40>; 378*252c8b45SMarek Vasut interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 379*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 929>; 380*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 381*252c8b45SMarek Vasut resets = <&cpg 929>; 382*252c8b45SMarek Vasut i2c-scl-internal-delay-ns = <6>; 383*252c8b45SMarek Vasut #address-cells = <1>; 384*252c8b45SMarek Vasut #size-cells = <0>; 385*252c8b45SMarek Vasut status = "disabled"; 386*252c8b45SMarek Vasut }; 387*252c8b45SMarek Vasut 388*252c8b45SMarek Vasut i2c3: i2c@e6540000 { 389*252c8b45SMarek Vasut compatible = "renesas,i2c-r8a7792", 390*252c8b45SMarek Vasut "renesas,rcar-gen2-i2c"; 391*252c8b45SMarek Vasut reg = <0 0xe6540000 0 0x40>; 392*252c8b45SMarek Vasut interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 393*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 928>; 394*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 395*252c8b45SMarek Vasut resets = <&cpg 928>; 396*252c8b45SMarek Vasut i2c-scl-internal-delay-ns = <6>; 397*252c8b45SMarek Vasut #address-cells = <1>; 398*252c8b45SMarek Vasut #size-cells = <0>; 399*252c8b45SMarek Vasut status = "disabled"; 400*252c8b45SMarek Vasut }; 401*252c8b45SMarek Vasut 402*252c8b45SMarek Vasut i2c4: i2c@e6520000 { 403*252c8b45SMarek Vasut compatible = "renesas,i2c-r8a7792", 404*252c8b45SMarek Vasut "renesas,rcar-gen2-i2c"; 405*252c8b45SMarek Vasut reg = <0 0xe6520000 0 0x40>; 406*252c8b45SMarek Vasut interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 407*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 927>; 408*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 409*252c8b45SMarek Vasut resets = <&cpg 927>; 410*252c8b45SMarek Vasut i2c-scl-internal-delay-ns = <6>; 411*252c8b45SMarek Vasut #address-cells = <1>; 412*252c8b45SMarek Vasut #size-cells = <0>; 413*252c8b45SMarek Vasut status = "disabled"; 414*252c8b45SMarek Vasut }; 415*252c8b45SMarek Vasut 416*252c8b45SMarek Vasut i2c5: i2c@e6528000 { 417*252c8b45SMarek Vasut compatible = "renesas,i2c-r8a7792", 418*252c8b45SMarek Vasut "renesas,rcar-gen2-i2c"; 419*252c8b45SMarek Vasut reg = <0 0xe6528000 0 0x40>; 420*252c8b45SMarek Vasut interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 421*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 925>; 422*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 423*252c8b45SMarek Vasut resets = <&cpg 925>; 424*252c8b45SMarek Vasut i2c-scl-internal-delay-ns = <110>; 425*252c8b45SMarek Vasut #address-cells = <1>; 426*252c8b45SMarek Vasut #size-cells = <0>; 427*252c8b45SMarek Vasut status = "disabled"; 428*252c8b45SMarek Vasut }; 429*252c8b45SMarek Vasut 430a3fb9ff3SMarek Vasut dmac0: dma-controller@e6700000 { 431a3fb9ff3SMarek Vasut compatible = "renesas,dmac-r8a7792", 432a3fb9ff3SMarek Vasut "renesas,rcar-dmac"; 433a3fb9ff3SMarek Vasut reg = <0 0xe6700000 0 0x20000>; 434a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 435a3fb9ff3SMarek Vasut GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 436a3fb9ff3SMarek Vasut GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 437a3fb9ff3SMarek Vasut GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 438a3fb9ff3SMarek Vasut GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 439a3fb9ff3SMarek Vasut GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 440a3fb9ff3SMarek Vasut GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 441a3fb9ff3SMarek Vasut GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 442a3fb9ff3SMarek Vasut GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 443a3fb9ff3SMarek Vasut GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 444a3fb9ff3SMarek Vasut GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 445a3fb9ff3SMarek Vasut GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 446a3fb9ff3SMarek Vasut GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 447a3fb9ff3SMarek Vasut GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 448a3fb9ff3SMarek Vasut GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 449a3fb9ff3SMarek Vasut GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 450a3fb9ff3SMarek Vasut interrupt-names = "error", 451a3fb9ff3SMarek Vasut "ch0", "ch1", "ch2", "ch3", 452a3fb9ff3SMarek Vasut "ch4", "ch5", "ch6", "ch7", 453a3fb9ff3SMarek Vasut "ch8", "ch9", "ch10", "ch11", 454a3fb9ff3SMarek Vasut "ch12", "ch13", "ch14"; 455a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 219>; 456a3fb9ff3SMarek Vasut clock-names = "fck"; 457a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 458a3fb9ff3SMarek Vasut resets = <&cpg 219>; 459a3fb9ff3SMarek Vasut #dma-cells = <1>; 460a3fb9ff3SMarek Vasut dma-channels = <15>; 461a3fb9ff3SMarek Vasut }; 462a3fb9ff3SMarek Vasut 463a3fb9ff3SMarek Vasut dmac1: dma-controller@e6720000 { 464a3fb9ff3SMarek Vasut compatible = "renesas,dmac-r8a7792", 465a3fb9ff3SMarek Vasut "renesas,rcar-dmac"; 466a3fb9ff3SMarek Vasut reg = <0 0xe6720000 0 0x20000>; 467a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 468a3fb9ff3SMarek Vasut GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 469a3fb9ff3SMarek Vasut GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 470a3fb9ff3SMarek Vasut GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 471a3fb9ff3SMarek Vasut GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 472a3fb9ff3SMarek Vasut GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 473a3fb9ff3SMarek Vasut GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 474a3fb9ff3SMarek Vasut GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 475a3fb9ff3SMarek Vasut GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 476a3fb9ff3SMarek Vasut GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 477a3fb9ff3SMarek Vasut GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 478a3fb9ff3SMarek Vasut GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 479a3fb9ff3SMarek Vasut GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 480a3fb9ff3SMarek Vasut GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 481a3fb9ff3SMarek Vasut GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 482a3fb9ff3SMarek Vasut GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 483a3fb9ff3SMarek Vasut interrupt-names = "error", 484a3fb9ff3SMarek Vasut "ch0", "ch1", "ch2", "ch3", 485a3fb9ff3SMarek Vasut "ch4", "ch5", "ch6", "ch7", 486a3fb9ff3SMarek Vasut "ch8", "ch9", "ch10", "ch11", 487a3fb9ff3SMarek Vasut "ch12", "ch13", "ch14"; 488a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 218>; 489a3fb9ff3SMarek Vasut clock-names = "fck"; 490a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 491a3fb9ff3SMarek Vasut resets = <&cpg 218>; 492a3fb9ff3SMarek Vasut #dma-cells = <1>; 493a3fb9ff3SMarek Vasut dma-channels = <15>; 494a3fb9ff3SMarek Vasut }; 495a3fb9ff3SMarek Vasut 496*252c8b45SMarek Vasut avb: ethernet@e6800000 { 497*252c8b45SMarek Vasut compatible = "renesas,etheravb-r8a7792", 498*252c8b45SMarek Vasut "renesas,etheravb-rcar-gen2"; 499*252c8b45SMarek Vasut reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 500*252c8b45SMarek Vasut interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 501*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 812>; 502*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 503*252c8b45SMarek Vasut resets = <&cpg 812>; 504*252c8b45SMarek Vasut #address-cells = <1>; 505*252c8b45SMarek Vasut #size-cells = <0>; 506*252c8b45SMarek Vasut status = "disabled"; 507*252c8b45SMarek Vasut }; 508*252c8b45SMarek Vasut 509*252c8b45SMarek Vasut qspi: spi@e6b10000 { 510*252c8b45SMarek Vasut compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 511*252c8b45SMarek Vasut reg = <0 0xe6b10000 0 0x2c>; 512*252c8b45SMarek Vasut interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 513*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 917>; 514*252c8b45SMarek Vasut dmas = <&dmac0 0x17>, <&dmac0 0x18>, 515*252c8b45SMarek Vasut <&dmac1 0x17>, <&dmac1 0x18>; 516*252c8b45SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 517*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 518*252c8b45SMarek Vasut resets = <&cpg 917>; 519*252c8b45SMarek Vasut num-cs = <1>; 520*252c8b45SMarek Vasut #address-cells = <1>; 521*252c8b45SMarek Vasut #size-cells = <0>; 522*252c8b45SMarek Vasut status = "disabled"; 523*252c8b45SMarek Vasut }; 524*252c8b45SMarek Vasut 525a3fb9ff3SMarek Vasut scif0: serial@e6e60000 { 526a3fb9ff3SMarek Vasut compatible = "renesas,scif-r8a7792", 527a3fb9ff3SMarek Vasut "renesas,rcar-gen2-scif", "renesas,scif"; 528a3fb9ff3SMarek Vasut reg = <0 0xe6e60000 0 64>; 529a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 530a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 721>, 531a3fb9ff3SMarek Vasut <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 532a3fb9ff3SMarek Vasut clock-names = "fck", "brg_int", "scif_clk"; 533a3fb9ff3SMarek Vasut dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 534a3fb9ff3SMarek Vasut <&dmac1 0x29>, <&dmac1 0x2a>; 535a3fb9ff3SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 536a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 537a3fb9ff3SMarek Vasut resets = <&cpg 721>; 538a3fb9ff3SMarek Vasut status = "disabled"; 539a3fb9ff3SMarek Vasut }; 540a3fb9ff3SMarek Vasut 541a3fb9ff3SMarek Vasut scif1: serial@e6e68000 { 542a3fb9ff3SMarek Vasut compatible = "renesas,scif-r8a7792", 543a3fb9ff3SMarek Vasut "renesas,rcar-gen2-scif", "renesas,scif"; 544a3fb9ff3SMarek Vasut reg = <0 0xe6e68000 0 64>; 545a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 546a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 720>, 547a3fb9ff3SMarek Vasut <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 548a3fb9ff3SMarek Vasut clock-names = "fck", "brg_int", "scif_clk"; 549a3fb9ff3SMarek Vasut dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 550a3fb9ff3SMarek Vasut <&dmac1 0x2d>, <&dmac1 0x2e>; 551a3fb9ff3SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 552a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 553a3fb9ff3SMarek Vasut resets = <&cpg 720>; 554a3fb9ff3SMarek Vasut status = "disabled"; 555a3fb9ff3SMarek Vasut }; 556a3fb9ff3SMarek Vasut 557a3fb9ff3SMarek Vasut scif2: serial@e6e58000 { 558a3fb9ff3SMarek Vasut compatible = "renesas,scif-r8a7792", 559a3fb9ff3SMarek Vasut "renesas,rcar-gen2-scif", "renesas,scif"; 560a3fb9ff3SMarek Vasut reg = <0 0xe6e58000 0 64>; 561a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 562a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 719>, 563a3fb9ff3SMarek Vasut <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 564a3fb9ff3SMarek Vasut clock-names = "fck", "brg_int", "scif_clk"; 565a3fb9ff3SMarek Vasut dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 566a3fb9ff3SMarek Vasut <&dmac1 0x2b>, <&dmac1 0x2c>; 567a3fb9ff3SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 568a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 569a3fb9ff3SMarek Vasut resets = <&cpg 719>; 570a3fb9ff3SMarek Vasut status = "disabled"; 571a3fb9ff3SMarek Vasut }; 572a3fb9ff3SMarek Vasut 573a3fb9ff3SMarek Vasut scif3: serial@e6ea8000 { 574a3fb9ff3SMarek Vasut compatible = "renesas,scif-r8a7792", 575a3fb9ff3SMarek Vasut "renesas,rcar-gen2-scif", "renesas,scif"; 576a3fb9ff3SMarek Vasut reg = <0 0xe6ea8000 0 64>; 577a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 578a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 718>, 579a3fb9ff3SMarek Vasut <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 580a3fb9ff3SMarek Vasut clock-names = "fck", "brg_int", "scif_clk"; 581a3fb9ff3SMarek Vasut dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 582a3fb9ff3SMarek Vasut <&dmac1 0x2f>, <&dmac1 0x30>; 583a3fb9ff3SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 584a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 585a3fb9ff3SMarek Vasut resets = <&cpg 718>; 586a3fb9ff3SMarek Vasut status = "disabled"; 587a3fb9ff3SMarek Vasut }; 588a3fb9ff3SMarek Vasut 589a3fb9ff3SMarek Vasut hscif0: serial@e62c0000 { 590a3fb9ff3SMarek Vasut compatible = "renesas,hscif-r8a7792", 591a3fb9ff3SMarek Vasut "renesas,rcar-gen2-hscif", "renesas,hscif"; 592a3fb9ff3SMarek Vasut reg = <0 0xe62c0000 0 96>; 593a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 594a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 717>, 595a3fb9ff3SMarek Vasut <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 596a3fb9ff3SMarek Vasut clock-names = "fck", "brg_int", "scif_clk"; 597a3fb9ff3SMarek Vasut dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 598a3fb9ff3SMarek Vasut <&dmac1 0x39>, <&dmac1 0x3a>; 599a3fb9ff3SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 600a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 601a3fb9ff3SMarek Vasut resets = <&cpg 717>; 602a3fb9ff3SMarek Vasut status = "disabled"; 603a3fb9ff3SMarek Vasut }; 604a3fb9ff3SMarek Vasut 605a3fb9ff3SMarek Vasut hscif1: serial@e62c8000 { 606a3fb9ff3SMarek Vasut compatible = "renesas,hscif-r8a7792", 607a3fb9ff3SMarek Vasut "renesas,rcar-gen2-hscif", "renesas,hscif"; 608a3fb9ff3SMarek Vasut reg = <0 0xe62c8000 0 96>; 609a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 610a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 716>, 611a3fb9ff3SMarek Vasut <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 612a3fb9ff3SMarek Vasut clock-names = "fck", "brg_int", "scif_clk"; 613a3fb9ff3SMarek Vasut dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 614a3fb9ff3SMarek Vasut <&dmac1 0x4d>, <&dmac1 0x4e>; 615a3fb9ff3SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 616a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 617a3fb9ff3SMarek Vasut resets = <&cpg 716>; 618a3fb9ff3SMarek Vasut status = "disabled"; 619a3fb9ff3SMarek Vasut }; 620a3fb9ff3SMarek Vasut 621a3fb9ff3SMarek Vasut msiof0: spi@e6e20000 { 622a3fb9ff3SMarek Vasut compatible = "renesas,msiof-r8a7792", 623a3fb9ff3SMarek Vasut "renesas,rcar-gen2-msiof"; 624a3fb9ff3SMarek Vasut reg = <0 0xe6e20000 0 0x0064>; 625a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 626a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 000>; 627a3fb9ff3SMarek Vasut dmas = <&dmac0 0x51>, <&dmac0 0x52>, 628a3fb9ff3SMarek Vasut <&dmac1 0x51>, <&dmac1 0x52>; 629a3fb9ff3SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 630a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 631a3fb9ff3SMarek Vasut resets = <&cpg 000>; 632a3fb9ff3SMarek Vasut #address-cells = <1>; 633a3fb9ff3SMarek Vasut #size-cells = <0>; 634a3fb9ff3SMarek Vasut status = "disabled"; 635a3fb9ff3SMarek Vasut }; 636a3fb9ff3SMarek Vasut 637a3fb9ff3SMarek Vasut msiof1: spi@e6e10000 { 638a3fb9ff3SMarek Vasut compatible = "renesas,msiof-r8a7792", 639a3fb9ff3SMarek Vasut "renesas,rcar-gen2-msiof"; 640a3fb9ff3SMarek Vasut reg = <0 0xe6e10000 0 0x0064>; 641a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 642a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 208>; 643a3fb9ff3SMarek Vasut dmas = <&dmac0 0x55>, <&dmac0 0x56>, 644a3fb9ff3SMarek Vasut <&dmac1 0x55>, <&dmac1 0x56>; 645a3fb9ff3SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 646a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 647a3fb9ff3SMarek Vasut resets = <&cpg 208>; 648a3fb9ff3SMarek Vasut #address-cells = <1>; 649a3fb9ff3SMarek Vasut #size-cells = <0>; 650a3fb9ff3SMarek Vasut status = "disabled"; 651a3fb9ff3SMarek Vasut }; 652a3fb9ff3SMarek Vasut 653a3fb9ff3SMarek Vasut can0: can@e6e80000 { 654a3fb9ff3SMarek Vasut compatible = "renesas,can-r8a7792", 655a3fb9ff3SMarek Vasut "renesas,rcar-gen2-can"; 656a3fb9ff3SMarek Vasut reg = <0 0xe6e80000 0 0x1000>; 657a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 658a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 916>, 659a3fb9ff3SMarek Vasut <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 660a3fb9ff3SMarek Vasut clock-names = "clkp1", "clkp2", "can_clk"; 661a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 662a3fb9ff3SMarek Vasut resets = <&cpg 916>; 663a3fb9ff3SMarek Vasut status = "disabled"; 664a3fb9ff3SMarek Vasut }; 665a3fb9ff3SMarek Vasut 666a3fb9ff3SMarek Vasut can1: can@e6e88000 { 667a3fb9ff3SMarek Vasut compatible = "renesas,can-r8a7792", 668a3fb9ff3SMarek Vasut "renesas,rcar-gen2-can"; 669a3fb9ff3SMarek Vasut reg = <0 0xe6e88000 0 0x1000>; 670a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 671a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 915>, 672a3fb9ff3SMarek Vasut <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 673a3fb9ff3SMarek Vasut clock-names = "clkp1", "clkp2", "can_clk"; 674a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 675a3fb9ff3SMarek Vasut resets = <&cpg 915>; 676a3fb9ff3SMarek Vasut status = "disabled"; 677a3fb9ff3SMarek Vasut }; 678a3fb9ff3SMarek Vasut 679a3fb9ff3SMarek Vasut vin0: video@e6ef0000 { 680a3fb9ff3SMarek Vasut compatible = "renesas,vin-r8a7792", 681a3fb9ff3SMarek Vasut "renesas,rcar-gen2-vin"; 682a3fb9ff3SMarek Vasut reg = <0 0xe6ef0000 0 0x1000>; 683a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 684a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 811>; 685a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 686a3fb9ff3SMarek Vasut resets = <&cpg 811>; 687a3fb9ff3SMarek Vasut status = "disabled"; 688a3fb9ff3SMarek Vasut }; 689a3fb9ff3SMarek Vasut 690a3fb9ff3SMarek Vasut vin1: video@e6ef1000 { 691a3fb9ff3SMarek Vasut compatible = "renesas,vin-r8a7792", 692a3fb9ff3SMarek Vasut "renesas,rcar-gen2-vin"; 693a3fb9ff3SMarek Vasut reg = <0 0xe6ef1000 0 0x1000>; 694a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 695a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 810>; 696a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 697a3fb9ff3SMarek Vasut resets = <&cpg 810>; 698a3fb9ff3SMarek Vasut status = "disabled"; 699a3fb9ff3SMarek Vasut }; 700a3fb9ff3SMarek Vasut 701a3fb9ff3SMarek Vasut vin2: video@e6ef2000 { 702a3fb9ff3SMarek Vasut compatible = "renesas,vin-r8a7792", 703a3fb9ff3SMarek Vasut "renesas,rcar-gen2-vin"; 704a3fb9ff3SMarek Vasut reg = <0 0xe6ef2000 0 0x1000>; 705a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 706a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 809>; 707a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 708a3fb9ff3SMarek Vasut resets = <&cpg 809>; 709a3fb9ff3SMarek Vasut status = "disabled"; 710a3fb9ff3SMarek Vasut }; 711a3fb9ff3SMarek Vasut 712a3fb9ff3SMarek Vasut vin3: video@e6ef3000 { 713a3fb9ff3SMarek Vasut compatible = "renesas,vin-r8a7792", 714a3fb9ff3SMarek Vasut "renesas,rcar-gen2-vin"; 715a3fb9ff3SMarek Vasut reg = <0 0xe6ef3000 0 0x1000>; 716a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 717a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 808>; 718a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 719a3fb9ff3SMarek Vasut resets = <&cpg 808>; 720a3fb9ff3SMarek Vasut status = "disabled"; 721a3fb9ff3SMarek Vasut }; 722a3fb9ff3SMarek Vasut 723a3fb9ff3SMarek Vasut vin4: video@e6ef4000 { 724a3fb9ff3SMarek Vasut compatible = "renesas,vin-r8a7792", 725a3fb9ff3SMarek Vasut "renesas,rcar-gen2-vin"; 726a3fb9ff3SMarek Vasut reg = <0 0xe6ef4000 0 0x1000>; 727a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 728a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 805>; 729a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 730a3fb9ff3SMarek Vasut resets = <&cpg 805>; 731a3fb9ff3SMarek Vasut status = "disabled"; 732a3fb9ff3SMarek Vasut }; 733a3fb9ff3SMarek Vasut 734a3fb9ff3SMarek Vasut vin5: video@e6ef5000 { 735a3fb9ff3SMarek Vasut compatible = "renesas,vin-r8a7792", 736a3fb9ff3SMarek Vasut "renesas,rcar-gen2-vin"; 737a3fb9ff3SMarek Vasut reg = <0 0xe6ef5000 0 0x1000>; 738a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 739a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 804>; 740a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 741a3fb9ff3SMarek Vasut resets = <&cpg 804>; 742a3fb9ff3SMarek Vasut status = "disabled"; 743a3fb9ff3SMarek Vasut }; 744a3fb9ff3SMarek Vasut 745*252c8b45SMarek Vasut sdhi0: sd@ee100000 { 746*252c8b45SMarek Vasut compatible = "renesas,sdhi-r8a7792", 747*252c8b45SMarek Vasut "renesas,rcar-gen2-sdhi"; 748*252c8b45SMarek Vasut reg = <0 0xee100000 0 0x328>; 749*252c8b45SMarek Vasut interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 750*252c8b45SMarek Vasut dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 751*252c8b45SMarek Vasut <&dmac1 0xcd>, <&dmac1 0xce>; 752*252c8b45SMarek Vasut dma-names = "tx", "rx", "tx", "rx"; 753*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 314>; 754*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 755*252c8b45SMarek Vasut resets = <&cpg 314>; 756*252c8b45SMarek Vasut status = "disabled"; 757*252c8b45SMarek Vasut }; 758*252c8b45SMarek Vasut 759*252c8b45SMarek Vasut gic: interrupt-controller@f1001000 { 760*252c8b45SMarek Vasut compatible = "arm,gic-400"; 761*252c8b45SMarek Vasut #interrupt-cells = <3>; 762*252c8b45SMarek Vasut interrupt-controller; 763*252c8b45SMarek Vasut reg = <0 0xf1001000 0 0x1000>, 764*252c8b45SMarek Vasut <0 0xf1002000 0 0x2000>, 765*252c8b45SMarek Vasut <0 0xf1004000 0 0x2000>, 766*252c8b45SMarek Vasut <0 0xf1006000 0 0x2000>; 767*252c8b45SMarek Vasut interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 768*252c8b45SMarek Vasut IRQ_TYPE_LEVEL_HIGH)>; 769*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 408>; 770*252c8b45SMarek Vasut clock-names = "clk"; 771*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 772*252c8b45SMarek Vasut resets = <&cpg 408>; 773*252c8b45SMarek Vasut }; 774*252c8b45SMarek Vasut 775a3fb9ff3SMarek Vasut vsp@fe928000 { 776a3fb9ff3SMarek Vasut compatible = "renesas,vsp1"; 777a3fb9ff3SMarek Vasut reg = <0 0xfe928000 0 0x8000>; 778a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 779a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 131>; 780a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 781a3fb9ff3SMarek Vasut resets = <&cpg 131>; 782a3fb9ff3SMarek Vasut }; 783a3fb9ff3SMarek Vasut 784a3fb9ff3SMarek Vasut vsp@fe930000 { 785a3fb9ff3SMarek Vasut compatible = "renesas,vsp1"; 786a3fb9ff3SMarek Vasut reg = <0 0xfe930000 0 0x8000>; 787a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 788a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 128>; 789a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 790a3fb9ff3SMarek Vasut resets = <&cpg 128>; 791a3fb9ff3SMarek Vasut }; 792a3fb9ff3SMarek Vasut 793a3fb9ff3SMarek Vasut vsp@fe938000 { 794a3fb9ff3SMarek Vasut compatible = "renesas,vsp1"; 795a3fb9ff3SMarek Vasut reg = <0 0xfe938000 0 0x8000>; 796a3fb9ff3SMarek Vasut interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 797a3fb9ff3SMarek Vasut clocks = <&cpg CPG_MOD 127>; 798a3fb9ff3SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 799a3fb9ff3SMarek Vasut resets = <&cpg 127>; 800a3fb9ff3SMarek Vasut }; 801a3fb9ff3SMarek Vasut 802*252c8b45SMarek Vasut jpu: jpeg-codec@fe980000 { 803*252c8b45SMarek Vasut compatible = "renesas,jpu-r8a7792", 804*252c8b45SMarek Vasut "renesas,rcar-gen2-jpu"; 805*252c8b45SMarek Vasut reg = <0 0xfe980000 0 0x10300>; 806*252c8b45SMarek Vasut interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 807*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 106>; 808*252c8b45SMarek Vasut power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 809*252c8b45SMarek Vasut resets = <&cpg 106>; 810*252c8b45SMarek Vasut }; 811*252c8b45SMarek Vasut 812*252c8b45SMarek Vasut du: display@feb00000 { 813*252c8b45SMarek Vasut compatible = "renesas,du-r8a7792"; 814*252c8b45SMarek Vasut reg = <0 0xfeb00000 0 0x40000>; 815*252c8b45SMarek Vasut reg-names = "du"; 816*252c8b45SMarek Vasut interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 817*252c8b45SMarek Vasut <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 818*252c8b45SMarek Vasut clocks = <&cpg CPG_MOD 724>, 819*252c8b45SMarek Vasut <&cpg CPG_MOD 723>; 820*252c8b45SMarek Vasut clock-names = "du.0", "du.1"; 821*252c8b45SMarek Vasut status = "disabled"; 822*252c8b45SMarek Vasut 823*252c8b45SMarek Vasut ports { 824*252c8b45SMarek Vasut #address-cells = <1>; 825*252c8b45SMarek Vasut #size-cells = <0>; 826*252c8b45SMarek Vasut 827*252c8b45SMarek Vasut port@0 { 828*252c8b45SMarek Vasut reg = <0>; 829*252c8b45SMarek Vasut du_out_rgb0: endpoint { 830*252c8b45SMarek Vasut }; 831*252c8b45SMarek Vasut }; 832*252c8b45SMarek Vasut port@1 { 833*252c8b45SMarek Vasut reg = <1>; 834*252c8b45SMarek Vasut du_out_rgb1: endpoint { 835*252c8b45SMarek Vasut }; 836*252c8b45SMarek Vasut }; 837a3fb9ff3SMarek Vasut }; 838a3fb9ff3SMarek Vasut }; 839a3fb9ff3SMarek Vasut 840*252c8b45SMarek Vasut prr: chipid@ff000044 { 841*252c8b45SMarek Vasut compatible = "renesas,prr"; 842*252c8b45SMarek Vasut reg = <0 0xff000044 0 4>; 843*252c8b45SMarek Vasut }; 844a3fb9ff3SMarek Vasut }; 845a3fb9ff3SMarek Vasut 846*252c8b45SMarek Vasut timer { 847*252c8b45SMarek Vasut compatible = "arm,armv7-timer"; 848*252c8b45SMarek Vasut interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 849*252c8b45SMarek Vasut <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 850*252c8b45SMarek Vasut <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 851*252c8b45SMarek Vasut <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 852a3fb9ff3SMarek Vasut }; 853a3fb9ff3SMarek Vasut}; 854