1*a500e4e5SMarek Vasut/* 2*a500e4e5SMarek Vasut * Device Tree Source for the Stout board 3*a500e4e5SMarek Vasut * 4*a500e4e5SMarek Vasut * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 5*a500e4e5SMarek Vasut * 6*a500e4e5SMarek Vasut * SPDX-License-Identifier: GPL-2.0 7*a500e4e5SMarek Vasut */ 8*a500e4e5SMarek Vasut 9*a500e4e5SMarek Vasut/dts-v1/; 10*a500e4e5SMarek Vasut#include "r8a7790.dtsi" 11*a500e4e5SMarek Vasut 12*a500e4e5SMarek Vasut/ { 13*a500e4e5SMarek Vasut model = "Stout"; 14*a500e4e5SMarek Vasut compatible = "renesas,stout", "renesas,r8a7790"; 15*a500e4e5SMarek Vasut 16*a500e4e5SMarek Vasut aliases { 17*a500e4e5SMarek Vasut serial0 = &scif0; 18*a500e4e5SMarek Vasut }; 19*a500e4e5SMarek Vasut 20*a500e4e5SMarek Vasut memory@40000000 { 21*a500e4e5SMarek Vasut device_type = "memory"; 22*a500e4e5SMarek Vasut reg = <0 0x40000000 0 0x40000000>; 23*a500e4e5SMarek Vasut }; 24*a500e4e5SMarek Vasut}; 25*a500e4e5SMarek Vasut 26*a500e4e5SMarek Vasut&extal_clk { 27*a500e4e5SMarek Vasut clock-frequency = <20000000>; 28*a500e4e5SMarek Vasut}; 29*a500e4e5SMarek Vasut 30*a500e4e5SMarek Vasut&pfc { 31*a500e4e5SMarek Vasut pinctrl-0 = <&scif_clk_pins>; 32*a500e4e5SMarek Vasut pinctrl-names = "default"; 33*a500e4e5SMarek Vasut 34*a500e4e5SMarek Vasut scif0_pins: scif0 { 35*a500e4e5SMarek Vasut groups = "scif0_data"; 36*a500e4e5SMarek Vasut function = "scif0"; 37*a500e4e5SMarek Vasut }; 38*a500e4e5SMarek Vasut 39*a500e4e5SMarek Vasut scif_clk_pins: scif_clk { 40*a500e4e5SMarek Vasut groups = "scif_clk"; 41*a500e4e5SMarek Vasut function = "scif_clk"; 42*a500e4e5SMarek Vasut }; 43*a500e4e5SMarek Vasut}; 44*a500e4e5SMarek Vasut 45*a500e4e5SMarek Vasut&scif0 { 46*a500e4e5SMarek Vasut pinctrl-0 = <&scif0_pins>; 47*a500e4e5SMarek Vasut pinctrl-names = "default"; 48*a500e4e5SMarek Vasut 49*a500e4e5SMarek Vasut status = "okay"; 50*a500e4e5SMarek Vasut}; 51*a500e4e5SMarek Vasut 52*a500e4e5SMarek Vasut&scif_clk { 53*a500e4e5SMarek Vasut clock-frequency = <14745600>; 54*a500e4e5SMarek Vasut}; 55