1/*
2 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&prm_clocks {
11       corex2_d3_fck: corex2_d3_fck {
12               #clock-cells = <0>;
13               compatible = "fixed-factor-clock";
14               clocks = <&corex2_fck>;
15               clock-mult = <1>;
16               clock-div = <3>;
17       };
18
19       corex2_d5_fck: corex2_d5_fck {
20               #clock-cells = <0>;
21               compatible = "fixed-factor-clock";
22               clocks = <&corex2_fck>;
23               clock-mult = <1>;
24               clock-div = <5>;
25       };
26};
27&cm_clocks {
28       dpll5_ck: dpll5_ck@d04 {
29               #clock-cells = <0>;
30               compatible = "ti,omap3-dpll-clock";
31               clocks = <&sys_ck>, <&sys_ck>;
32               reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
33               ti,low-power-stop;
34               ti,lock;
35       };
36
37       dpll5_m2_ck: dpll5_m2_ck@d50 {
38               #clock-cells = <0>;
39               compatible = "ti,divider-clock";
40               clocks = <&dpll5_ck>;
41               ti,max-div = <31>;
42               reg = <0x0d50>;
43               ti,index-starts-at-one;
44       };
45
46       sgx_gate_fck: sgx_gate_fck@b00 {
47               #clock-cells = <0>;
48               compatible = "ti,composite-gate-clock";
49               clocks = <&core_ck>;
50               ti,bit-shift = <1>;
51               reg = <0x0b00>;
52       };
53
54       core_d3_ck: core_d3_ck {
55               #clock-cells = <0>;
56               compatible = "fixed-factor-clock";
57               clocks = <&core_ck>;
58               clock-mult = <1>;
59               clock-div = <3>;
60       };
61
62       core_d4_ck: core_d4_ck {
63               #clock-cells = <0>;
64               compatible = "fixed-factor-clock";
65               clocks = <&core_ck>;
66               clock-mult = <1>;
67               clock-div = <4>;
68       };
69
70       core_d6_ck: core_d6_ck {
71               #clock-cells = <0>;
72               compatible = "fixed-factor-clock";
73               clocks = <&core_ck>;
74               clock-mult = <1>;
75               clock-div = <6>;
76       };
77
78       omap_192m_alwon_fck: omap_192m_alwon_fck {
79               #clock-cells = <0>;
80               compatible = "fixed-factor-clock";
81               clocks = <&dpll4_m2x2_ck>;
82               clock-mult = <1>;
83               clock-div = <1>;
84       };
85
86       core_d2_ck: core_d2_ck {
87               #clock-cells = <0>;
88               compatible = "fixed-factor-clock";
89               clocks = <&core_ck>;
90               clock-mult = <1>;
91               clock-div = <2>;
92       };
93
94       sgx_mux_fck: sgx_mux_fck@b40 {
95               #clock-cells = <0>;
96               compatible = "ti,composite-mux-clock";
97               clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
98               reg = <0x0b40>;
99       };
100
101       sgx_fck: sgx_fck {
102               #clock-cells = <0>;
103               compatible = "ti,composite-clock";
104               clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
105       };
106
107       sgx_ick: sgx_ick@b10 {
108               #clock-cells = <0>;
109               compatible = "ti,wait-gate-clock";
110               clocks = <&l3_ick>;
111               reg = <0x0b10>;
112               ti,bit-shift = <0>;
113       };
114
115       cpefuse_fck: cpefuse_fck@a08 {
116               #clock-cells = <0>;
117               compatible = "ti,gate-clock";
118               clocks = <&sys_ck>;
119               reg = <0x0a08>;
120               ti,bit-shift = <0>;
121       };
122
123       ts_fck: ts_fck@a08 {
124               #clock-cells = <0>;
125               compatible = "ti,gate-clock";
126               clocks = <&omap_32k_fck>;
127               reg = <0x0a08>;
128               ti,bit-shift = <1>;
129       };
130
131       usbtll_fck: usbtll_fck@a08 {
132               #clock-cells = <0>;
133               compatible = "ti,wait-gate-clock";
134               clocks = <&dpll5_m2_ck>;
135               reg = <0x0a08>;
136               ti,bit-shift = <2>;
137       };
138
139       usbtll_ick: usbtll_ick@a18 {
140               #clock-cells = <0>;
141               compatible = "ti,omap3-interface-clock";
142               clocks = <&core_l4_ick>;
143               reg = <0x0a18>;
144               ti,bit-shift = <2>;
145       };
146
147       mmchs3_ick: mmchs3_ick@a10 {
148               #clock-cells = <0>;
149               compatible = "ti,omap3-interface-clock";
150               clocks = <&core_l4_ick>;
151               reg = <0x0a10>;
152               ti,bit-shift = <30>;
153       };
154
155       mmchs3_fck: mmchs3_fck@a00 {
156               #clock-cells = <0>;
157               compatible = "ti,wait-gate-clock";
158               clocks = <&core_96m_fck>;
159               reg = <0x0a00>;
160               ti,bit-shift = <30>;
161       };
162
163       dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
164               #clock-cells = <0>;
165               compatible = "ti,dss-gate-clock";
166               clocks = <&dpll4_m4x2_ck>;
167               ti,bit-shift = <0>;
168               reg = <0x0e00>;
169               ti,set-rate-parent;
170       };
171
172       dss_ick: dss_ick_3430es2@e10 {
173               #clock-cells = <0>;
174               compatible = "ti,omap3-dss-interface-clock";
175               clocks = <&l4_ick>;
176               reg = <0x0e10>;
177               ti,bit-shift = <0>;
178       };
179
180       usbhost_120m_fck: usbhost_120m_fck@1400 {
181               #clock-cells = <0>;
182               compatible = "ti,gate-clock";
183               clocks = <&dpll5_m2_ck>;
184               reg = <0x1400>;
185               ti,bit-shift = <1>;
186       };
187
188       usbhost_48m_fck: usbhost_48m_fck@1400 {
189               #clock-cells = <0>;
190               compatible = "ti,dss-gate-clock";
191               clocks = <&omap_48m_fck>;
192               reg = <0x1400>;
193               ti,bit-shift = <0>;
194       };
195
196       usbhost_ick: usbhost_ick@1410 {
197               #clock-cells = <0>;
198               compatible = "ti,omap3-dss-interface-clock";
199               clocks = <&l4_ick>;
200               reg = <0x1410>;
201               ti,bit-shift = <0>;
202       };
203};
204
205&cm_clockdomains {
206       dpll5_clkdm: dpll5_clkdm {
207               compatible = "ti,clockdomain";
208               clocks = <&dpll5_ck>;
209       };
210
211       sgx_clkdm: sgx_clkdm {
212               compatible = "ti,clockdomain";
213               clocks = <&sgx_ick>;
214       };
215
216       dss_clkdm: dss_clkdm {
217               compatible = "ti,clockdomain";
218               clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
219                        <&dss1_alwon_fck>, <&dss_ick>;
220       };
221
222       core_l4_clkdm: core_l4_clkdm {
223               compatible = "ti,clockdomain";
224               clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
225                        <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
226                        <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
227                        <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
228                        <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
229                        <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
230                        <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
231                        <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
232                        <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
233                        <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
234                        <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
235       };
236
237       usbhost_clkdm: usbhost_clkdm {
238               compatible = "ti,clockdomain";
239               clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
240                        <&usbhost_ick>;
241       };
242};
243