1*d9be183bSDerald D. Woods/* 2*d9be183bSDerald D. Woods * Device Tree Source for OMAP34xx/OMAP35xx SoC 3*d9be183bSDerald D. Woods * 4*d9be183bSDerald D. Woods * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5*d9be183bSDerald D. Woods * 6*d9be183bSDerald D. Woods * This file is licensed under the terms of the GNU General Public License 7*d9be183bSDerald D. Woods * version 2. This program is licensed "as is" without any warranty of any 8*d9be183bSDerald D. Woods * kind, whether express or implied. 9*d9be183bSDerald D. Woods */ 10*d9be183bSDerald D. Woods 11*d9be183bSDerald D. Woods#include <dt-bindings/media/omap3-isp.h> 12*d9be183bSDerald D. Woods 13*d9be183bSDerald D. Woods#include "omap3.dtsi" 14*d9be183bSDerald D. Woods 15*d9be183bSDerald D. Woods/ { 16*d9be183bSDerald D. Woods cpus { 17*d9be183bSDerald D. Woods cpu: cpu@0 { 18*d9be183bSDerald D. Woods /* OMAP343x/OMAP35xx variants OPP1-5 */ 19*d9be183bSDerald D. Woods operating-points = < 20*d9be183bSDerald D. Woods /* kHz uV */ 21*d9be183bSDerald D. Woods 125000 975000 22*d9be183bSDerald D. Woods 250000 1075000 23*d9be183bSDerald D. Woods 500000 1200000 24*d9be183bSDerald D. Woods 550000 1270000 25*d9be183bSDerald D. Woods 600000 1350000 26*d9be183bSDerald D. Woods >; 27*d9be183bSDerald D. Woods clock-latency = <300000>; /* From legacy driver */ 28*d9be183bSDerald D. Woods }; 29*d9be183bSDerald D. Woods }; 30*d9be183bSDerald D. Woods 31*d9be183bSDerald D. Woods ocp@68000000 { 32*d9be183bSDerald D. Woods omap3_pmx_core2: pinmux@480025d8 { 33*d9be183bSDerald D. Woods compatible = "ti,omap3-padconf", "pinctrl-single"; 34*d9be183bSDerald D. Woods reg = <0x480025d8 0x24>; 35*d9be183bSDerald D. Woods #address-cells = <1>; 36*d9be183bSDerald D. Woods #size-cells = <0>; 37*d9be183bSDerald D. Woods #pinctrl-cells = <1>; 38*d9be183bSDerald D. Woods #interrupt-cells = <1>; 39*d9be183bSDerald D. Woods interrupt-controller; 40*d9be183bSDerald D. Woods pinctrl-single,register-width = <16>; 41*d9be183bSDerald D. Woods pinctrl-single,function-mask = <0xff1f>; 42*d9be183bSDerald D. Woods }; 43*d9be183bSDerald D. Woods 44*d9be183bSDerald D. Woods isp: isp@480bc000 { 45*d9be183bSDerald D. Woods compatible = "ti,omap3-isp"; 46*d9be183bSDerald D. Woods reg = <0x480bc000 0x12fc 47*d9be183bSDerald D. Woods 0x480bd800 0x017c>; 48*d9be183bSDerald D. Woods interrupts = <24>; 49*d9be183bSDerald D. Woods iommus = <&mmu_isp>; 50*d9be183bSDerald D. Woods syscon = <&scm_conf 0x6c>; 51*d9be183bSDerald D. Woods ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>; 52*d9be183bSDerald D. Woods #clock-cells = <1>; 53*d9be183bSDerald D. Woods ports { 54*d9be183bSDerald D. Woods #address-cells = <1>; 55*d9be183bSDerald D. Woods #size-cells = <0>; 56*d9be183bSDerald D. Woods }; 57*d9be183bSDerald D. Woods }; 58*d9be183bSDerald D. Woods 59*d9be183bSDerald D. Woods bandgap: bandgap@48002524 { 60*d9be183bSDerald D. Woods reg = <0x48002524 0x4>; 61*d9be183bSDerald D. Woods compatible = "ti,omap34xx-bandgap"; 62*d9be183bSDerald D. Woods #thermal-sensor-cells = <0>; 63*d9be183bSDerald D. Woods }; 64*d9be183bSDerald D. Woods }; 65*d9be183bSDerald D. Woods 66*d9be183bSDerald D. Woods thermal_zones: thermal-zones { 67*d9be183bSDerald D. Woods #include "omap3-cpu-thermal.dtsi" 68*d9be183bSDerald D. Woods }; 69*d9be183bSDerald D. Woods}; 70*d9be183bSDerald D. Woods 71*d9be183bSDerald D. Woods&ssi { 72*d9be183bSDerald D. Woods status = "ok"; 73*d9be183bSDerald D. Woods 74*d9be183bSDerald D. Woods clocks = <&ssi_ssr_fck>, 75*d9be183bSDerald D. Woods <&ssi_sst_fck>, 76*d9be183bSDerald D. Woods <&ssi_ick>; 77*d9be183bSDerald D. Woods clock-names = "ssi_ssr_fck", 78*d9be183bSDerald D. Woods "ssi_sst_fck", 79*d9be183bSDerald D. Woods "ssi_ick"; 80*d9be183bSDerald D. Woods}; 81*d9be183bSDerald D. Woods 82*d9be183bSDerald D. Woods/include/ "omap34xx-omap36xx-clocks.dtsi" 83*d9be183bSDerald D. Woods/include/ "omap36xx-omap3430es2plus-clocks.dtsi" 84*d9be183bSDerald D. Woods/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 85