1*d9be183bSDerald D. Woods/* 2*d9be183bSDerald D. Woods * Common support for omap3 EVM 35xx/37xx processor modules 3*d9be183bSDerald D. Woods */ 4*d9be183bSDerald D. Woods 5*d9be183bSDerald D. Woods/ { 6*d9be183bSDerald D. Woods memory@80000000 { 7*d9be183bSDerald D. Woods device_type = "memory"; 8*d9be183bSDerald D. Woods reg = <0x80000000 0x10000000>; /* 256 MB */ 9*d9be183bSDerald D. Woods }; 10*d9be183bSDerald D. Woods 11*d9be183bSDerald D. Woods wl12xx_vmmc: wl12xx_vmmc { 12*d9be183bSDerald D. Woods pinctrl-names = "default"; 13*d9be183bSDerald D. Woods pinctrl-0 = <&wl12xx_gpio>; 14*d9be183bSDerald D. Woods }; 15*d9be183bSDerald D. Woods}; 16*d9be183bSDerald D. Woods 17*d9be183bSDerald D. Woods&dss { 18*d9be183bSDerald D. Woods vdds_dsi-supply = <&vpll2>; 19*d9be183bSDerald D. Woods vdda_video-supply = <&lcd_3v3>; 20*d9be183bSDerald D. Woods pinctrl-names = "default"; 21*d9be183bSDerald D. Woods pinctrl-0 = < 22*d9be183bSDerald D. Woods &dss_dpi_pins1 23*d9be183bSDerald D. Woods &dss_dpi_pins2 24*d9be183bSDerald D. Woods >; 25*d9be183bSDerald D. Woods}; 26*d9be183bSDerald D. Woods 27*d9be183bSDerald D. Woods&hsusb2_phy { 28*d9be183bSDerald D. Woods pinctrl-names = "default"; 29*d9be183bSDerald D. Woods pinctrl-0 = <&ehci_phy_pins>; 30*d9be183bSDerald D. Woods}; 31*d9be183bSDerald D. Woods 32*d9be183bSDerald D. Woods&omap3_pmx_core { 33*d9be183bSDerald D. Woods pinctrl-names = "default"; 34*d9be183bSDerald D. Woods pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; 35*d9be183bSDerald D. Woods 36*d9be183bSDerald D. Woods dss_dpi_pins1: pinmux_dss_dpi_pins2 { 37*d9be183bSDerald D. Woods pinctrl-single,pins = < 38*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 39*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 40*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 41*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 42*d9be183bSDerald D. Woods 43*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 44*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 45*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 46*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 47*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 48*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 49*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 50*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 51*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 52*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 53*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 54*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 55*d9be183bSDerald D. Woods 56*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ 57*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ 58*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ 59*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ 60*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ 61*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ 62*d9be183bSDerald D. Woods >; 63*d9be183bSDerald D. Woods }; 64*d9be183bSDerald D. Woods 65*d9be183bSDerald D. Woods mmc1_pins: pinmux_mmc1_pins { 66*d9be183bSDerald D. Woods pinctrl-single,pins = < 67*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 68*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 69*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 70*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 71*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 72*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 73*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ 74*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ 75*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ 76*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ 77*d9be183bSDerald D. Woods >; 78*d9be183bSDerald D. Woods }; 79*d9be183bSDerald D. Woods 80*d9be183bSDerald D. Woods /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ 81*d9be183bSDerald D. Woods mmc2_pins: pinmux_mmc2_pins { 82*d9be183bSDerald D. Woods pinctrl-single,pins = < 83*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 84*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 85*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 86*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 87*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 88*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 89*d9be183bSDerald D. Woods >; 90*d9be183bSDerald D. Woods }; 91*d9be183bSDerald D. Woods 92*d9be183bSDerald D. Woods uart3_pins: pinmux_uart3_pins { 93*d9be183bSDerald D. Woods pinctrl-single,pins = < 94*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 95*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 96*d9be183bSDerald D. Woods >; 97*d9be183bSDerald D. Woods }; 98*d9be183bSDerald D. Woods 99*d9be183bSDerald D. Woods /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ 100*d9be183bSDerald D. Woods on_board_gpio_61: pinmux_ehci_port_select_pins { 101*d9be183bSDerald D. Woods pinctrl-single,pins = < 102*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) 103*d9be183bSDerald D. Woods >; 104*d9be183bSDerald D. Woods }; 105*d9be183bSDerald D. Woods 106*d9be183bSDerald D. Woods /* Used by OHCI and EHCI. OHCI won't work without external phy */ 107*d9be183bSDerald D. Woods hsusb2_pins: pinmux_hsusb2_pins { 108*d9be183bSDerald D. Woods pinctrl-single,pins = < 109*d9be183bSDerald D. Woods 110*d9be183bSDerald D. Woods /* mcspi1_cs3.hsusb2_data2 */ 111*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) 112*d9be183bSDerald D. Woods 113*d9be183bSDerald D. Woods /* mcspi2_clk.hsusb2_data7 */ 114*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) 115*d9be183bSDerald D. Woods 116*d9be183bSDerald D. Woods /* mcspi2_simo.hsusb2_data4 */ 117*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) 118*d9be183bSDerald D. Woods 119*d9be183bSDerald D. Woods /* mcspi2_somi.hsusb2_data5 */ 120*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) 121*d9be183bSDerald D. Woods 122*d9be183bSDerald D. Woods /* mcspi2_cs0.hsusb2_data6 */ 123*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) 124*d9be183bSDerald D. Woods 125*d9be183bSDerald D. Woods /* mcspi2_cs1.hsusb2_data3 */ 126*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) 127*d9be183bSDerald D. Woods >; 128*d9be183bSDerald D. Woods }; 129*d9be183bSDerald D. Woods 130*d9be183bSDerald D. Woods wl12xx_gpio: pinmux_wl12xx_gpio { 131*d9be183bSDerald D. Woods pinctrl-single,pins = < 132*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ 133*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ 134*d9be183bSDerald D. Woods >; 135*d9be183bSDerald D. Woods }; 136*d9be183bSDerald D. Woods 137*d9be183bSDerald D. Woods smsc911x_pins: pinmux_smsc911x_pins { 138*d9be183bSDerald D. Woods pinctrl-single,pins = < 139*d9be183bSDerald D. Woods OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 140*d9be183bSDerald D. Woods >; 141*d9be183bSDerald D. Woods }; 142*d9be183bSDerald D. Woods}; 143*d9be183bSDerald D. Woods 144*d9be183bSDerald D. Woods&omap3_pmx_wkup { 145*d9be183bSDerald D. Woods dss_dpi_pins2: pinmux_dss_dpi_pins1 { 146*d9be183bSDerald D. Woods pinctrl-single,pins = < 147*d9be183bSDerald D. Woods OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ 148*d9be183bSDerald D. Woods OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ 149*d9be183bSDerald D. Woods OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ 150*d9be183bSDerald D. Woods OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ 151*d9be183bSDerald D. Woods OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ 152*d9be183bSDerald D. Woods OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ 153*d9be183bSDerald D. Woods >; 154*d9be183bSDerald D. Woods }; 155*d9be183bSDerald D. Woods}; 156*d9be183bSDerald D. Woods 157*d9be183bSDerald D. Woods&mmc1 { 158*d9be183bSDerald D. Woods pinctrl-names = "default"; 159*d9be183bSDerald D. Woods pinctrl-0 = <&mmc1_pins>; 160*d9be183bSDerald D. Woods}; 161*d9be183bSDerald D. Woods 162*d9be183bSDerald D. Woods&mmc2 { 163*d9be183bSDerald D. Woods pinctrl-names = "default"; 164*d9be183bSDerald D. Woods pinctrl-0 = <&mmc2_pins>; 165*d9be183bSDerald D. Woods}; 166*d9be183bSDerald D. Woods 167*d9be183bSDerald D. Woods&mmc3 { 168*d9be183bSDerald D. Woods status = "disabled"; 169*d9be183bSDerald D. Woods}; 170*d9be183bSDerald D. Woods 171*d9be183bSDerald D. Woods&uart1 { 172*d9be183bSDerald D. Woods interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; 173*d9be183bSDerald D. Woods}; 174*d9be183bSDerald D. Woods 175*d9be183bSDerald D. Woods&uart2 { 176*d9be183bSDerald D. Woods interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; 177*d9be183bSDerald D. Woods}; 178*d9be183bSDerald D. Woods 179*d9be183bSDerald D. Woods&uart3 { 180*d9be183bSDerald D. Woods interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; 181*d9be183bSDerald D. Woods pinctrl-names = "default"; 182*d9be183bSDerald D. Woods pinctrl-0 = <&uart3_pins>; 183*d9be183bSDerald D. Woods}; 184*d9be183bSDerald D. Woods 185*d9be183bSDerald D. Woods/* 186*d9be183bSDerald D. Woods * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface 187*d9be183bSDerald D. Woods * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. 188*d9be183bSDerald D. Woods */ 189*d9be183bSDerald D. Woods&gpio2 { 190*d9be183bSDerald D. Woods en_usb2_port { 191*d9be183bSDerald D. Woods gpio-hog; 192*d9be183bSDerald D. Woods gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ 193*d9be183bSDerald D. Woods output-low; 194*d9be183bSDerald D. Woods line-name = "enable usb2 port"; 195*d9be183bSDerald D. Woods }; 196*d9be183bSDerald D. Woods}; 197*d9be183bSDerald D. Woods 198*d9be183bSDerald D. Woods/* T2_GPIO_2 low to route GPIO_61 to on-board devices */ 199*d9be183bSDerald D. Woods&twl_gpio { 200*d9be183bSDerald D. Woods en_on_board_gpio_61 { 201*d9be183bSDerald D. Woods gpio-hog; 202*d9be183bSDerald D. Woods gpios = <2 GPIO_ACTIVE_HIGH>; 203*d9be183bSDerald D. Woods output-low; 204*d9be183bSDerald D. Woods line-name = "en_hsusb2_clk"; 205*d9be183bSDerald D. Woods }; 206*d9be183bSDerald D. Woods}; 207*d9be183bSDerald D. Woods 208*d9be183bSDerald D. Woods&gpmc { 209*d9be183bSDerald D. Woods ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ 210*d9be183bSDerald D. Woods <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ 211*d9be183bSDerald D. Woods 212*d9be183bSDerald D. Woods ethernet@gpmc { 213*d9be183bSDerald D. Woods pinctrl-names = "default"; 214*d9be183bSDerald D. Woods pinctrl-0 = <&smsc911x_pins>; 215*d9be183bSDerald D. Woods }; 216*d9be183bSDerald D. Woods}; 217