1/* 2 * Copyright (C) 2018 MediaTek Inc. 3 * Author: Ryder Lee <ryder.lee@mediatek.com> 4 * 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 */ 7 8#include <dt-bindings/clock/mt7629-clk.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/mt7629-power.h> 13#include <dt-bindings/reset/mtk-reset.h> 14#include "skeleton.dtsi" 15 16/ { 17 compatible = "mediatek,mt7629"; 18 interrupt-parent = <&sysirq>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 enable-method = "mediatek,mt6589-smp"; 26 27 cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a7"; 30 reg = <0x0>; 31 clock-frequency = <1250000000>; 32 }; 33 34 cpu@1 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a7"; 37 reg = <0x1>; 38 clock-frequency = <1250000000>; 39 }; 40 }; 41 42 clk20m: oscillator@0 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <20000000>; 46 clock-output-names = "clk20m"; 47 }; 48 49 clk40m: oscillator@1 { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <40000000>; 53 clock-output-names = "clkxtal"; 54 }; 55 56 timer { 57 compatible = "arm,armv7-timer"; 58 interrupt-parent = <&gic>; 59 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 60 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 61 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 62 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 63 clock-frequency = <20000000>; 64 arm,cpu-registers-not-fw-configured; 65 }; 66 67 infracfg: syscon@10000000 { 68 compatible = "mediatek,mt7629-infracfg", "syscon"; 69 reg = <0x10000000 0x1000>; 70 #clock-cells = <1>; 71 u-boot,dm-pre-reloc; 72 }; 73 74 pericfg: syscon@10002000 { 75 compatible = "mediatek,mt7629-pericfg", "syscon"; 76 reg = <0x10002000 0x1000>; 77 #clock-cells = <1>; 78 u-boot,dm-pre-reloc; 79 }; 80 81 timer0: timer@10004000 { 82 compatible = "mediatek,timer"; 83 reg = <0x10004000 0x80>; 84 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 85 clocks = <&topckgen CLK_TOP_10M_SEL>, 86 <&topckgen CLK_TOP_CLKXTAL_D4>; 87 clock-names = "mux", "src"; 88 u-boot,dm-pre-reloc; 89 }; 90 91 scpsys: scpsys@10006000 { 92 compatible = "mediatek,mt7629-scpsys"; 93 reg = <0x10006000 0x1000>; 94 clocks = <&topckgen CLK_TOP_HIF_SEL>; 95 clock-names = "hif_sel"; 96 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>; 97 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 98 #power-domain-cells = <1>; 99 infracfg = <&infracfg>; 100 }; 101 102 mcucfg: syscon@10200000 { 103 compatible = "mediatek,mt7629-mcucfg", "syscon"; 104 reg = <0x10200000 0x1000>; 105 #clock-cells = <1>; 106 u-boot,dm-pre-reloc; 107 }; 108 109 sysirq: interrupt-controller@10200a80 { 110 compatible = "mediatek,sysirq"; 111 reg = <0x10200a80 0x20>; 112 interrupt-controller; 113 #interrupt-cells = <3>; 114 interrupt-parent = <&gic>; 115 }; 116 117 dramc: dramc@10203000 { 118 compatible = "mediatek,mt7629-dramc"; 119 reg = <0x10203000 0x600>, /* EMI */ 120 <0x10213000 0x1000>, /* DDRPHY */ 121 <0x10214000 0xd00>; /* DRAMC_AO */ 122 clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>, 123 <&topckgen CLK_TOP_SYSPLL1_D8>, 124 <&topckgen CLK_TOP_MEM_SEL>, 125 <&topckgen CLK_TOP_DMPLL>; 126 clock-names = "phy", "phy_mux", "mem", "mem_mux"; 127 u-boot,dm-pre-reloc; 128 }; 129 130 apmixedsys: clock-controller@10209000 { 131 compatible = "mediatek,mt7629-apmixedsys"; 132 reg = <0x10209000 0x1000>; 133 #clock-cells = <1>; 134 u-boot,dm-pre-reloc; 135 }; 136 137 topckgen: clock-controller@10210000 { 138 compatible = "mediatek,mt7629-topckgen"; 139 reg = <0x10210000 0x1000>; 140 #clock-cells = <1>; 141 u-boot,dm-pre-reloc; 142 }; 143 144 watchdog: watchdog@10212000 { 145 compatible = "mediatek,wdt"; 146 reg = <0x10212000 0x600>; 147 interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>; 148 #reset-cells = <1>; 149 status = "disabled"; 150 }; 151 152 wdt-reboot { 153 compatible = "wdt-reboot"; 154 wdt = <&watchdog>; 155 }; 156 157 pinctrl: pinctrl@10217000 { 158 compatible = "mediatek,mt7629-pinctrl"; 159 reg = <0x10217000 0x8000>; 160 161 gpio: gpio-controller { 162 gpio-controller; 163 #gpio-cells = <2>; 164 }; 165 }; 166 167 gic: interrupt-controller@10300000 { 168 compatible = "arm,gic-400"; 169 interrupt-controller; 170 #interrupt-cells = <3>; 171 interrupt-parent = <&gic>; 172 reg = <0x10310000 0x1000>, 173 <0x10320000 0x1000>, 174 <0x10340000 0x2000>, 175 <0x10360000 0x2000>; 176 }; 177 178 uart0: serial@11002000 { 179 compatible = "mediatek,hsuart"; 180 reg = <0x11002000 0x400>; 181 reg-shift = <2>; 182 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 183 clocks = <&topckgen CLK_TOP_UART_SEL>, 184 <&pericfg CLK_PERI_UART0_PD>; 185 clock-names = "baud", "bus"; 186 status = "disabled"; 187 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; 188 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; 189 u-boot,dm-pre-reloc; 190 }; 191 192 uart1: serial@11003000 { 193 compatible = "mediatek,hsuart"; 194 reg = <0x11003000 0x400>; 195 reg-shift = <2>; 196 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 197 clocks = <&topckgen CLK_TOP_UART_SEL>, 198 <&pericfg CLK_PERI_UART1_PD>; 199 clock-names = "baud", "bus"; 200 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; 201 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; 202 status = "disabled"; 203 }; 204 205 uart2: serial@11004000 { 206 compatible = "mediatek,hsuart"; 207 reg = <0x11004000 0x400>; 208 reg-shift = <2>; 209 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 210 clocks = <&topckgen CLK_TOP_UART_SEL>, 211 <&pericfg CLK_PERI_UART2_PD>; 212 clock-names = "baud", "bus"; 213 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; 214 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; 215 status = "disabled"; 216 }; 217 218 qspi: qspi@11014000 { 219 compatible = "mediatek,mt7629-qspi"; 220 reg = <0x11014000 0xe0>, <0x30000000 0x10000000>; 221 reg-names = "reg_base", "mem_base"; 222 status = "disabled"; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 u-boot,dm-pre-reloc; 226 }; 227 228 ethsys: syscon@1b000000 { 229 compatible = "mediatek,mt7629-ethsys", "syscon"; 230 reg = <0x1b000000 0x1000>; 231 #clock-cells = <1>; 232 #reset-cells = <1>; 233 }; 234 235 eth: ethernet@1b100000 { 236 compatible = "mediatek,mt7629-eth", "syscon"; 237 reg = <0x1b100000 0x20000>; 238 clocks = <&topckgen CLK_TOP_ETH_SEL>, 239 <&topckgen CLK_TOP_F10M_REF_SEL>, 240 <ðsys CLK_ETH_ESW_EN>, 241 <ðsys CLK_ETH_GP0_EN>, 242 <ðsys CLK_ETH_GP1_EN>, 243 <ðsys CLK_ETH_GP2_EN>, 244 <ðsys CLK_ETH_FE_EN>, 245 <&sgmiisys0 CLK_SGMII_TX_EN>, 246 <&sgmiisys0 CLK_SGMII_RX_EN>, 247 <&sgmiisys0 CLK_SGMII_CDR_REF>, 248 <&sgmiisys0 CLK_SGMII_CDR_FB>, 249 <&sgmiisys1 CLK_SGMII_TX_EN>, 250 <&sgmiisys1 CLK_SGMII_RX_EN>, 251 <&sgmiisys1 CLK_SGMII_CDR_REF>, 252 <&sgmiisys1 CLK_SGMII_CDR_FB>, 253 <&apmixedsys CLK_APMIXED_SGMIPLL>, 254 <&apmixedsys CLK_APMIXED_ETH2PLL>; 255 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", 256 "fe", "sgmii_tx250m", "sgmii_rx250m", 257 "sgmii_cdr_ref", "sgmii_cdr_fb", 258 "sgmii2_tx250m", "sgmii2_rx250m", 259 "sgmii2_cdr_ref", "sgmii2_cdr_fb", 260 "sgmii_ck", "eth2pll"; 261 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, 262 <&topckgen CLK_TOP_F10M_REF_SEL>; 263 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, 264 <&topckgen CLK_TOP_SGMIIPLL_D2>; 265 power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; 266 resets = <ðsys ETHSYS_FE_RST>; 267 reset-names = "fe"; 268 mediatek,ethsys = <ðsys>; 269 mediatek,sgmiisys = <&sgmiisys0>; 270 mediatek,infracfg = <&infracfg>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 status = "disabled"; 274 }; 275 276 sgmiisys0: syscon@1b128000 { 277 compatible = "mediatek,mt7629-sgmiisys", "syscon"; 278 reg = <0x1b128000 0x1000>; 279 #clock-cells = <1>; 280 }; 281 282 sgmiisys1: syscon@1b130000 { 283 compatible = "mediatek,mt7629-sgmiisys", "syscon"; 284 reg = <0x1b130000 0x1000>; 285 #clock-cells = <1>; 286 }; 287}; 288