xref: /openbmc/u-boot/arch/arm/dts/meson-gxbb.dtsi (revision d9b23e26) 
1/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This library is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This library is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "meson-gx.dtsi"
44#include <dt-bindings/gpio/meson-gxbb-gpio.h>
45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
46#include <dt-bindings/clock/gxbb-clkc.h>
47#include <dt-bindings/clock/gxbb-aoclkc.h>
48#include <dt-bindings/reset/gxbb-aoclkc.h>
49
50/ {
51	compatible = "amlogic,meson-gxbb";
52
53	soc {
54		usb0_phy: phy@c0000000 {
55			compatible = "amlogic,meson-gxbb-usb2-phy";
56			#phy-cells = <0>;
57			reg = <0x0 0xc0000000 0x0 0x20>;
58			resets = <&reset RESET_USB_OTG>;
59			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
60			clock-names = "usb_general", "usb";
61			status = "disabled";
62		};
63
64		usb1_phy: phy@c0000020 {
65			compatible = "amlogic,meson-gxbb-usb2-phy";
66			#phy-cells = <0>;
67			reg = <0x0 0xc0000020 0x0 0x20>;
68			resets = <&reset RESET_USB_OTG>;
69			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
70			clock-names = "usb_general", "usb";
71			status = "disabled";
72		};
73
74		usb0: usb@c9000000 {
75			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
76			reg = <0x0 0xc9000000 0x0 0x40000>;
77			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
78			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
79			clock-names = "otg";
80			phys = <&usb0_phy>;
81			phy-names = "usb2-phy";
82			dr_mode = "host";
83			status = "disabled";
84		};
85
86		usb1: usb@c9100000 {
87			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
88			reg = <0x0 0xc9100000 0x0 0x40000>;
89			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
90			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
91			clock-names = "otg";
92			phys = <&usb1_phy>;
93			phy-names = "usb2-phy";
94			dr_mode = "host";
95			status = "disabled";
96		};
97	};
98};
99
100&ethmac {
101	clocks = <&clkc CLKID_ETH>,
102		 <&clkc CLKID_FCLK_DIV2>,
103		 <&clkc CLKID_MPLL2>;
104	clock-names = "stmmaceth", "clkin0", "clkin1";
105};
106
107&aobus {
108	pinctrl_aobus: pinctrl@14 {
109		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
110		#address-cells = <2>;
111		#size-cells = <2>;
112		ranges;
113
114		gpio_ao: bank@14 {
115			reg = <0x0 0x00014 0x0 0x8>,
116			      <0x0 0x0002c 0x0 0x4>,
117			      <0x0 0x00024 0x0 0x8>;
118			reg-names = "mux", "pull", "gpio";
119			gpio-controller;
120			#gpio-cells = <2>;
121			gpio-ranges = <&pinctrl_aobus 0 0 14>;
122		};
123
124		uart_ao_a_pins: uart_ao_a {
125			mux {
126				groups = "uart_tx_ao_a", "uart_rx_ao_a";
127				function = "uart_ao";
128			};
129		};
130
131		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
132			mux {
133				groups = "uart_cts_ao_a",
134				       "uart_rts_ao_a";
135				function = "uart_ao";
136			};
137		};
138
139		uart_ao_b_pins: uart_ao_b {
140			mux {
141				groups = "uart_tx_ao_b", "uart_rx_ao_b";
142				function = "uart_ao_b";
143			};
144		};
145
146		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
147			mux {
148				groups = "uart_cts_ao_b",
149				       "uart_rts_ao_b";
150				function = "uart_ao_b";
151			};
152		};
153
154		remote_input_ao_pins: remote_input_ao {
155			mux {
156				groups = "remote_input_ao";
157				function = "remote_input_ao";
158			};
159		};
160
161		i2c_ao_pins: i2c_ao {
162			mux {
163				groups = "i2c_sck_ao",
164				       "i2c_sda_ao";
165				function = "i2c_ao";
166			};
167		};
168
169		pwm_ao_a_3_pins: pwm_ao_a_3 {
170			mux {
171				groups = "pwm_ao_a_3";
172				function = "pwm_ao_a_3";
173			};
174		};
175
176		pwm_ao_a_6_pins: pwm_ao_a_6 {
177			mux {
178				groups = "pwm_ao_a_6";
179				function = "pwm_ao_a_6";
180			};
181		};
182
183		pwm_ao_a_12_pins: pwm_ao_a_12 {
184			mux {
185				groups = "pwm_ao_a_12";
186				function = "pwm_ao_a_12";
187			};
188		};
189
190		pwm_ao_b_pins: pwm_ao_b {
191			mux {
192				groups = "pwm_ao_b";
193				function = "pwm_ao_b";
194			};
195		};
196
197		i2s_am_clk_pins: i2s_am_clk {
198			mux {
199				groups = "i2s_am_clk";
200				function = "i2s_out_ao";
201			};
202		};
203
204		i2s_out_ao_clk_pins: i2s_out_ao_clk {
205			mux {
206				groups = "i2s_out_ao_clk";
207				function = "i2s_out_ao";
208			};
209		};
210
211		i2s_out_lr_clk_pins: i2s_out_lr_clk {
212			mux {
213				groups = "i2s_out_lr_clk";
214				function = "i2s_out_ao";
215			};
216		};
217
218		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
219			mux {
220				groups = "i2s_out_ch01_ao";
221				function = "i2s_out_ao";
222			};
223		};
224
225		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
226			mux {
227				groups = "i2s_out_ch23_ao";
228				function = "i2s_out_ao";
229			};
230		};
231
232		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
233			mux {
234				groups = "i2s_out_ch45_ao";
235				function = "i2s_out_ao";
236			};
237		};
238
239		spdif_out_ao_6_pins: spdif_out_ao_6 {
240			mux {
241				groups = "spdif_out_ao_6";
242				function = "spdif_out_ao";
243			};
244		};
245
246		spdif_out_ao_13_pins: spdif_out_ao_13 {
247			mux {
248				groups = "spdif_out_ao_13";
249				function = "spdif_out_ao";
250			};
251		};
252	};
253};
254
255&periphs {
256	pinctrl_periphs: pinctrl@4b0 {
257		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
258		#address-cells = <2>;
259		#size-cells = <2>;
260		ranges;
261
262		gpio: bank@4b0 {
263			reg = <0x0 0x004b0 0x0 0x28>,
264			      <0x0 0x004e8 0x0 0x14>,
265			      <0x0 0x00120 0x0 0x14>,
266			      <0x0 0x00430 0x0 0x40>;
267			reg-names = "mux", "pull", "pull-enable", "gpio";
268			gpio-controller;
269			#gpio-cells = <2>;
270			gpio-ranges = <&pinctrl_periphs 0 14 120>;
271		};
272
273		emmc_pins: emmc {
274			mux {
275				groups = "emmc_nand_d07",
276				       "emmc_cmd",
277				       "emmc_clk",
278				       "emmc_ds";
279				function = "emmc";
280			};
281		};
282
283		nor_pins: nor {
284			mux {
285				groups = "nor_d",
286				       "nor_q",
287				       "nor_c",
288				       "nor_cs";
289				function = "nor";
290			};
291		};
292
293		sdcard_pins: sdcard {
294			mux {
295				groups = "sdcard_d0",
296				       "sdcard_d1",
297				       "sdcard_d2",
298				       "sdcard_d3",
299				       "sdcard_cmd",
300				       "sdcard_clk";
301				function = "sdcard";
302			};
303		};
304
305		sdio_pins: sdio {
306			mux {
307				groups = "sdio_d0",
308				       "sdio_d1",
309				       "sdio_d2",
310				       "sdio_d3",
311				       "sdio_cmd",
312				       "sdio_clk";
313				function = "sdio";
314			};
315		};
316
317		sdio_irq_pins: sdio_irq {
318			mux {
319				groups = "sdio_irq";
320				function = "sdio";
321			};
322		};
323
324		uart_a_pins: uart_a {
325			mux {
326				groups = "uart_tx_a",
327				       "uart_rx_a";
328				function = "uart_a";
329			};
330		};
331
332		uart_a_cts_rts_pins: uart_a_cts_rts {
333			mux {
334				groups = "uart_cts_a",
335				       "uart_rts_a";
336				function = "uart_a";
337			};
338		};
339
340		uart_b_pins: uart_b {
341			mux {
342				groups = "uart_tx_b",
343				       "uart_rx_b";
344				function = "uart_b";
345			};
346		};
347
348		uart_b_cts_rts_pins: uart_b_cts_rts {
349			mux {
350				groups = "uart_cts_b",
351				       "uart_rts_b";
352				function = "uart_b";
353			};
354		};
355
356		uart_c_pins: uart_c {
357			mux {
358				groups = "uart_tx_c",
359				       "uart_rx_c";
360				function = "uart_c";
361			};
362		};
363
364		uart_c_cts_rts_pins: uart_c_cts_rts {
365			mux {
366				groups = "uart_cts_c",
367				       "uart_rts_c";
368				function = "uart_c";
369			};
370		};
371
372		i2c_a_pins: i2c_a {
373			mux {
374				groups = "i2c_sck_a",
375				       "i2c_sda_a";
376				function = "i2c_a";
377			};
378		};
379
380		i2c_b_pins: i2c_b {
381			mux {
382				groups = "i2c_sck_b",
383				       "i2c_sda_b";
384				function = "i2c_b";
385			};
386		};
387
388		i2c_c_pins: i2c_c {
389			mux {
390				groups = "i2c_sck_c",
391				       "i2c_sda_c";
392				function = "i2c_c";
393			};
394		};
395
396		eth_rgmii_pins: eth-rgmii {
397			mux {
398				groups = "eth_mdio",
399				       "eth_mdc",
400				       "eth_clk_rx_clk",
401				       "eth_rx_dv",
402				       "eth_rxd0",
403				       "eth_rxd1",
404				       "eth_rxd2",
405				       "eth_rxd3",
406				       "eth_rgmii_tx_clk",
407				       "eth_tx_en",
408				       "eth_txd0",
409				       "eth_txd1",
410				       "eth_txd2",
411				       "eth_txd3";
412				function = "eth";
413			};
414		};
415
416		eth_rmii_pins: eth-rmii {
417			mux {
418				groups = "eth_mdio",
419				       "eth_mdc",
420				       "eth_clk_rx_clk",
421				       "eth_rx_dv",
422				       "eth_rxd0",
423				       "eth_rxd1",
424				       "eth_tx_en",
425				       "eth_txd0",
426				       "eth_txd1";
427				function = "eth";
428			};
429		};
430
431		pwm_a_x_pins: pwm_a_x {
432			mux {
433				groups = "pwm_a_x";
434				function = "pwm_a_x";
435			};
436		};
437
438		pwm_a_y_pins: pwm_a_y {
439			mux {
440				groups = "pwm_a_y";
441				function = "pwm_a_y";
442			};
443		};
444
445		pwm_b_pins: pwm_b {
446			mux {
447				groups = "pwm_b";
448				function = "pwm_b";
449			};
450		};
451
452		pwm_d_pins: pwm_d {
453			mux {
454				groups = "pwm_d";
455				function = "pwm_d";
456			};
457		};
458
459		pwm_e_pins: pwm_e {
460			mux {
461				groups = "pwm_e";
462				function = "pwm_e";
463			};
464		};
465
466		pwm_f_x_pins: pwm_f_x {
467			mux {
468				groups = "pwm_f_x";
469				function = "pwm_f_x";
470			};
471		};
472
473		pwm_f_y_pins: pwm_f_y {
474			mux {
475				groups = "pwm_f_y";
476				function = "pwm_f_y";
477			};
478		};
479
480		hdmi_hpd_pins: hdmi_hpd {
481			mux {
482				groups = "hdmi_hpd";
483				function = "hdmi_hpd";
484			};
485		};
486
487		hdmi_i2c_pins: hdmi_i2c {
488			mux {
489				groups = "hdmi_sda", "hdmi_scl";
490				function = "hdmi_i2c";
491			};
492		};
493
494		i2sout_ch23_y_pins: i2sout_ch23_y {
495			mux {
496				groups = "i2sout_ch23_y";
497				function = "i2s_out";
498			};
499		};
500
501		i2sout_ch45_y_pins: i2sout_ch45_y {
502			mux {
503				groups = "i2sout_ch45_y";
504				function = "i2s_out";
505			};
506		};
507
508		i2sout_ch67_y_pins: i2sout_ch67_y {
509			mux {
510				groups = "i2sout_ch67_y";
511				function = "i2s_out";
512			};
513		};
514
515		spdif_out_y_pins: spdif_out_y {
516			mux {
517				groups = "spdif_out_y";
518				function = "spdif_out";
519			};
520		};
521	};
522};
523
524&hiubus {
525	clkc: clock-controller@0 {
526		compatible = "amlogic,gxbb-clkc";
527		#clock-cells = <1>;
528		reg = <0x0 0x0 0x0 0x3db>;
529	};
530};
531
532&apb {
533	mali: gpu@c0000 {
534		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
535		reg = <0x0 0xc0000 0x0 0x40000>;
536		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
537			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
538			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
539			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
540			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
541			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
542			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
543			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
544			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
545			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
546		interrupt-names = "gp", "gpmmu", "pp", "pmu",
547			"pp0", "ppmmu0", "pp1", "ppmmu1",
548			"pp2", "ppmmu2";
549		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
550		clock-names = "bus", "core";
551
552		/*
553		 * Mali clocking is provided by two identical clock paths
554		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
555		 * free mux to safely change frequency while running.
556		 */
557		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
558				  <&clkc CLKID_MALI_0>,
559				  <&clkc CLKID_MALI>; /* Glitch free mux */
560		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
561					 <0>, /* Do Nothing */
562					 <&clkc CLKID_MALI_0>;
563		assigned-clock-rates = <0>, /* Do Nothing */
564				       <666666666>,
565				       <0>; /* Do Nothing */
566	};
567};
568
569&i2c_A {
570	clocks = <&clkc CLKID_I2C>;
571};
572
573&i2c_AO {
574	clocks = <&clkc CLKID_AO_I2C>;
575};
576
577&i2c_B {
578	clocks = <&clkc CLKID_I2C>;
579};
580
581&i2c_C {
582	clocks = <&clkc CLKID_I2C>;
583};
584
585&saradc {
586	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
587	clocks = <&xtal>,
588		 <&clkc CLKID_SAR_ADC>,
589		 <&clkc CLKID_SANA>,
590		 <&clkc CLKID_SAR_ADC_CLK>,
591		 <&clkc CLKID_SAR_ADC_SEL>;
592	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
593};
594
595&sd_emmc_a {
596	clocks = <&clkc CLKID_SD_EMMC_A>,
597		 <&xtal>,
598		 <&clkc CLKID_FCLK_DIV2>;
599	clock-names = "core", "clkin0", "clkin1";
600};
601
602&sd_emmc_b {
603	clocks = <&clkc CLKID_SD_EMMC_B>,
604		 <&xtal>,
605		 <&clkc CLKID_FCLK_DIV2>;
606	clock-names = "core", "clkin0", "clkin1";
607};
608
609&sd_emmc_c {
610	clocks = <&clkc CLKID_SD_EMMC_C>,
611		 <&xtal>,
612		 <&clkc CLKID_FCLK_DIV2>;
613	clock-names = "core", "clkin0", "clkin1";
614};
615
616&spifc {
617	clocks = <&clkc CLKID_SPI>;
618};
619
620&vpu {
621	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
622};
623
624&hwrng {
625	clocks = <&clkc CLKID_RNG0>;
626	clock-names = "core";
627};
628
629&hdmi_tx {
630	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
631	resets = <&reset RESET_HDMITX_CAPB3>,
632		 <&reset RESET_HDMI_SYSTEM_RESET>,
633		 <&reset RESET_HDMI_TX>;
634	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
635	clocks = <&clkc CLKID_HDMI_PCLK>,
636		 <&clkc CLKID_CLK81>,
637		 <&clkc CLKID_GCLK_VENCI_INT0>;
638	clock-names = "isfr", "iahb", "venci";
639};
640